EP1522100A1 - Ensemble circuit integre - Google Patents

Ensemble circuit integre

Info

Publication number
EP1522100A1
EP1522100A1 EP03764888A EP03764888A EP1522100A1 EP 1522100 A1 EP1522100 A1 EP 1522100A1 EP 03764888 A EP03764888 A EP 03764888A EP 03764888 A EP03764888 A EP 03764888A EP 1522100 A1 EP1522100 A1 EP 1522100A1
Authority
EP
European Patent Office
Prior art keywords
node
coupled
output connection
circuit arrangement
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03764888A
Other languages
German (de)
English (en)
Inventor
Daniel Kehrer
Herbert Knapp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1522100A1 publication Critical patent/EP1522100A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45562—Indexing scheme relating to differential amplifiers the IC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45638—Indexing scheme relating to differential amplifiers the LC comprising one or more coils
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors

Definitions

  • the invention relates to an integrated circuit arrangement.
  • Bandwidth is usually limited by parasitic capacitances such as, for example, by parasitic capacitances of a data output connection (pad) and by inductances of an output line (bond wire), which is usually connected to the pad.
  • Peaking coils are coils (inductors) which are arranged in the power supply section of an output circuit. Like the design of a circuit for the smallest possible parasitic capacitances, these increase the usable bandwidth of one
  • FIG. 7 A schematic output circuit of a Differential amplifier with integrated peaking coils according to the prior art is shown in FIG. 7.
  • FIG. 7 shows an equivalent circuit diagram of an integrated circuit arrangement 50 according to the prior art, which has a differential amplifier 51 as the output stage.
  • a first data input 1 of the differential amplifier 51 is coupled to the gate of a first transistor 2, one source / drain region of which is coupled to a first node 3 and the second one
  • Source / drain region is coupled to a second node 4.
  • the second node 4 forms a first output connection of the differential amplifier 51.
  • the first node 3 is coupled to a connection of a current source 5 and to a first source / drain region of a second transistor 6.
  • the gate of the second transistor 6 is coupled to a second data input 7, which second data input is different from the first data input 1.
  • the second source / drain region of the second transistor 6 is coupled to a third node 8.
  • the third node 8 forms a second output connection of the differential amplifier 51.
  • the second node 4 is coupled to a first peaking coil 9 and a first line 10, which leads a first line 10 from the first output connection 4 of the differential amplifier 51 to a first data output connection (pad). 52 forms.
  • the first peaking coil 9 is also coupled to a connection of a voltage source 53 by means of a first resistor 11.
  • the third node 8 is coupled to a second peaking coil 12 and a second line 13, which forms a second line 13 from the second output connection 8 of the differential amplifier 51 to a second data output connection (pad) 54.
  • the second peaking Coil 12 is also coupled to the second connection of the voltage source by means of a second resistor 14.
  • the first output connection 4 of the differential amplifier 51 is coupled to a fourth node 15.
  • the fourth node 15 is coupled to a first capacitance 16, which essentially represents the parasitic capacitances of the output circuit (transistor 2).
  • the fourth node 15 is coupled to a fifth node 17.
  • the fifth node 17 is coupled to a second capacitance 18, which essentially represents the parasitic capacitances of the first data output connection 52.
  • the fifth node 17 is coupled to a first data output 19.
  • the second output connection 8 of the differential amplifier 51 is coupled to a sixth node 20.
  • the sixth node 20 is coupled to a third capacitance 21, which essentially represents the parasitic capacitances of the output circuit (transistor 6).
  • the sixth node 20 is coupled to a seventh node 22.
  • the seventh node 22 is coupled to a fourth capacitance 23, which essentially represents the parasitic capacitances of the second data output connection 54.
  • “the seventh node 22 is coupled to a second data output 24th
  • [4] discloses an operational monitoring system for radar systems with a monitoring / reception device located near the radar antenna for obtaining a sample of the transmission signal from the radar transmitter.
  • the invention is based on the problem of increasing the available bandwidth of an output circuit.
  • An integrated circuit arrangement has an output circuit with at least one first output connection and at least one first data output connection.
  • An inductance is connected between the at least first output connection and the at least first data output connection.
  • circuit arrangement which provides a larger usable bandwidth for data signals. This takes place by means of the advantageous formation of a serial inductance in a branch of the circuit which couples the at least first output connection to the at least first data output connection. This inductance forms together with a parasitic capacitance of the
  • a filter that increases the usable bandwidth of the circuit arrangement is clearly shown in the data output connection.
  • the output circuit of the circuit arrangement according to the invention preferably has a second output connection. Furthermore, the circuit arrangement has a second one
  • the first inductance of the circuit arrangement according to the invention is preferably designed such that it forms, together with the first data output connection, a first frequency filter which has a predetermined frequency band
  • the second inductance of the circuit arrangement according to the invention is designed such that it together with the second data output connection forms a second Forms frequency filter, which has the predetermined frequency band.
  • Capacities of the first or second data output connections resulting filters have a resonance frequency which corresponds to the frequency band of the circuit arrangement used.
  • the filter is preferably set up such that the predetermined frequency band is in the range from 1 GHz to 100 GHz lies.
  • the filter is particularly preferably set up such that the frequency band is in the range from 10 GHz to 20 GHz.
  • a filter is preferably formed by means of each parasitic capacitance and by means of a corresponding inductance.
  • the integrated circuit arrangement then has a plurality of frequency filters, which are coupled in series, between the at least first output connection and the at least first data output connection.
  • the frequency filters are each formed from an inductance and a parasitic capacitance, which are caused by electronic components which are coupled into the connection between the output connection of the output circuit and the data output connection. This can e.g. Electrostatic discharge devices (ESD), which are used to protect the integrated circuit arrangement from external charges.
  • ESD Electrostatic discharge devices
  • the output circuit is preferably set up in such a way that a differential signal can be provided at the first output connection and the second output connection.
  • the output circuit provides a differential signal at the first output connection and at the second output connection, the at least one first inductance being coupled to the at least one second inductance.
  • At least one inductor is preferably a monolithic, integrated inductor. All inductors are particularly preferably designed as monolithic, integrated inductors.
  • the output circuit of the integrated circuit arrangement can be any broadband output stage.
  • the output circuit preferably has a differential amplifier or a multiplexer.
  • Figure 1 is a schematic diagram of a
  • Figure 2 is a schematic diagram of a
  • Figure 3 is a schematic circuit diagram of a circuit arrangement according to a third embodiment of the invention.
  • Figure 4 is a schematic circuit diagram of a circuit arrangement according to a fourth embodiment of the invention.
  • Figure 5 is a diagram showing the course of a signal over a frequency of the signal for a circuit arrangement with and without series inductance
  • FIG. 6A shows an eye diagram for a circuit arrangement without peaking coils according to the prior art
  • FIG. 6B shows an eye diagram for a circuit arrangement with peaking coils according to the prior art
  • FIG. 6C shows an eye diagram for a circuit arrangement according to the invention with peaking coils and serial inductors
  • Figure 7 is a schematic diagram of an output stage according to the prior art.
  • FIG. 1 shows a first exemplary embodiment of an integrated circuit arrangement 150 which has a differential amplifier 151 based on CMOS as the output stage.
  • Differential amplifier 151 is coupled to the gate of a first transistor 102, one of which has a source / drain region is coupled to a first node 103 and its second source / drain region is coupled to a second node 104.
  • the second node 104 forms a first output connection of the differential amplifier 151.
  • the first node 103 is coupled to a connection of a current source 105 and to a first source / drain region of a second transistor 106.
  • the gate of the second transistor 106 is coupled to a second data input 107, which second data input 107 is different from the first data input 101.
  • the second source / drain region of the second transistor 106 is coupled to a third node 108.
  • the third node 108 forms a second output connection of the differential amplifier 151.
  • the second node 104 is coupled to a first peaking coil 109 and a first line 110, which leads a first line 110 from the first output connection 104 of the differential amplifier 151 to a first data output connection (pad). 152 forms.
  • the first peaking coil 109 is also coupled to a connection of a voltage source 153 by means of a first resistor 111.
  • the third node 108 is coupled to a second peaking coil 112 and a second line 113, which forms a second line 113 from the second output connection 108 of the differential amplifier 151 to a second data output connection (pad) 154.
  • the second peaking coil 112 is further coupled to the connection of the voltage source 153 by means of a second resistor 114.
  • the first output connection 104 of the differential amplifier 151 is coupled to a fourth node 115.
  • the fourth node 115 is coupled to a first capacitance 116, which in the
  • the fourth Node 115 coupled to a first serial, monolithic inductor 125.
  • the first serial, monolithic inductor 125 is coupled to a fifth node 117.
  • the fifth node 117 is coupled to a second capacitance 118, which essentially represents the parasitic capacitances of the first data output connection 152.
  • the fifth node 117 is coupled to a first data output 119.
  • the second output connection 108 of the differential amplifier 151 is coupled to a sixth node 120.
  • the sixth node 120 is coupled to a third capacitance 121, which essentially represents the parasitic capacitances of the output circuit (transistor 106).
  • the sixth node 20 is coupled to a second serial, monolithic inductor 126.
  • the second serial, monolithic inductor 126 is coupled to a seventh node 122.
  • the seventh node 122 is coupled to a fourth capacitance 123, which essentially represents the parasitic capacitances of the second data output connection 154.
  • the seventh node 122 is coupled to a second data output 124.
  • the first capacitance 116, the second capacitance 118 and the first serial inductance 125 together form a first ⁇ filter.
  • the third capacitance 121, the fourth capacitance 123 and the second serial inductance 126 together form a second ⁇ filter.
  • the usable bandwidth of the output circuit (differential amplifier) is increased by means of these ⁇ filters.
  • the two peaking coils 109 and 112 each have an inductance of 0.25 nH
  • the parasitic capacitances of transistors 102 and 106 are 50 fF
  • the two serial inductors 125 and 126 have an inductance of 0.15 nH.
  • the teaching according to the invention can be used for all broadband output circuits for increasing the bandwidth of the output circuit.
  • FIG. 2 shows the equivalent circuit diagram of a multiplexer 251 based on CMOS as the output stage of the circuit arrangement 250, which has serial, monolithic inductors according to the invention in its output connection.
  • a first data input 201 is coupled to the gate of a first transistor 202, the first source / drain region of which is coupled to a first node 203 and the second source / drain region of which is coupled to a second node 204.
  • the first node 203 is coupled to a first source / drain region of a second transistor 204.
  • the gate of the second transistor 204 is coupled to a second data input 205, which is different from the first data input 201.
  • Transistor 204 is coupled to a sixth node 206. Furthermore, the first node 203 is coupled to a first source / drain region of a third transistor 207. The gate of the third transistor 207 is coupled to a first clock input 208. The second source / drain area of the third
  • Transistor 207 is coupled to a third node 208.
  • the third node 208 is one with a connector Current source 209 and coupled to a first source / drain region of a fourth transistor 210.
  • the gate of the fourth transistor 210 is coupled to a second clock input 211, which second clock input 211 is different from the first 208 clock input.
  • the second source / drain region of the fourth transistor 210 is coupled to a fourth node 212.
  • the fourth node 212 is coupled to a first source / drain region of a fifth transistor 213 and to a first source / drain region of a sixth transistor 214.
  • the gate of the fifth transistor 213 is coupled to a third data input 215.
  • a second source / drain region of the fifth transistor 213 is coupled to a fifth node 216.
  • the fifth node 216 forms a first output terminal 216 of the multiplexer 251.
  • the gate of the sixth transistor 214 is coupled to a fourth data input 217, which is different from the third data input 215.
  • a second source / drain region of the sixth transistor 214 is coupled to the sixth node 206.
  • the sixth node 206 forms a second output connection 206 of the multiplexer 251
  • the second node 204 is coupled to the fifth node 216. Furthermore, the second node 204 is coupled to a first peaking coil 217. The first peaking coil 217 is further coupled to a connection of a voltage source 253 by means of a first resistor 218.
  • the fifth node 216 is also coupled to a first line 219, which forms a first line 219 from the first output connection 216 of the multiplexer 251 to a first data output connection 252
  • the sixth node 206 is also coupled to a second peaking coil 220 and a second line 221, which forms a second line 221 from the second output connection 206 of the multiplexer 251 to a second data output connection 254.
  • the second peaking coil 220 is also coupled to the connection of the voltage source 253 by means of a second resistor 222.
  • the first output port 216 is coupled to a seventh node 223.
  • the seventh node 223 is coupled to a first capacitance 224, which essentially represents the parasitic capacitances of the output circuit (transistors).
  • the seventh node 223 is coupled to a first serial, monolithic inductor 225, which is also coupled to an eighth node 226.
  • the eighth node 226 is coupled to a second capacitance 227, which essentially represents the parasitic capacitances of the first data output connection 252.
  • the eighth node 226 is coupled to a first data output 228.
  • the second output port 206 is coupled to a ninth node 229.
  • the ninth node 229 is coupled to a third capacitance 230, which essentially represents the parasitic capacitances of the output circuit (transistors). Furthermore, the ninth node 229 is coupled to a second serial, monolithic inductor 231, which is further coupled to a tenth node 232.
  • the tenth node 232 is coupled to a fourth capacitance 233, which essentially represents the parasitic capacitances of the second data output connection 254. Furthermore, the tenth node 232 is coupled to a second data output 234.
  • FIG. 3 shows a third exemplary embodiment of the invention. The embodiment is the same as the first
  • the fifth node 117 is coupled to a fifth capacitance 327 and a third serial, monolithic inductor 328.
  • the third serial, monolithic inductor 328 is coupled to an eighth node 329, which is coupled to the first data output 119 and the second capacitance 118.
  • the seventh node 122 is coupled to a sixth capacitance 330 and a fourth serial monolithic inductor 331.
  • the fourth serial, monolithic inductor 331 is coupled to a ninth node 332, which is coupled to the second data output 124 and the fourth capacitance 123.
  • the fifth capacitance 327 and the sixth capacitance 330 represent parasitic capacitances which e.g. caused by electrostatic discharge device (ESD) 333, which ESD are used to protect the integrated circuit arrangement from external charges.
  • ESD electrostatic discharge device
  • a first ⁇ filter is formed by means of the first capacitance 116, the fifth capacitance 327 and the first serial, monolithic inductance 125.
  • a second ⁇ filter is formed by means of the fifth capacitance 327, the second capacitance 118 and the third serial, monolithic inductor 328.
  • a third ⁇ filter is formed by means of the third capacitance 121, the sixth capacitance 330 and the second serial, monolithic inductor 126.
  • the first ⁇ filter is connected in series with the second ⁇ filter.
  • the third ⁇ filter is connected in series with the fourth ⁇ filter.
  • FIG. 4 A fourth exemplary embodiment of the invention is shown in FIG. The embodiment is the same as the first
  • the coupling of the two serial, monolithic inductors has the advantage with a differential output signal, which is provided by the output circuit, that space can be saved with the same available inductance, since the
  • Inductors 125 and 126 are available for both output signals of the output stage.
  • the results of simulations are compared with one another in FIG.
  • the voltage (signal strength) available at the output of the circuit arrangement is plotted against the frequency of the signal.
  • a first simulation 501 was carried out for a circuit arrangement according to the prior art without a serial, monolithic inductance.
  • a second simulation 502 was carried out for a circuit arrangement according to the first exemplary embodiment of the invention. It can be clearly seen that in the invention Circuitry the signal level shows a steeper fall 503 at high frequencies. However, this steeper drop 503 only occurs at higher frequencies than in a circuit arrangement according to the prior art.
  • the increase in the signal in the circuit arrangement according to the invention between approximately 30 GHz and approximately 50 GHz means that the available bandwidth is significantly increased.
  • the diagram shows that the use of a serial, monolithic inductance significantly increases the usable bandwidth of an output stage.
  • FIG. 6A shows a so-called eye diagram of a simulated circuit arrangement according to the prior art without peaking coils.
  • the important parameters of a data signal can be derived from the eye diagram.
  • the eye diagram is created by superimposing similar "1" and "0" sequences of the data signal on a screen of an oscilloscope.
  • the overlay of many individual bits usually shows an out of focus image.
  • the cause is the existing overshoot and a signal jitter caused by a band limitation.
  • FIG. 6A shows a relatively flat rise in the signal.
  • the so-called eye therefore has only a relatively small opening.
  • FIG. 6B shows a so-called eye diagram of a simulated circuit arrangement according to the prior art with peaking coils.
  • the eye in FIG. 6B is opened further. This indicates an improvement in the quality of the circuit arrangement.
  • the rise in the signal is still flat or slow. This means that reaching a threshold is what reaching is regarded as a signal, is only achieved after a certain time.
  • FIG. 6C shows a so-called eye diagram of a simulated circuit arrangement according to the first
  • Embodiment of the invention shown.
  • the eye shown is wide open.
  • the increase in the signal in the initial area of the eye is much steeper than in FIG. 6B.
  • the circuit arrangement according to the invention with at least one serial, monolithic inductance significantly increases the usable frequency band. It can also be seen that a sampling rate of the signal and thus a data transmission rate could be increased since the signal jitter is small and the steepness of the rise in the signal is sufficient to increase the sampling rate.
  • the invention provides a circuit arrangement of an output stage, which clearly increases the usable bandwidth of the output stage by means of at least one monolithic inductor, which is connected in series with the output circuit, if the limiting element for the bandwidth is the parasitic capacitances.
  • the invention can be used for all types of broadband output circuits, for example also for driver circuits or latch circuits, which can be designed, for example, in CML technology using bipolar transistors.
  • the invention can also be used for any semiconductor technology, such as SiGe, InP, GaAs or other compound semiconductors, on which inductors can be realized.
  • semiconductor technology such as SiGe, InP, GaAs or other compound semiconductors, on which inductors can be realized.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un ensemble circuit intégré (150) comprenant une inductance série (125, 126) monolithique. L'ensemble circuit intégré (150) comporte un circuit de sortie comprenant au moins une première borne de sortie (104, 108), à laquelle un signal de données peut être fourni, et au moins une première borne de sortie de données (152, 154). Au moins une première inductance série (125, 126) est montée entre la borne ou les bornes de sortie (104, 108) et la borne ou les bornes de sortie de données (152, 154).
EP03764888A 2002-07-12 2003-07-11 Ensemble circuit integre Withdrawn EP1522100A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10231638A DE10231638B4 (de) 2002-07-12 2002-07-12 Integrierte Schaltungsanordnung
DE10231638 2002-07-12
PCT/DE2003/002349 WO2004010501A1 (fr) 2002-07-12 2003-07-11 Ensemble circuit integre

Publications (1)

Publication Number Publication Date
EP1522100A1 true EP1522100A1 (fr) 2005-04-13

Family

ID=29796336

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03764888A Withdrawn EP1522100A1 (fr) 2002-07-12 2003-07-11 Ensemble circuit integre

Country Status (4)

Country Link
US (1) US7576619B2 (fr)
EP (1) EP1522100A1 (fr)
DE (1) DE10231638B4 (fr)
WO (1) WO2004010501A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3433929A1 (fr) * 2016-03-22 2019-01-30 Telefonaktiebolaget LM Ericsson (PUBL) Interface à haute vitesse de basse puissance
CN110995239A (zh) * 2019-10-25 2020-04-10 芯创智（北京）微电子有限公司 一种带阻抗匹配的驱动电路以及工作方法

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DE735656C (de) 1936-10-02 1943-05-22 Siemens Ag Elektrisch gesteuerter Ausloeser fuer Hochleistungsschalter mit selbstanlaufendem Motor
US4145692A (en) * 1977-03-09 1979-03-20 Raytheon Company Radar performance monitor
US4791326A (en) * 1987-01-22 1988-12-13 Intel Corporation Current controlled solid state switch
JPH04107940A (ja) * 1990-08-29 1992-04-09 Hitachi Ltd 半導体装置及びその構成部品
US5519353A (en) 1992-06-09 1996-05-21 At&T Corp. Balanced driver circuit for eliminating inductive noise
US5594324A (en) * 1995-03-31 1997-01-14 Space Systems/Loral, Inc. Stabilized power converter having quantized duty cycle
US6459343B1 (en) * 1999-02-25 2002-10-01 Formfactor, Inc. Integrated circuit interconnect system forming a multi-pole filter
US6323735B1 (en) 2000-05-25 2001-11-27 Silicon Laboratories, Inc. Method and apparatus for synthesizing high-frequency signals utilizing on-package oscillator circuit inductors

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Title
See references of WO2004010501A1 *

Also Published As

Publication number Publication date
US20060232349A1 (en) 2006-10-19
WO2004010501A1 (fr) 2004-01-29
DE10231638A1 (de) 2004-01-29
DE10231638B4 (de) 2011-07-28
US7576619B2 (en) 2009-08-18

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