EP1506580B1 - Cellules de memoire a grille flottante presentant un rapport de couplage ameliore - Google Patents
Cellules de memoire a grille flottante presentant un rapport de couplage ameliore Download PDFInfo
- Publication number
- EP1506580B1 EP1506580B1 EP03712560A EP03712560A EP1506580B1 EP 1506580 B1 EP1506580 B1 EP 1506580B1 EP 03712560 A EP03712560 A EP 03712560A EP 03712560 A EP03712560 A EP 03712560A EP 1506580 B1 EP1506580 B1 EP 1506580B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductive
- control gate
- stack
- layer
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000007667 floating Methods 0.000 title claims abstract description 31
- 230000008878 coupling Effects 0.000 title claims abstract description 21
- 238000010168 coupling process Methods 0.000 title claims abstract description 21
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 21
- 230000015654 memory Effects 0.000 title claims description 17
- 230000001965 increasing effect Effects 0.000 title description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 91
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 229920005591 polysilicon Polymers 0.000 description 28
- 230000008569 process Effects 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000007943 implant Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- -1 phosphorous ions Chemical class 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Definitions
- the present invention relates to a non-volatile floating gate semiconductor memory device with increased floating gate (FG) to control gate (CG) coupling ratio (also called coupling coefficient), a method of forming such semiconductor device and ultra-high density non-volatile memories (NVM) using such semiconductor device.
- NVMs include an EPROM, and EEPROM and a flash memory cell.
- NVMs are used in a wide variety of commercial and military electronic devices and equipment, such as e.g. hand-held telephones, radios and digital cameras.
- the market for these electronic devices continues to demand devices with a lower supply voltage, lower power consumption and a decreased chip size.
- Flash memories or flash memory cells comprise a MOSFET with a (or a plurality of) floating gate(s) between a control gate and a channel region, the floating gate(s) and the control gate being separated by a thin dielectric layer.
- the FG size has been reduced to sub-micron scale. Electrons (or holes) are injected in a floating gate by tunneling through an oxide barrier. Charges stored in the FG modify the device threshold voltage. In this way, data is stored.
- the CG controls the electrical potential of the FG.
- the FG to CG coupling ratio which is related to the areal overlap between the FG and the CG, affects the read/write speed of the flash memory. Furthermore, the better (higher) the coupling ratio, the more the required operation voltage of the memory cell can be reduced.
- a solution for reducing the required CG voltage during program / erase is to increase the capacitive coupling ratio ( ⁇ cg ) between the CG and the FG.
- This solution is adopted for example in US-6069382 .
- a NVM cell is described there, which includes a FG having a bottom surface in contact with a tunnel layer formed on a substrate, a top surface and side wall surfaces oriented along two perpendicular directions of the memory cell.
- a dielectric layer covers at least a portion of the top surface and covers at least a portion of the surfaces oriented along the perpendicular directions.
- a CG overlaps the FG over substantially all of its surface area, the aforementioned dielectric layer separating the two gates galvanically. In this way, the coupling ratio between FG and CG is increased due to the increased overlap area, but also the cell size is increased.
- the present invention provides a non-volatile floating gate semiconductor memory device with an enhanced (increased) floating gate to control gate coupling ratio, comprising:
- the insulating layer may be formed by means of a blanket layer or by means of an insulating spacer. If an insulating spacer is used, the galvanic contact between each conductive spacer and the control gate may be formed by a direct contact between the conductive spacers and the control gate. In both cases (a blanket layer or an insulating spacer as side wall dielectric), the galvanic contact may be made by means of a conductive layer, e.g. a silicide layer, over at least a part of the conductive spacer and at least a part of the control gate. Both the conductive spacer and the control gate may be covered by the conductive layer everywhere where they are not covered by another layer. Insulating spacers may be provided alongside the conductive spacers.
- a conductive layer e.g. a silicide layer
- the present invention also provides a method for manufacturing on a substrate with a planar surface a non-volatile floating gate semiconductor memory device with an enhanced (increased) floating gate to control gate coupling ratio is also provided.
- the method comprises the steps of:
- the semiconductor memory device obtained is smaller than the device obtained by a non-self-aligned process used to make prior art devices.
- the step of forming an insulating layer may comprise depositing a blanket layer or forming insulating spacers. If insulating spacers are formed, the step of forming a galvanic contact may comprise providing a direct contact between a conductive spacer and the control gate. The step of forming a galvanic coupling between each conductive spacer and the control gate may also comprise forming a conductive layer, e.g. by silicidizing, over at least part of the control gate and over at least part of the conductive spacers.
- Insulating spacers may be provided alongside the conductive spacers.
- the present invention also provides a non-volatile memory including a semiconductor memory device according to the present invention.
- the non-volatile memory may for example be a flash memory or an EEPROM.
- Such a non-volatile memory including a semiconductor memory device according to the present invention can be made smaller than prior art non-volatile memories.
- the memory can be programmed and/or erased at lower voltages, thus relaxing the requirements on the high voltage transistors in the peripheral circuit. Alternatively, not using decreased voltages, such non-volatile memory can be used to have faster erase and programming times.
- a substrate 10 or a well in a substrate is provided.
- the term “substrate” may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed.
- this "substrate” may include a semiconductor substrate such as e.g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), a germanium (Ge), or a silicon germanium (SiGe) substrate.
- GaAs gallium arsenide
- GaAsP gallium arsenide phosphide
- Ge germanium
- SiGe silicon germanium
- the "substrate” may include, for example, an insulating layer such as a SiO 2 or an Si 3 N 4 layer in addition to a semiconductor substrate portion.
- the term substrate also includes silicon-on-glass, silicon-on sapphire substrates.
- the term “substrate” is thus used to define generally the elements for layers that underlie a layer or portions of interest.
- the "substrate” may be any other base on which a layer is formed, for example a glass or metal layer.
- the present invention may be implemented based on other semiconductor material systems and that the skilled person can select suitable materials as equivalents of the dielectric and conductive materials described below.
- Fig. 2 is a cross-section in a direction perpendicular to the cross-section of Fig. 1 .
- a tunnel oxide (Tox) layer 12 comprising silicon dioxide, is formed, e.g. by thermally growing it in an oxygen-steam ambient, at a temperature between about 600 to 1000°C, to a thickness between about 6 to 15 5 nm.
- a dry oxidation can be used for growing the tunnel oxide layer 12.
- a first polysilicon layer 14 is deposited, which will later on form the FG.
- the deposition of the first polysilicon layer is preferably done by a CVD procedure, to a thickness between about 50 to 400 nm.
- Doping of the polysilicon layer 14 is either accomplished in situ, during deposition, e.g. via the addition of arsine or phosphine to a silane ambient, or via an ion implantation procedure, using for example arsenic or phosphorous ions applied to an intrinsically polysilicon layer.
- the first polysilicon layer 14 is patterned with slits 15, as illustrated in Fig. 2 . These slits serve to isolate adjacent floating gates from each other (floating gates located on a same wordline but on different bitlines).
- IPD 16 is formed over the FG polysilicon layer 14.
- This IPD 16 comprises a dielectric material such as silicon oxide, and may be deposited via any suitable method such as an LPCVD or a PECVD procedure, to an equivalent oxide thickness (EOT) between about 10 to 30 nm.
- the IPD 16 preferably comprises other insulating materials, e.g. an Oxide Nitride Oxide (ONO) layer, and may be formed or grown by conventional techniques.
- An ONO layer comprises successive layers of silicon dioxide, silicon nitride and silicon dioxide.
- CG polysilicon 18 is deposited.
- the deposition of the CG polysilicon layer 18 may be done by LPCVD procedures, to a thickness between about 50 to 400 nm.
- Doping of the CG polysilicon layer 18 is either accomplished in situ, during deposition, via the addition of a suitable dopant impurity such as arsine or phosphine to a silane ambient, or via an ion implantation procedure, using such a dopant, e.g. arsenic or phosphorous ions applied to an intrinsically polysilicon layer.
- a stack is etched, as shown in Fig. 1 .
- a lightly doped drain (LDD) or medium doped drain (MDD) implant 20 is carried out, i.e. an impurity implantation in the substrate 10 with a dose of the order of 10 13 - 10 14 atoms per cm 2 .
- the purpose of this LDD implant 20 is to create a reduced doping gradient between a drain/source to be formed and a channel under the tunnel oxide 12, which lowers the maximum electric field in the channel in the vicinity of the drain/source.
- a side wall dielectric 22 - for instance (nitrided) silicon oxide - is deposited or grown over the substrate 10 and gate stack 14, 16, 18.
- This can be done as a blanket layer, as shown in Fig. 3 , but alternatively dielectric spacers, such as TEOS spacers, can be used, as shown in Fig. 4 .
- the use of a blanket layer has the advantage that the step coverage is very good.
- the use of a dielectric spacer has the disadvantage that the creation of the bottom insulation of the conductive spacers 24 (between the conductive spacers 24 and source / drain 28,30) requires additional process steps so as to form insulator layer 23.
- a suitable dielectric spacer over-etch may be used, so that the top side wall 25 of the CG is not covered by dielectric spacer 22.
- dielectric spacer 22 instead of TEOS spacers also nitride spacers may be used.
- the side wall dielectric 22 preferably has an electrical thickness of the same order as that of the IPD 16.
- conductive spacers 24 are formed along the gate stack 14, 16, 18. This may be done by first forming a polysilicon layer 26 over the side wall dielectric 22, as shown in Fig. 5 , which is referring to the case in which the side wall dielectric 22 has been formed by a blanket layer ( Fig. 3 ). Thereafter, an anisotropic etch is carried out, using the side wall dielectric 22 for end point detection of the main etch. It is to be noted that this is a self-aligned process without a masking step. The polysilicon spacer etch is followed by an etch removing all the uncovered side wall dielectric 22. The result is shown in Fig. 6 .
- a masking step is needed before anisotropically etching the polysilicon layer 26.
- the polysilicon spacer etch is followed by an etch removing all the uncovered parts of insulator layer 23.
- the polysilicon spacers 24 are insulated from both the floating gate 14 and the control gate 18 by means of the side wall dielectric 22.
- the floating gate 14 is insulated from the polysilicon spacers 24 by means of the TEOS spacer, while the control gate 18 is only partially insulated from the polysilicon spacers 24 (the top side wall 25 of the control gate 18 directly contacts a polysilicon spacer 24).
- the polysilicon spacers 24 can serve as offset spacers for a highly doped drain (HDD) implant, thus forming source and drain regions 28, 30, as shown in Fig. 7 .
- a highly doped implant has an impurity concentration of the order of 10 15 atoms per cm 2 .
- the stacked gate does not overlap with the heavily doped source and drain regions 28, 30.
- the LDD structure 20 ensures a low dopant gradient in the drain channel region, which reduces the maximum electric field in the drain - channel and source - channel interfaces.
- insulating spacers 32 e.g. nitride spacers or TEOS spacers, are formed alongside the polysilicon spacers 24.
- a 0.12 ⁇ m process for example combined TEOS-nitride spacers may be used, the total thickness of the combined spacer being about 80 nm (20 nm TEOS and 60 nm nitride for example).
- the composition and dimensions of the spacers may vary.
- the insulating spacers 32 will prevent bridging between the conductive spacers 24 and the source and drain regions 28, 30 during a subsequent silicidation step, as this would short circuit the CG 18 to the source and drain regions 28, 30. The new situation is shown in Fig. 7 .
- the HDD implant can be done after the formation of the insulating spacers 32, in which case the LDD / MDD region 20 will be longer, as shown in Fig. 8 .
- This approach is easier to integrate into an existing CMOS process, ass HDD implants are normally done after spacer formation.
- the insulating spacers are used to define the HDD offset, as in the embodiment of Fig. 8 , their size is critical. If they only serve to prevent bridging (as in the embodiment of Fig. 7 ), the dimensions are less critical or not critical at all.
- the uncovered silicon and polysilicon areas are provided with a conductive layer 34, for example they may be silicidized.
- the polysilicon spacer 24 is silicidized everywhere where it is not covered by another layer (in casu insulating spacer 32). No bridging across the insulating spacer 32 should occur. Because of the very short distance between the polysilicon spacers 24 and the control gate 18 (the sidewall dielectric 22 preferably has a thickness of less than 30 nm), bridging occurs and the spacers 24 and the CG 18 will be interconnected at the positions labeled B1, B2 in Fig. 9 . It is to be noted that the CG 18 and polysilicon spacers 24 are adjacent along the entire word line length (which is the direction perpendicular to the plane of the paper), which implies that a local absence of bridging does not hamper cell operation.
- a conductive layer (not represented in the drawings) may still be provided, e.g. by silicidizing uncovered silicon and polysilicon areas.
- Fig. 10 A cross section of a layout of a cell according to this embodiment of the present invention, but without supplementary conductive layer, is shown in Fig. 10 .
- FIG. 9 A cross section of a layout of an embodiment of a cell according to the present invention (with blanket layer as side wall dielectric 22) is shown in Fig. 9 . It comprises a conventional stacked gate floating gate transistor on a substrate 10 with a planar surface, the stack 14, 16, 18 having opposite walls extending vertically with respect to the planar surface.
- the device according to the present invention has a conductive spacer 24 at both sides of the stack 14, 16, 18.
- the conductive spacers 24 are galvanically connected to the CG 18, for example by means of a conductive layer 34, e.g. a silicide layer.
- the conductive spacers 24 are separated from the FG 14 by means of a non-conducting layer 22.
- the cell can be programmed and/or erased at lower voltages, thus relaxing the requirements on the high voltage transistors in the peripheral circuit.
- the increased coupling coefficient can be used to have faster erase and programming times.
- the insulating layer 22 between the conductive spacers 24 and the substrate 10 should be able to sustain the high voltages occurring between source or drain regions 28, 30 and CG 18 during program and erase.
- cell architecture in Fig. 9 is a simple 1-transistor flash cell, the same principle can be used for other cell types (e.g. 2-transistor flash cells) as well.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Claims (10)
- Dispositif de mémoire non volatile à semi-conducteur à grille flottante avec un rapport de couplage entre grille flottante et grille de commande, comprenant :- un substrat avec une surface plane,- un empilement comprenant une grille flottante et une grille de commande sur le substrat, l'empilement ayant deux parois opposées s'étendant pratiquement verticalement par rapport à la surface plane,- un espaceur conducteur associé à chaque paroi opposée de l'empilement,- une couche isolante entre chaque paroi opposée de l'empilement et l'espaceur conducteur correspondant, et- un contact galvanique entre chaque espaceur conducteur et la grille de commande,dans lequel la grille de commande est au moins partiellement isolée des espaceurs conducteurs par la couche isolante.
- Dispositif de mémoire à semi-conducteur selon la revendication 1, dans lequel l'empilement comporte en outre une couche diélectrique.
- Dispositif de mémoire à semi-conducteur selon la revendication 2, dans lequel la couche isolante a une épaisseur électrique du même ordre de grandeur que la couche diélectrique.
- Dispositif de mémoire à semi-conducteur selon la revendication 1, dans lequel la couche isolante est formée au moyen d'une couche de couverture ou au moyen d'un espaceur.
- Dispositif de mémoire à semi-conducteur selon la revendication 1, dans lequel le contact galvanique est formé par un contact direct entre chaque espaceur conducteur et la grille de commande.
- Dispositif de mémoire à semi-conducteur selon la revendication 1, dans lequel le contact galvanique entre les espaceurs conducteurs et la grille de commande est réalisé au moyen d'une couche conductrice au-dessus d'au moins une partie de l'espaceur conducteur et d'au moins une partie de la grille de commande.
- Dispositif de mémoire à semi-conducteur selon la revendication 6, dans lequel la couche conductrice est une couche de siliciure.
- Dispositif de mémoire à semi-conducteur selon la revendication 1, comportant en outre des espaceurs isolants le long des espaceurs conducteurs.
- Procédé de fabrication sur un substrat avec une surface plane d'un dispositif de mémoire non volatile à semi-conducteur à grille flottante avec un rapport de couplage entre grille flottante et grille de commande, comprenant les étapes suivantes :- formation d'un empilement comprenant une grille flottante et une grille de commande sur le substrat, l'empilement ayant deux parois opposées s'étendant pratiquement verticalement par rapport à la surface plane,- formation d'un espaceur conducteur associé à chaque paroi opposée de l'empilement,- formation d'une couche isolante entre chaque paroi opposée de l'empilement et l'espaceur conducteur correspondant, et- formation d'un contact galvanique entre chaque espaceur conducteur et la grille de commande,dans lequel l'étape de formation d'une couche isolante entre chaque paroi opposée de l'empilement et l'espaceur conducteur correspondant comprend la formation d'une couche isolante telle que la grille de commande est au moins partiellement isolée des espaceurs conducteurs par la couche isolante.
- Mémoire non volatile comprenant le dispositif à semi-conducteur selon les revendications 1 à 8.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03712560A EP1506580B1 (fr) | 2002-05-08 | 2003-04-11 | Cellules de memoire a grille flottante presentant un rapport de couplage ameliore |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02076771 | 2002-05-08 | ||
EP02076771 | 2002-05-08 | ||
EP03712560A EP1506580B1 (fr) | 2002-05-08 | 2003-04-11 | Cellules de memoire a grille flottante presentant un rapport de couplage ameliore |
PCT/IB2003/001485 WO2003096431A1 (fr) | 2002-05-08 | 2003-04-11 | Cellules de memoire a grille flottante presentant un rapport de couplage ameliore |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1506580A1 EP1506580A1 (fr) | 2005-02-16 |
EP1506580B1 true EP1506580B1 (fr) | 2010-07-21 |
Family
ID=29414749
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03712560A Expired - Lifetime EP1506580B1 (fr) | 2002-05-08 | 2003-04-11 | Cellules de memoire a grille flottante presentant un rapport de couplage ameliore |
Country Status (9)
Country | Link |
---|---|
US (1) | US7045852B2 (fr) |
EP (1) | EP1506580B1 (fr) |
JP (1) | JP2005524994A (fr) |
CN (1) | CN100533772C (fr) |
AT (1) | ATE475200T1 (fr) |
AU (1) | AU2003216649A1 (fr) |
DE (1) | DE60333452D1 (fr) |
TW (1) | TWI306312B (fr) |
WO (1) | WO2003096431A1 (fr) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7221008B2 (en) * | 2003-10-06 | 2007-05-22 | Sandisk Corporation | Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory |
KR100650369B1 (ko) * | 2004-10-01 | 2006-11-27 | 주식회사 하이닉스반도체 | 폴리실리콘부유측벽을 갖는 비휘발성메모리장치 및 그제조 방법 |
US7381615B2 (en) * | 2004-11-23 | 2008-06-03 | Sandisk Corporation | Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices |
US7416956B2 (en) * | 2004-11-23 | 2008-08-26 | Sandisk Corporation | Self-aligned trench filling for narrow gap isolation regions |
US7319618B2 (en) * | 2005-08-16 | 2008-01-15 | Macronic International Co., Ltd. | Low-k spacer structure for flash memory |
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CN101866691B (zh) * | 2010-04-29 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | 获得快闪存储单元电容耦合率的方法 |
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US5284784A (en) * | 1991-10-02 | 1994-02-08 | National Semiconductor Corporation | Buried bit-line source-side injection flash memory cell |
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US6069382A (en) * | 1998-02-11 | 2000-05-30 | Cypress Semiconductor Corp. | Non-volatile memory cell having a high coupling ratio |
-
2003
- 2003-04-11 JP JP2004504303A patent/JP2005524994A/ja active Pending
- 2003-04-11 WO PCT/IB2003/001485 patent/WO2003096431A1/fr active Application Filing
- 2003-04-11 DE DE60333452T patent/DE60333452D1/de not_active Expired - Lifetime
- 2003-04-11 EP EP03712560A patent/EP1506580B1/fr not_active Expired - Lifetime
- 2003-04-11 AT AT03712560T patent/ATE475200T1/de not_active IP Right Cessation
- 2003-04-11 CN CNB038103206A patent/CN100533772C/zh not_active Expired - Fee Related
- 2003-04-11 US US10/513,874 patent/US7045852B2/en not_active Expired - Lifetime
- 2003-04-11 AU AU2003216649A patent/AU2003216649A1/en not_active Abandoned
- 2003-05-05 TW TW092112230A patent/TWI306312B/zh not_active IP Right Cessation
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US7045852B2 (en) | 2006-05-16 |
WO2003096431A1 (fr) | 2003-11-20 |
CN100533772C (zh) | 2009-08-26 |
US20050218445A1 (en) | 2005-10-06 |
TW200405578A (en) | 2004-04-01 |
EP1506580A1 (fr) | 2005-02-16 |
ATE475200T1 (de) | 2010-08-15 |
DE60333452D1 (de) | 2010-09-02 |
TWI306312B (en) | 2009-02-11 |
CN1653621A (zh) | 2005-08-10 |
AU2003216649A1 (en) | 2003-11-11 |
JP2005524994A (ja) | 2005-08-18 |
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