EP1501071B1 - Methode, ein schwarzes Bild einzufügen, und Vorrichtung zur Anzeige - Google Patents

Methode, ein schwarzes Bild einzufügen, und Vorrichtung zur Anzeige Download PDF

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Publication number
EP1501071B1
EP1501071B1 EP03016980A EP03016980A EP1501071B1 EP 1501071 B1 EP1501071 B1 EP 1501071B1 EP 03016980 A EP03016980 A EP 03016980A EP 03016980 A EP03016980 A EP 03016980A EP 1501071 B1 EP1501071 B1 EP 1501071B1
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EP
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Prior art keywords
black image
transistor
voltage
electrode
line
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EP03016980A
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English (en)
French (fr)
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EP1501071A1 (de
Inventor
Po-Sheng Shih
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Hannstar Display Corp
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Hannstar Display Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen

Definitions

  • the present invention relates to liquid crystal display. More particularly, the present invention relates to black image insertion method and apparatus for display.
  • LCD Liquid crystal display
  • CTR cathode ray tube
  • Fig. 1A is a circuit diagram of a conventional liquid crystal pixel 100.
  • a scanning line 102 periodically switches a switching transistor 112 with enable pulses.
  • a data line 104 writes pixel data into a pixel cell 114 through the switching transistor 112.
  • a first electrode of the pixel cell 114 is connected to the switching transistor 112, and a second electrode of the pixel cell 114 is connected to the common voltage (V com ).
  • the common voltage is equal to a voltage of a common line 106.
  • the circuit further has a storage capacitor 116.
  • One electrode of the storage capacitor 116 is connected to the switching transistor 112, and the other electrode of the storage capacitor 116 is connected to the common line 106. Electric charges stored in the storage capacitor 116 are used to compensate for a leakage current of the pixel cell 114, keeping the voltage of the whole liquid crystal pixel 100 stable.
  • the enable pulses switching the switching transistor 112 are generally generated by a gate driver IC 120, as illustrated in Fig. 1B .
  • the gate driver IC 120 has n gate pins 122 (G 1 -G n ) connected to n scanning line 102 of the liquid crystal display, and sequentially switches n switching transistors 112 respectively coupled to n scanning line 102.
  • Inserting a black image between two adjacent frames requires a frequency of a data driver IC in charge of sending pixel data to double.
  • the high-frequency data driver IC is not only hard to produce but also has a problem of a lack of enough time to send pixel data to liquid crystal pixels.
  • a conventional method for inserting black image is described in " A Novel Wide-Viewing-Angle Motion-Picture LCD, SID'98" published by IBM Japan , and is illustrated in Fig. 2A .
  • a liquid crystal display 200 is divided into an upper screen 202 and a lower screen 204.
  • the two screens receive pixel data respectively from data driver IC 212 and 214, and a gate driver IC 216 controls the receiving order of the upper screen 202 and lower screen 204.
  • This technique published by IBM Japan uses two data driver ICs to improve the problem of high-frequency of the data driver IC.
  • a disadvantage of the technique is that two driver ICs increase cost.
  • a black-insert-ratio of the technique is fixed at 50%, a half display time of the liquid crystal display must be dark, the average brightness of the liquid crystal display therefore is lower, and the efficiency of the liquid crystal display also deteriorates.
  • a time gap between enable pulses 222 and 224 controlling two adjacent scanning line is defined as an enable pulse 226 to control sending of black image data.
  • a liquid crystal display apparatus has scanning lines, signal lines, active elements, pixel electrodes, common lines and opposed electrodes, arranged on one of a pair of substrates.
  • the liquid crystal display apparatus further includes opposed electrodes, pixel electrodes corresponding to the opposed electrodes, and a plurality of second scanning lines different from said scanning lines connected through that active elements to the pixel electrodes.
  • Common lines corresponding to said pixel electrodes are selected between the selection pulse of the scanning line to write the picture signal in said pixel electrode and the selection pulse of said scanning line to display the following image, and a pulse to clear the picture signal applied to said pixel electrode is applied through said selected common lines, thereby inserting a black image.
  • JP 9 127 917 A describes a liquid crystal display device wherein, in addition to a first switching element for write signal application to a liquid crystal picture element, a second switching element for black signal application is provided in parallel to the first switching element.
  • the second switching element is selectively ON to supply a black signal from a black signal supplying part to the liquid crystal picture element through a black signal feed line, and erasing (reset) of the write signal is performed.
  • the circuit having a black image transistor and a black image line makes the pixel cell present a dark state.
  • the gate driver IC commands the switches and the voltages of the switching transistor and the black image transistor to insert a black image between two frames in a liquid crystal display.
  • the circuit is simple, available with one gate driver IC and one data driver IC, and does not generate a problem when inserting black images because of RC delay or too many data lines.
  • the invention attaches a black image transistor to the conventional liquid crystal circuit to control the black image insertion and cooperate with a gate driver IC sending two enable signals to switch separately a switching transistor and the black image transistor.
  • the gate driver IC also can control an equivalent diode, formed by shorting a source and a gate of the black image transistor, to make a crystal pixel present a dark state. A black image is thus displayed on the liquid crystal display.
  • the gate driver IC has gate pins and black image pins.
  • the gate pin is connected to the scanning line to switch the switching transistor, and the black image pin is connected to the black image line to switch the black image transistor and modify the voltage of the black image line.
  • the gate driver IC respectively sends two enable pulses from the gate pins and the black image pins.
  • a time offset exists between the two enable pulses, periods of which are not necessarily equal.
  • the periods of the enable pulses of the black image line and the scanning line are equal, one black image is inserted within every frame. In other words, the frames and the black images are interlaced in a one-to-one relation. Nonetheless, the periods of the enable pulses of the black image line and the scanning line are unequal in some other operating conditions. In those operating conditions, one black image is inserted after several frames and the frames and the black images are Interlaced in a many-to-one relation.
  • the gate pin When the circuit is operating, the gate pin first sends an enable pulse to the switching transistor, pixel data are thus written into the pixel cell, and the black image pin must not turn on the black image transistorat this time. Subsequently, a black image enable pulse sent by the black image pin switches on the black image transistor and the pixel cell therefore presents a dark state because of a voltage of a first electrode of the pixel cell is between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the invention is carried out only with one gate driver IC and one data driver IC, and the frequencies of these two driver ICs need not be raised.
  • the problem of difficulty in producing the ICs because of their high frequency is thus avoided.
  • the starting time point of the black image enable pulse that makes the pixel cell present a dark state can be arbitrarily adjusted, so the black-insert-ratio is not fixed at 50% as in the prior art.
  • Liquid crystal displays utilizing the invention do not sacrifice half their brightness, and the efficiency of liquid crystal displays is thus improved.
  • circuit design in the invention is simple and adjustable.
  • the invention is also useful for large-sized liquid crystal displays having heavy RC delay and high-resolution liquid crystal displays having too many data lines.
  • the invention provides a black image insertion method and apparatus suitable for large-sized or high-resolution liquid crystal displays.
  • the present invention provides black image insertion method and apparatus for display to improve the problem of inserting black images in a liquid crystal display.
  • the invention attaches a black image transistor to the conventional liquid crystal circuit to control the black image insertion, and cooperate with a gate driver IC sending two enable signals to switch a switching transistor and the black image transistor separately.
  • the gate driver IC also can control an equivalent diode, formed by shorting a source and a gate of the black image transistor, to make a crystal pixel present a dark state. A black image is therefore displayed on the liquid crystal display.
  • FIG. 3A illustrates a circuit diagram of the example.
  • a scanning line 302 periodically switches a switching transistor 312 with enable pulses.
  • a data line 304 writes pixel data into a pixel cell 314 through the switching transistor 312.
  • a first electrode of the pixel cell 314 is connected to the switching transistor 312, and a second electrode of the pixel cell 314 is connected to the common voltage (V com ).
  • the common voltage is equal to a voltage of a common line 306.
  • one electrode of a storage capacitor 316 is connected to the switching transistor 312, and the other electrode of the storage capacitor 316 is connected to the common line 306.
  • the example adds a black image transistor 318 and a black image line 308 into the foregoing circuit.
  • a gate of the black image transistor 318 is connected to the black image line 308, a source of the black image transistor 318 is connected to the common line 306, and a drain of the black image transistor 318 is connected to the first electrode of the pixel cell 314.
  • the drain and source of the black image transistor 318 are electrically conducted, such that a voltage of the first electrode of the pixel cell 314 is pulled to a black image voltage range and the pixel cell 314 therefore presents a dark state.
  • the black image voltage range is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the example further provides a gate driver IC.
  • the gate driver IC controls the switching transistor 312 and black image transistor 318 through the scanning line 302 and the black image line 308, respectively, as illustrated in Fig. 3B .
  • the gate driver IC 320 has gate pins 322 (G 1 -G n ) and black image pins 328 (BI 1 -BI n ).
  • the gate pin 322 is connected to the scanning line 302 to switch the switching transistor 312, while the black image pin 328 is connected to the black image line 308 to switch the black image transistor 318 and modify the gate voltage.
  • the gate driver IC 320 respectively sends two enable pulses from the gate pins 322 and the black image pins 328, and therein a black image enable pulse of the black image line 308 is located between two adjacent enable pulses of the scanning line 302.
  • the gate driver IC 320 also can control the voltages of the scanning line 302 and the black image line 308.
  • the black image insertion circuit for display is not limited to operation with the gate driver IC in this embodiment.
  • Other gate driver ICs are also can be used in this invention if they can send a black image enable pulse of the black image line 308 between two adjacent enable pulses of the scanning line 302 and control the voltages of the black image line 308 and scanning line 302.
  • a time offset is designated between the two enable pulses, and periods thereof them are not necessarily equal.
  • the periods of the enable pulses of the black image line 308 and the scanning line 302 are equal, one black image is inserted between every two frames. In other words, the frames and the black images are Interlaced in a one-to-one relation. Nonetheless, the periods of the enable pulses of the black image line 308 and the scanning line 302 are unequal in some other operating conditions. In those operating conditions, one black image is inserted after several frames, the frames and the black images are Interlaced in many-to-one relation.
  • Fig. 3D is a graph for the many-to-one relation of the enable pulses of the scanning line 302 and the black image line 308.
  • a voltage signal 364 of the black image line 308 presents a black image enable pulse 364a.
  • the black image line 308 sends one enable pulse (like the black image enable pulse 364a in Fig. 3D ) after the scanning line 302 sending several enable pulses (like the enable pulses 362a and 362b in Fig. 3D ).
  • the display method of the many-to-one relation of the frames and the black images can be used in any embodiment of the present invention, and are not only limited to this embodiment.
  • Fig. 3C is a graph of voltage versus time in accordance with one embodiment such as the circuit in Fig. 3A while operating. The following descriptions refer simultaneously to Fig. 3C and Fig. 3A .
  • a voltage signal 332 of the scanning line 302 sends an enable pulse to switch on the switching transistor 312, the data line 304 then sends the pixel data to the first electrode of the pixel cell 314 though the switching transistor 312, and a voltage signal 334 of the first electrode is raised to the voltage of the pixel data.
  • a voltage signal 336a of the black image line 308 sends a black image enable pulse to switch on the black image transistor 318.
  • the drain and the source of the black image transistor 318 are electrically conducted, the voltage signal 334 of the first electrode is therefore pulled to a black image voltage range 342, and the pixel cell 314 presents a black state.
  • the black image voltage range 342 is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the voltage signal 334 of the first electrode is pulled to a black image voltage range 342.
  • the voltage of the voltage signal 336a may or may not return to the original voltage, such as area 352, before the starting time point of a next enable pulse of the voltage signal 332 at time 5. Therefore, the gate driver IC 320 has to return the voltage of the black image line 308 to the original voltage at time T 4 .
  • the voltage signal 332 of the scanning line 302 sends the next enable pulse to switch on the switching transistor 312 again, and the data line 304 then sends the next pixel data to the first electrode of the pixel cell 314 through the switching transistor 312.
  • the period of the two starting time points of the two adjacent enable pulses sent by the voltage signal 332 is called a frame time.
  • the foregoing black image enable pulse (at time T 2 ) sent by the voltage signal 336a of the black image line 308 must be between the two adjacent enable pulses, time T 1 and time T 5 , sent by the voltage signal 332 of the scanning line 302.
  • the time T 4 at which the voltage signal 336a modifies the voltage signal 334 must be earlier than the time when the next enable pulse of the voltage signal 332 starts, time T 5 . All circuit conditions are therefore kept the same before any pixel data are sent to the liquid crystal pixel 300.
  • the voltage signal of black image line 308 circuit in Fig. 3A has other operation modes besides the one illustrated in Fig. 3C , as illustrated in Fig. 3E.
  • Fig. 3E is a graph of voltage versus time in accordance with another embodiment exemplified by the circuit in Fig. 3A operating in another way.
  • the main difference between the Fig. 3C and Fig. 3E is the switch-on period of the voltage signal of the black image line 308 after time T 2 .
  • the voltage signal 336b of the black image line 308 in Fig. 3E switches on the black image transistor 318 at time T 2 and then keeps the black image transistor 318 in the switched-on state, until the black image transistor 318 is switched off at time T 3 '.
  • the voltage signal 336b is not like the voltage signal 336a in Fig. 3C , which is only a short pulse from time T 2 to time T 3 .
  • the voltage signal 336b of the black image line 308 sends a black image enable pulse to switch on the black image transistor 318.
  • the drain and the source of the black image transistor 318 are electrically conducted, the voltage signal 334 of the first electrode is therefore pulled to a black image voltage range 342, and the pixel cell 314 presents a black state.
  • the black image voltage range 342 is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the drain and the source of the black image transistor 318 are electrically conducted until the voltage signal 336b switches off the black image transistor 318 at time T 3 '. After that, the voltage signal 332 of the scanning line 302 sends the next enable pulse to switch on the switching transistor 312 again at time T 5 .
  • FIG. 4A illustrates a circuit diagram of a preferred embodiment of the invention.
  • a scanning line 402 periodically switches a switching transistor 412 with enable pulses.
  • a data line 404 writes pixel data into a pixel cell 414 through the switching transistor 412.
  • a first electrode of the pixel cell 414 is connected to the switching transistor 412 and a second electrode of the pixel cell 414 is connected to the common voltage (V com ). Furthermore, one electrode of a storage capacitor 416 is connected to the switching transistor 412 and the other electrode of the storage capacitor 416 is connected to a black image line 408 of the invention.
  • the invention adds a black image transistor 418a and a black image line 408 into the foregoing circuit.
  • a gate and a source of the black image transistor 418a are both connected to the black image line 408, and a drain of the black image transistor 418a is connected to the first electrode of the pixel cell 414.
  • the black image transistor 418a in circuit is equivalent to a diode 418b, as illustrated in Fig. 4B .
  • the diode 418b i.e. the gate and the source of the black image transistor 418a
  • the diodes 418b thus are turned on.
  • the voltage of the black image line 408 then couples with the voltage of the first electrode of the pixel cell 414 so as to pull the voltage of the first electrode of the pixel cell 414 to a black image voltage range.
  • the pixel cell 414 therefore presents a dark state.
  • the black image voltage range is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • This preferred embodiment also provides a gate driver IC as illustrated in Fig. 3B .
  • the gate driver IC controls the switching transistor 412 and black image transistor 418a through the scanning line 402 and the black image line 408, respectively.
  • the gate driver IC 320 has gate pins 322 (G 1 -G n ) and black image pins 328 (BI 1 -BI n ).
  • the gate pin 322 is connected to the scanning line 402 to switch the switching transistor 412
  • the black image pin 328 is connected to the black image line 408 to switch the black image transistor 418a and modify the gate voltage.
  • the gate driver IC 320 respectively sends two enable pulses from the gate pins 322 and the black image pins 328, and a black image enable pulse of the black image line 408 is between two adjacent enable pulses of the scanning line 402.
  • the gate driver IC 320 also can control the voltages of the scanning line 402 and the black image line 408.
  • the black image insertion circuit for display is not limited to operation with the gate driver IC as in this embodiment.
  • Other gate driver ICs also can be used in this invention if they can send a black image enable pulse of the black image line 408 between two adjacent enable pulses of the scanning line 402, and control the voltages of the black image line 408 and scanning line 402.
  • Fig. 4C is a graph of voltage versus time in accordance with one embodiment as exemplified by the circuit in Fig. 4A during operation. The following descriptions refer to Fig. 4C and Fig. 4A .
  • a voltage signal 432 of the scanning line 402 sends an enable pulse to switch on the switching transistor 412
  • the data line 404 then sends the pixel data to the first electrode of the pixel cell 414 though the switching transistor 412
  • a voltage signal 434 of the first electrode is raised to the voltage of the pixel data.
  • the black image transistor 418a in the circuit is equivalent to the diode 418b; the voltage signal 436 therefore must be lower than the voltage signal 434 of the first electrode so as to prevent the black image transistor 418a (i.e. the diode 418b) from being turned on.
  • a voltage signal 436 of the black image line 408 sends a black image enable pulse to switch on the black image transistor 418.
  • the voltage of the black image enable pulse must be higher than the voltage of the pixel data.
  • the black image transistor 418a in the circuit is equivalent to the diode 418b. The diode 418b is therefore turned on and then the voltage signal 434 of the first electrode is then charged to about the voltage signal 436 of the black image line 408.
  • the voltage signal 434 of the first electrode is coupled to a black image voltage range 442 by the voltage signal 436 of the black image line 408, and the pixel cell 414 thus presents a black state.
  • the black image voltage range 442 is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the voltage signal 436 of the black image line 408 in this embodiment couples the voltage signal 434 of the first electrode to a black image voltage range 442.
  • the voltage of the voltage signal 436 may be unable to return to the original voltage (as illustrated by area 452 in Fig. 4C ) before the starting time point of a next enable pulse of the voltage signal 432 (at time T 10 ). Therefore, the gate driver IC 320 has to return the voltage of the black image line 408 to the original voltage at time T 9 .
  • the voltage signal 432 of the scanning line 402 sends the next enable pulse to switch on the switching transistor 412 again, and the data line 404 then sends the next pixel data to the first electrode of the pixel cell 414 through the switching transistor 412.
  • the period of the two starting time points of the two adjacent enable pulses sent by the voltage signal 432 is called a frame time.
  • the foregoing black image enable pulse (at time T 7 ) sent by the voltage signal 436 of the black image line 408 must be between the two adjacent enable pulses (at time T 6 and time T 10 ) sent by the voltage signal 432 of the scanning line 402.
  • the time T 9 that the voltage signal 436 modified must be earlier than the starting time point of the next enable pulse of the voltage signal 432 (at time T 10 ). All circuit conditions are therefore kept the same before any pixel data are sent to the liquid crystal pixel 400.
  • FIG. 5A illustrates a circuit diagram of another preferred embodiment of the invention.
  • a scanning line 502 periodically switches a switching transistor 512 with enable pulses.
  • a data line 504 writes pixel data into a pixel cell 514 through the switching transistor 512.
  • a first electrode of the pixel cell 514 is connected to the switching transistor 512, and a second electrode of the pixel cell 514 is connected to the common voltage (V com ). Furthermore, one electrode of a storage capacitor 516 is connected to the switching transistor 512, and the other electrode of the storage capacitor 516 is connected to a black image line 508 of the invention.
  • the invention adds a black image transistor 518a and a black image line 508 into the foregoing circuit.
  • a gate and a source of the black image transistor 518a are both connected to the first electrode of the pixel cell 514, and a drain of the black image transistor 518a is connected to the black image line 508.
  • the black image transistor 518a in circuit is equivalent to a diode 518b, as illustrated in Fig. 5B .
  • a black image enable pulse is sent from the black image line 508 to the diode 518b (i.e. the drain of the black image transistor 518a), and the voltage of the black image enable pulse is lower than the voltage of the pixel data, the diodes 518b thus are turned on.
  • the voltage of the black image line 508 then couples with the voltage of the first electrode of the pixel cell 514, so as to pull the voltage of the first electrode of the pixel cell 514 to a black image voltage range and the pixel cell 514 therefore presents a dark state.
  • the black image voltage range is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • This preferred embodiment also provides a gate driver IC as illustrated in Fig. 3B .
  • the gate driver IC controls the switching transistor 512 and black image transistor 518a through the scanning line 502 and the black image line 508, respectively.
  • the gate driver IC 320 has gate pins 322 (G 1 -G n ) and black image pins 328 (BI 1 -BI n ).
  • the gate pin 322 is connected to the scanning line 502 to switch the switching transistor 512
  • the black image pin 328 is connected to the black image line 508 to switch the black image transistor 518a and modify the gate voltage.
  • the gate driver IC 320 respectively sends two enable pulses from the gate pins 322 and the black image pins 328, and a black image enable pulse of the black image line 508 is between two adjacent enable pulses of the scanning line 502.
  • the gate driver IC 320 also can control the voltages of the scanning line 502 and the black image line 508.
  • the black image insertion circuit for display is not limited to operation with the gate driver IC as exemplified in this embodiment; other gate driver ICs also can be used in this invention if they can send a black image enable pulse of the black image line 508 between two adjacent enable pulses of the scanning line 502 and control the voltages of the black image line 508 and scanning line 502.
  • Fig. 5C is a graph of voltage versus time in accordance with one embodiment as exemplified by the circuit in Fig. 5A during operation. The following descriptions refer to Fig. 5C and Fig. 5A .
  • a voltage signal 532 of the scanning line 502 sends an enable pulse to switch on the switching transistor 512
  • the data line 504 then sends the pixel data to the first electrode of the pixel cell 514 though the switching transistor 512 and a voltage signal 534 of the first electrode is raised to the voltage of the pixel data.
  • the black image transistor 518a in the circuit is equivalent to the diode 518b.
  • the voltage signal 536 therefore must be higher than the voltage signal 534 of the first electrode so as to prevent the black image transistor 518a (i.e. the diode 518b) from being be turned on.
  • a voltage signal 536 of the black image line 508 sends a black image enable pulse to switch on the black image transistor 518, and the voltage of the black image enable pulse must be lower than the voltage of the pixel data.
  • the black image transistor 518a in the circuit is equivalent to the diode 518b, the diode 518b is therefore turned on, and then the voltage signal 534 of the first electrode is then discharged to about the voltage signal 536 of the black image line 508.
  • the voltage signal 534 of the first electrode is coupled to a black image voltage range 542 by the voltage signal 536 of the black image line 508.
  • the pixel cell 514 thereby presents a black state.
  • the black image voltage range 542 is defined as being between the common voltage V com plus a zero-level gray scale voltage and the common voltage V com minus the zero-level gray scale voltage.
  • the voltage signal 536 of the black image line 508 in this embodiment couples the voltage signal 534 of the first electrode to a black image voltage range 542.
  • the voltage of the voltage signal 536 may be unable to return to the original voltage (as illustrated by area 552 in Fig. 4C ) before the starting time point of a next enable pulse of the voltage signal 532 (at time T 15 ). Therefore, the gate driver IC 320 has to return the voltage of the black image line 508 to the origin voltage at time T 14 .
  • the voltage signal 532 of the scanning line 502 sends the next enable pulse to switch on the switching transistor 512 again, and the data line 504 then sends the next pixel data to the first electrode of the pixel cell 514 through the switching transistor 512.
  • the period of the two starting time points of the two adjacent enable pulses sent by the voltage signal 532 is called a frame time.
  • the foregoing black image enable pulse (at time T 12 ) sent by the voltage signal 536 of the black image line 508 must be between the two adjacent enable pulses (at time T 11 and time T 15 ) sent by the voltage signal 532 of the scanning line 502.
  • the time T 14 that the voltage signal 536 modified must be earlier than the starting time point of the next enable pulse of the voltage signal 532 (at time T 15 ). All circuit conditions are therefore kept the same before any pixel data are sent to the liquid crystal pixel 500.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Claims (10)

  1. Ein Schwarzbild-Einfüge-Verfahren für eine Anzeige, wobei ein Schwarzbild zwischen zwei Rahmen einer Flüssigkristallanzeige eingefügt wird, wobei jeder der Rahmen von einer Mehrzahl von Flüssigkristallzellen (414, 514) angezeigt wird, wobei jede der Flüssigkristallzellen (414, 514) eine erste Elektrode und eine zweite Elektrode aufweist, wobei die erste Elektrode mit einem Schalttransistor (412, 512) verbunden ist und ferner mit einem Schwarzbild-Transistor (418a, 518a) verbunden ist, wobei ein Source-Anschluss und ein Gate-Anschluss des schwarzes-Bild-Transistors (418a) mit einer Schwarzbild-Leitung (408) verbunden sind, während ein Drain-Anschluss des Schwarzbild-Transistors (418a) mit der ersten Elektrode verbunden ist, oder der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (518a) mit der ersten Elektrode verbunden sind, während der Drain-Anschluss des Schwarzbild-Transistors (518a) mit der Schwarzbild-Leitung (508) verbunden ist, wobei eine Mehrzahl von Freigabeimpulsen (432, 532) den Schalttransistor (412, 512) periodisch umschaltet und die zweite Elektrode mit einer konstanten gemeinsamen Spannung (VCOM) verbunden ist, wobei das Schwarzbild-Einfüge-Verfahren aufweist:
    Senden eines der Freigabeimpulse (432, 532) durch eine Abtastleitung (402, 502), die mit einem ersten Anschlussstift eines Gate-Treiber-Schaltkreises verbunden ist, zum Einschalten des Schalttransistors (412, 512), wobei eine Spannung der ersten Elektrode zu einer Datenspannung geändert wird, und
    Senden eines Schwarzbild-Freigabeimpulses (436, 536) durch die Schwarzbild-Leitung (408, 508), die mit einem zweiten Anschlussstift des Gate-Treiber-Schaltkreises verbunden ist, zum Einschalten des Schwarzbild-Transistors (418a, 518a), bevor ein nächster Freigabeimpuls (432, 532) den Schalttransistor (412, 512) wieder einschaltet, und Ändern der Spannung der ersten Elektrode von der Datenspannung zu einer Schwarzbild-Spannung, wobei der Schwarzbild-Freigabeimpuls (436, 536) in Folge einen ersten Pegel, einen zweiten Pegel und einen dritten Pegel aufweist, die ungleich zueinander sind, wobei der dritte Pegel zwischen dem ersten Pegel und dem zweiten Pegel liegt, und wobei, wenn der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (418a) mit der Schwarzbild-Leitung (408) verbunden sind und der Drain-Anschluss des Schwarzbild-Transistors (418a) mit der ersten Elektrode verbunden ist, der erste Pegel niedriger als die Datenspannung (434) ist und der zweite Pegel höher als die Datenspannung (434) ist, wenn der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (518a) mit der ersten Elektrode verbunden sind und der Drain-Anschluss des Schwarzbild-Transistors (518a) mit der Schwarzbild-Leitung (508) verbunden ist, der erste Pegel höher als die Datenspannung (534) ist und der zweite Pegel niedriger als die Datenspannung (534) ist, der erste Pegel zum Ausschalten des Schwarzbild-Transistors (418a, 518a) während des Sendens des Freigabeimpulses (432, 532) zum Einschalten des Schalttransistors (412, 512) vorgesehen ist, der zweite Pegel zum Einschalten des Schwarzbild-Transistors (418a, 518a) vorgesehen ist, der dritte Pegel zum Koppeln der Spannung der ersten Elektrode mit der Schwarzbild-Spannung vorgesehen ist, und es eine erste Zeitverschiebung zwischen dem Freigabeimpuls (432, 532) und dem Schwarzbild-Freigabeimpuls (436, 536) gibt.
  2. Das Schwarzbild-Einfüge-Verfahren gemäß Anspruch 1, wobei die Schwarzbild-Spannung zwischen der konstanten gemeinsamen Spannung (VCOM) plus einer Nullpegel-Grauskalenspannung und der konstanten gemeinsamen Spannung (VCOM) minus der Nullspannungs-Grauskalenspannung liegt.
  3. Das Schwarzbild-Einfüge-Verfahren gemäß Anspruch 1, wobei der dritte Pegel höher als der erste Pegel ist und niedriger als der zweite Pegel ist, wenn der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (418a) mit der Schwarzbild-Leitung (408) verbunden sind und der Drain-Anschluss des Schwarzbild-Transistors (418a) mit der ersten Elektrode verbunden ist.
  4. Das Schwarzbild-Einfüge-Verfahren gemäß Anspruch 1, wobei der dritte Pegel niedriger als der erste Pegel ist und höher als der zweite Pegel ist, wenn der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (518a) mit der ersten Elektrode verbunden sind und der Drain-Anschluss des Schwarzbild-Transistors (518a) mit der Schwarzbild-Leitung (508) verbunden ist.
  5. Das Schwarzbild-Einfüge-Verfahren gemäß Anspruch 1, ferner aufweisend:
    nachdem die Spannung der ersten Elektrode von der Datenspannung zu der Schwarzbild-Spannung geändert wurde und bevor ein weiterer nächster Freigabeimpuls (432, 532) den Schalttransistor (412, 512) einschaltet, Zurückbringen des Schwarzbild-Transistors (418a, 518a) in den Ausschalt-Zustand, wobei es eine ferner zweite Zeitverschiebung zwischen dem weiteren nächsten Freigabeimpuls (432, 532) und dem schwarzes-Bild-Freigabeimpuls (436, 536) gibt.
  6. Das Schwarzbild-Einfüge-Verfahren gemäß Anspruch 1, wobei Perioden des Freigabeimpulses (432, 532) und des Schwarzbild-Freigabeimpulses (436, 536) ungleich sind.
  7. Ein Schwarzbild-Einfüge-Schaltkreis für eine Anzeige, wobei der Schwarzbild-Einfüge-Schaltkreis für eine Anzeige aufweist:
    einen Schalttransistor (412, 512),
    eine Flüssigkristallzelle (414, 514), die eine erste Elektrode und eine zweite Elektrode aufweist, wobei eine konstante gemeinsame Spannung (VCOM) an die zweite Elektrode angelegt wird,
    eine Abtastleitung, die zum Senden eines Freigabeimpulses (432, 532) zum Umschalten des Schalttransistors (412, 512) eingerichtet ist,
    eine Datenleitung (404, 504), die zum Senden von Pixeldaten durch den Schalttransistor (412, 512) an die erste Elektrode eingerichtet ist,
    eine Schwarzbild-Leitung (408, 508), die zum Senden eines Schwarzbild-Freigabeimpulses (436, 536) zum Koppeln mit der Spannung der ersten Elektrode eingerichtet ist,
    einen Speicherkondensator (416, 516), der die erste Elektrode und die Schwarzbild-Leitung (408, 508) miteinander verbindet, und
    einen schwarzes-Bild-Transistor (418a, 518a), der die erste Elektrode und die Schwarzbild-Leitung (408, 508) miteinander verbindet, dadurch gekennzeichnet, dass ein Source-Anschluss und ein Gate-Anschluss des Schwarzbild-Transistors (418a) mit der Schwarzbild-Leitung (408) verbunden sind, während ein Drain-Anschluss des schwarzes-Bild-Transistors (418a) mit der ersten Elektrode verbunden ist, oder der Source-Anschluss und der Gate-Anschluss des Schwarzbild-Transistors (518a) mit der ersten Elektrode verbunden sind, während der Drain-Anschluss des schwarzes-Bild-Transistors (518a) mit der Schwarzbild-Leitung (508) verbunden ist.
  8. Der Schwarzbild-Einfüge-Schaltkreis gemäß Anspruch 7, wobei der Schwarzbild-Einfüge-Schaltkreis ferner einen Gate-Treiber-IC (IC, engl. Integrated Circuit [Integrierter Schaltkreis]) aufweist und der Gate-Treiber-IC aufweist:
    mindestens einen ersten Anschlussstift, der mit der Abtastleitung verbunden ist, wobei der erste Anschlussstift zum Senden eines Freigabesignals zum Umschalten des Schalttransistors (412, 512) eingerichtet ist, und
    mindestens einen zweiten Anschlussstift, der mit der Schwarzbild-Leitung (408, 508) verbunden ist, wobei der zweite Anschlussstift zum Senden der Schwarzbild-Daten an die Schwarzbild-Leitung (408, 508) eingerichtet ist, wobei der erste Anschlussstift und der zweite Anschlussstift jeweils zum Senden des Freigabesignals und der Schwarzbild-Daten eingerichtet sind, so dass es eine vorbestimmte Zeitverschiebung zwischen dem Freigabesignal und den Schwarzbild-Daten gibt.
  9. Der Schwarzbild-Einfüge-Schaltkreis gemäß Anspruch 8, wobei der erste Anschlussstift und der zweite Anschlussstift jeweils zum Senden des Freigabesignals und der Schwarzbild-Daten eingerichtet sind, so dass Perioden des Freigabesignals und der Schwarzbild-Daten gleich sind.
  10. Der Schwarzbild-Einfüge-Schaltkreis gemäß Anspruch 8, wobei der erste Anschlussstift und der zweite Anschlussstift jeweils zum Senden des Freigabesignals und der Schwarzbild-Daten eingerichtet sind, so dass Perioden des Freigabesignals und der Schwarzbild-Daten ungleich sind.
EP03016980A 2003-07-25 2003-07-25 Methode, ein schwarzes Bild einzufügen, und Vorrichtung zur Anzeige Expired - Lifetime EP1501071B1 (de)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09127917A (ja) * 1995-11-01 1997-05-16 Nec Corp 液晶表示装置
US20020008685A1 (en) * 2000-03-15 2002-01-24 Atsushi Ban Active matrix type display apparatus and method for driving the same
US20020063683A1 (en) * 2000-11-29 2002-05-30 Choong-Hoon Yi Triodic rectifier switch

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3747768B2 (ja) * 2000-03-17 2006-02-22 株式会社日立製作所 液晶表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09127917A (ja) * 1995-11-01 1997-05-16 Nec Corp 液晶表示装置
US20020008685A1 (en) * 2000-03-15 2002-01-24 Atsushi Ban Active matrix type display apparatus and method for driving the same
US20020063683A1 (en) * 2000-11-29 2002-05-30 Choong-Hoon Yi Triodic rectifier switch

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