EP1494167A1 - Dispositif semiconducteur flexible et etiquette d'identification - Google Patents

Dispositif semiconducteur flexible et etiquette d'identification Download PDF

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Publication number
EP1494167A1
EP1494167A1 EP03102020A EP03102020A EP1494167A1 EP 1494167 A1 EP1494167 A1 EP 1494167A1 EP 03102020 A EP03102020 A EP 03102020A EP 03102020 A EP03102020 A EP 03102020A EP 1494167 A1 EP1494167 A1 EP 1494167A1
Authority
EP
European Patent Office
Prior art keywords
flexible
substrate
integrated circuit
antenna
flexible device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03102020A
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German (de)
English (en)
Inventor
designation of the inventor has not yet been filed The
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP03102020A priority Critical patent/EP1494167A1/fr
Priority to JP2006516786A priority patent/JP2007519215A/ja
Priority to EP04744449A priority patent/EP1644874B1/fr
Priority to DE602004003498T priority patent/DE602004003498T2/de
Priority to US10/563,416 priority patent/US7816774B2/en
Priority to PCT/IB2004/051080 priority patent/WO2005004049A1/fr
Priority to CN200480018675.3A priority patent/CN100524351C/zh
Priority to AT04744449T priority patent/ATE347149T1/de
Priority to TW093120096A priority patent/TWI354937B/zh
Publication of EP1494167A1 publication Critical patent/EP1494167A1/fr
Priority to US12/878,066 priority patent/US8105873B2/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • the invention relates to a flexible semiconductor device comprising a semiconductor substrate and an integrated circuit provided with a plurality of semiconductor elements, that are defined at a surface of the semiconductor substrate and interconnected according to a desired pattern in an interconnect structure.
  • the invention also relates to a security paper comprising the flexible semiconductor device and to an identification label comprising a carrier and the flexible semiconductor device.
  • the invention further relates to a method of manufacturing a flexible semiconductor device comprising the steps of
  • Such a flexible device such a label and such a method of manufacturing are known from US-A 6,291,877.
  • the known device is an integrated circuit defined in a so-called silicon-on-insulator (SOI) substrate.
  • SOI substrate is thinned after definition of the integrated circuit so that only the insulator layer and the silicon layer on top thereof are maintained. Therewith the device becomes very thin, for instance 5 to 10 micrometers and is rendered flexible. It is thereafter bonded in such a configuration as to be held between card substrates by a flexible adhesive.
  • the integrated circuit is therein provided with bond pads, that are connected to a wiring on the card substrate by conductive ink. This conductive ink is printed on one of the card substrates after assembly of the integrated circuit thereon.
  • the wiring comprises for instance a coil used for the receipt and transmission of data and energy.
  • the resulting identification label is limited for use at lower frequencies.
  • the conductive ink forms a track of considerable impedance, which is particularly disadvantageous at higher frequencies.
  • the track cannot be shortened easily in view of the limited resolution of the printing of the conductive ink.
  • the printing of a metal by means of a sol-gel method is in principle an alternative; however, the conversion temperature of such sol-gel precursor to a metal limits the choice of card substrates.
  • the first object is achieved in that the semiconductor substrate laterally extends in an active area; and that a support layer of electrically insulating material and an antenna are present.
  • the antenna is defined laterally outside the active area in an electrically conductive layer adjacent to the support layer and and is electrically connected to the interconnect structure, the semiconductor substrate being absent. in a non-substrate area between the antenna and the integrated circuit.
  • the second object is achieved in the label with this flexible device.
  • the provision of an integrated antenna takes away the necessity of a connection to a card substrate. Hence, no conductive ink is needed at all.
  • the known label was manufactured using at least two process steps which needed specific assembly: first the provision of the integrated circuit to a specific location on the card substrate; and second the provision of the conductive track by printing. No such specific location and no specific bonding is needed for the assembly of the present label.
  • the label may comprise only a single card substrate, instead of two.
  • the flexible device can be attached thereto or being integrated therein in a lamination process. This increases the flexibility of the label and reduces the components and thus the costs.
  • the integrated circuit comprises all functionality. If meant for use in an consumer apparatus, on a polymer package of an article, then the manufacturer of such apparatus or package does not need to have any knowledge of printing or antennas.
  • the integrated antenna is generally limited in size. In comparison with the wirings on the card substrate and the conductive ink track, the visibility of the flexible device with integrated antenna is thus diminished. This is clearly an advantage for many security applications, in which it is undesired that everybody recognizes the security feature immediately. Beyond that, the reliability of the label is improved in view of the absence of any connection.
  • the support layer Due to the support layer of electrically insulating material the resonating behavior of the antenna is improved. Furthermore, the support layer allows to remove any additional support substrate, before the devices are separated. In the known device, a support substrate is used and it is removed only after the flexible device is attached to the card substrate.
  • the support layer also allows that the semiconductor substrate is completely absent between the active area and the antenna. In this manner, the interaction between antenna and integrated circuit is reduced considerably, leading to good antenna performance.
  • the semiconductor substrate is absent anywhere outside the active area. This improves the flexibility.
  • the active area of the substrate is preferably in the shape of a mesa, which shape is robust and can be made with conventional etching techniques.
  • the antenna is provided at the surface of the integrated circuit.
  • the substrate is not removed in certain areas, and no support layer is provided.
  • the device of the invention has at least two advantages: the antenna of the invention can have a larger size, leading to lower transmission frequencies and increased distance and power transmission; and the mutual interaction between antenna and integrated circuit is diminished substantially.
  • the support layer comprises for instance a polymer material, such as polyamide, polycarbonate, fluorinated polymers, polysulfonates, epoxides, polyesters and the like.
  • a polymer material such as polyamide, polycarbonate, fluorinated polymers, polysulfonates, epoxides, polyesters and the like.
  • polyamide is preferred.
  • magnetic particles can be present in the support layer. Suitable magnetic particles are ferrite particles, with an average diameter of preferably 0.5 - 1.0 micrometer.
  • a further advantage of such support layer is that it can act as a protection against moisture, dust and contaminations. In the prior art, such continuous support layer cannot be realized since contacts need to be applied from the device to the antenna.
  • the integrated circuit of the device of the invention can be provided in different technologies. First of all, it can be defined at the surface of a silicon-on-insulator substrate. This technology is well known. Secondly, use can be made of semiconductor substrates of III-V material or on the other hand of polycrystalline silicon. Such a choice depends on the desired performance of the integrated circuit. Preferably, use is made of a conventional semiconductor substrate of monocrystalline silicon. This has the advantage that it is cheap as compared to a SOI substrate, while at the same time the designs conventionally used for non-flexible integrated circuits can be applied. Furthermore, the use of monocrystalline silicon allows the use of standard semiconductor factories. The mesa structure enables a good flexibility of the device.
  • the flexible device of the invention can be manufactured advantageously with a substrate transfer method, using a temporary support.
  • antennas can be implemented, such as antennas based on capacitive coupling, dipole antennas, multipole antennas. It is however preferred that the antenna is an inductor suitable for wireless communication.
  • the available frequency range is roughly from 1 to 3 GHz. The minimum is determined by the coil size, the maximum is determined by the strength of the rectifiers in the integrated circuit.
  • An inductor having a turn with a surface area of 1,5 * 1,5 mm is suitable for a frequency of 2,4 GHz.
  • Such an antenna can be used for transmission over a distance of 3 mm so as to provide 3-4 mW at 2 V, 100 mA.
  • the antenna quality can be improved further if a further inductor winding is provided at a second side opposite to the first side.
  • the second side is available for a further winding as the substrate is removed.
  • the contacts between the windings can be made through the interconnect structure.
  • the further winding may but need not to have the same diameter and shape as the first winding.
  • the windings, or generally, the antenna structures at both sides can be complementary.
  • the inductor at the second side could be spiralic.
  • the integrated circuit is laterally located within the inductor.
  • an optimal use of available surface area is realized.
  • the influence of the inductor on the circuit is limited.
  • the integrated circuit is subdivided in a plurality of circuit blocks, which are mutually spaced apart, but interconnected through the interconnect structure. This reduces the magnitude of eddy currents in the integrated circuit as a result of the inductor.
  • the semiconductor elements are defined at a surface of a semiconductor substrate; and the device comprises an active areas corresponding to the circuit blocks, and a non-substrate area being defined laterally between the active areas and around it, in which non-substrate area the semiconductor substrate is absent.
  • a perpendicular projection of the integrated circuit onto the electrically conductive layer of the antenna at least substantially overlaps with the antenna.
  • This embodiment is particularly suitable in combination with semiconductor elements in an advanced type and having thus resolution on a submicronscale.
  • the advantage of this embodiment is first of all the very small eddy current.
  • the antenna can form a mechanical protection for the integrated circuit.
  • the integrated circuit is provided with a security coating, which is a layer that is in principle not transparent for either ultraviolet radiation, visible light or infrared radiation. Beyond such a coating is difficult to remove by means of etching. In this manner it offers a good protection against hackers that desire to get access to or to modify the circuit design.
  • a security coating is preferably a layer filled with particles.
  • the layer may be an organic material or an inorganic material. Thickness and material of the coating will be an optimum between perfect protection and flexibility.
  • the application of a security coating is easier in the device of the invention in comparison to the prior art, as no bond pads are necessary, and hence it is possible to apply an unpatterned coating.
  • Security paper with an integrated circuit is for instance known from WO-A 99/54842.
  • the integrated circuit comprises an organic semiconductor material.
  • the security paper of the invention is characterized in that the flexible device of the invention is present. This has the important advantage that a laminating technology can be used for integration of the flexible device. This results therein that the device can be fully embedded in the paper. It is therewith less easy to remove the flexible device from the security paper.
  • the integrated circuit is hidden to a certain extent.
  • the device can further be provided with a security coating for optimal protection.
  • 'paper' is understood the mean paper which is made from natural or synthetic fibers, as well as "paper” which can nowadays be produced from plastic films, which paper is known for use as security paper.
  • the paper can be used for a variety of applications, including banknotes, passports and other official documents, tickets and the like.
  • security features may be present in addition to the integrated circuit. Examples thereof are a conductive security thread, holograms, optically active elements, as well as the presence of detectable fluorescent, magnetic or conductive particles or fibers in the substrate.
  • the security paper and/or the flexible device are very suitable for integration in identification documents or in apparatus, and particularly the encapsulation thereof. Its flexibility and its thinness renders it very suitable for integration in security paper and the like, and therewith for applications in which visibility of the flexible device is not preferred.
  • the invention also relates to use of the flexible device of the invention in a wireless communication.
  • both energy and data are sent from a reader to the flexible device.
  • the data are returned to the reader.
  • the desired operation generally involves the reading of a memory according to a predetermined pattern.
  • Cryptographic techniques can be used to improve the secrecy of the wireless transmission.
  • One very suitable manner known in cryptography is the use of hash-functions.
  • the flexible device randomizes the first signal before reading the memory. This randomizing occurs with a non-invertible function.
  • a second hash-function may be applied.
  • the resulting second signal is then compared with a reference signal stored in the reader or in a central database that is connected to the reader.
  • the flexible device is provided with a security coating having a measurable property inhomogeneously distributed over the coating, and with measurement elements to measure the said property.
  • the property is preferable realized with embedded dielectric, conductive, resistive or magnetic particles of different constitution, size and density.
  • the measurement elements therein measure the impedance. This provides a very good protection, and is particularly suitable for use in combination with a hash function, as described in the non-prepublished application EP03101515.9 (PHNL030634).
  • Fig. 1A shows a substrate 10 with a first side 1 and a second side 2.
  • the substrate 10 comprises monocrystalline silicon.
  • On top of the substrate a thermal oxide is present, and thereon an interconnect structure 3 is provided.
  • the interconnect structure generally comprises 3 to 5 conducting layers that are mutually separated by patterned dielectric layers.
  • the interconnect structure 3 interconnects the semiconductor elements defined at the first side of the substrate 10.
  • the semiconductor elements are in this case CMOS transistors and in addition thereto diodes for use as rectifiers. Together the interconnect structure 3 and the semiconductor elements define the integrated circuit 5.
  • an antenna 6 is present.
  • the antenna 6 is an inductor having one turn.
  • the antenna 6 is present on top of the interconnect structure 5, it is preferred in view of process steps that the antenna 6 is deposited as part of one metal layer of the interconnect structure 5. Although it is shown in the Fig., that the interconnect structure 5 extends over the complete substrate 10, this need not to be the case. In fact, it is preferred for reasons of limiting mechanical stress, that both the metal layers and the dielectric layers of the interconnect structure are deposited only in that region in which they contribute to the functionality.
  • Further elements such as diodes, Schottky diodes, bipolar transistors, capacitors, resistors, opto-electrical elements and others may be present as well. They are interconnected according to a desired circuit pattern, that is known per se to the skilled person.
  • processes are carried out at or in the vicinity of the substrate 10. These processes include for instance oxidation steps, photolithography steps, selective etching steps and intermediate doping steps such as diffusion or ion implantation, all known per se.
  • source and drain electrodes as well as an intermediate channel are provided in the active layer, that is covered by a gate oxide layer and a gate electrode of polycrystalline silicon, a metal, a silicide. Additional metal layers for interconnection purposes can be provided. However, it is preferred to keep the number of layers limited.
  • Fig. 1B shows the substrate 10, after that a coating 3 is provided.
  • the substrate and the interconnect structure is covered with a flexible coating, preferably a polymer.
  • the layer is provided by spin coating, spraying or the formation of a film, and is subsequently cured.
  • the adhesion of the coating 3 to the substrate 10 and the stack of layers on top of that is enhanced in that first a cleaning step with fuming HNO 3 is done and thereafter it is treated with a suitable primer.
  • a polyamide resin coating 3 is formed in that a precursor of the polyimide is applied.
  • the solvent is evaporated at 125 °C.
  • a heating step at 200 °C is done to activate the primer.
  • a photoresist 4 such as HPR504 is applied and exposed. The exposure results therein, that the photoresist 4 is present at the device area 21 and absent at the protection areas 22.
  • Fig. 1 C shows the result after some further steps.
  • the coating is patterned.
  • the patterning of the coating is realized with conventional developer solutions such as cyclopentanon.
  • the resist is stripped in a mixture of aceton and isopropanol.
  • the coating 3 is cured at 300-400 °C.
  • a 0,5 ⁇ m thick layer of PECVD oxide is deposited at about 300 °C. Neither the PECVD oxide nor the patterned deposition are shown in this Fig.
  • the protection areas which are defined laterally outside the area of the flexible device are treated with adhesion means, in this case a silane coupling agent. This treatment is done in a so-called "edge beat removal” fashion. Alternatively, the protection areas are dipped into a solution of this silane primer.
  • a UV glue releasable glue layer 31 and a carrier substrate 30 are provided. In this manner, the substrate 10 is temporarily attached to the carrier substrate 30 with a UV releasable glue layer 31.
  • the carrier substrate 30 is transparent, so that the glue layer can be released with UV-irradiation.
  • Fig. 1D shows the result after the substrate 10 has been thinned to a thickness d of about 5-20 micrometers.
  • the thinning of the substrate is for instance done with grinding, but alternatively or in addition thereto etching with for instance a KOH solution can be used.
  • Fig. 1E shows the result after that a suitable hard-etch mask 15 is provided and patterned so as to protect the integrated circuit 5.
  • the hard-etch mask can be chosen to desire as known to those skilled in the art.
  • Fig. 1F shows the result after the substrate 10 is removed in areas which are not protected by the hard etch mask 15. Herewith active areas 10A and non-substrate areas 10B are created.
  • Fig. 1 G and 2 show finally the device 100 after removal of the carrier substrate 30.
  • First use is made of UV-irradiation. Thereafter the substrate is separated into individual devices 100. This is done by cutting through the oxidic layer, which is present laterally around the devices 100. The cutting is for instance done with a razor blade.
  • the flexible device 100 is shown here as one device, it will be understood that this includes a plurality of devices 100. These may be separated afterwards. Also the separation step may be done by the customer. This method is further elucidated in the non-prepublished application EP02079697.5 (PHNL021153) which is included herein by reference.
  • Fig. 3 shows a first layout of the device 100 of the invention.
  • the antenna 6 is an inductor and the integrated circuit 5 is provided in the area in between of the inductor 6.
  • the antenna 6 and the integrated circuit are present on the layer of electrically insulating material 4 acting as support. More specifically, the integrated circuit 5 is positioned Centre symmetrically, so as to limit the negative influence of the inductor 6 thereon.
  • An interconnect from the inductor 6 to the integrated circuit 5 is not shown, but is present.
  • Fig. 4 shows a second layout.
  • the integrated circuit 5 is partitioned into several areas 5A-5D. This is assumed to reduce the eddy currents in the integrated circuit 5.
  • the areas 5A-5D are mutually interconnected, although this is not shown.
  • the integrated circuit 5 comprises a rectifier, a memory, a state machine, such as a shift register or a microcontroller, a clock generator, and some further interconnects and transistors for switching and/or other amplifying purposes.
  • the partioning is preferably realized in that each of the functions is put in a separate area.
  • Fig. 5 shows a third layout.
  • the integrated circuit 5 is pardoned into several areas 5A-5H.
  • the areas 5A-5H are positioned such that there is a substantial overlap with the antenna 6. This will decrease any eddy currents and other impact of the antenna on the integrated circuit 5 further.
  • the number of areas is subject to further design. This furthermore allows to provide a second turn of the antenna 6 inside the first turn, or eventually to use another antenna design that the inductor, for instance a dipole, without using a substantially larger area.
  • Fig. 6 shows an electric diagram of the antenna 6 with some additional components. Shown herein is the inductor acting as the antenna 6, a capacitor 61 for tuning purposes, as well as a voltage inducer 62, a sum resistance 63 and a load resistor 64.
  • the load resistor 64 can be a rectifier circuit, which converts the RF voltage to a DC voltage and may include the active circuitry of the integrated circuit.
  • the sum resistance 63 is the sum of the series radiation resistance R rad and the resistive losses R ohmic . This radiation resistance R rad is small for an inductor with a number of turns, e.g.
  • the radiation resistance R rad of a 1- or 2-turn inductor at a chip is less than 0.1 ⁇ at a frequency of 2.4 GHz.
  • the relative low voltage, induced in the radiation resistance R rad is multiplied by the Q-factor of the LC tank.
  • the Q-factor is about 60 at 2.4 GHz. This results thereof that the inductor is present outside the active area, at a support substrate of electrically insulating material.
  • This Q is sufficiently high to achieve voltage levels of several volts and power levels of several mW in the integrated circuit, on transmission over a short range, e.g. 1-2 mm.
  • the external RF source power is about 0.5 W at 2.4 GHz.
  • Optimum power efficiency will be achieved with the load on the tank equals the impedance of the tank, e.g. approximately equal to Q 2 . the sum resistance.
  • a flexible device 100 having an integrated circuit and an antenna which is incorporated or directly coupled to the interconnect structure of the integrated circuit.
  • An electrically insulating or dielectric layer is present as support layer for both antenna and integrated circuit.
  • the substrate is removed at non-substrate areas outside the active areas of the integrated circuit. This removal can be combined with the use of a substrate of monocrystalline silicon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Details Of Aerials (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Support Of Aerials (AREA)
EP03102020A 2003-07-04 2003-07-04 Dispositif semiconducteur flexible et etiquette d'identification Withdrawn EP1494167A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
EP03102020A EP1494167A1 (fr) 2003-07-04 2003-07-04 Dispositif semiconducteur flexible et etiquette d'identification
PCT/IB2004/051080 WO2005004049A1 (fr) 2003-07-04 2004-07-01 Dispositif a semi-conducteurs souple et etiquette d'identification
EP04744449A EP1644874B1 (fr) 2003-07-04 2004-07-01 Dispositif semiconducteur flexible et etiquette d'identification
DE602004003498T DE602004003498T2 (de) 2003-07-04 2004-07-01 Flexibles halbleiter-bauelement und identifikationsetikett
US10/563,416 US7816774B2 (en) 2003-07-04 2004-07-01 Flexible semiconductor device and identification label
JP2006516786A JP2007519215A (ja) 2003-07-04 2004-07-01 柔軟な半導体デバイス及び識別ラベル
CN200480018675.3A CN100524351C (zh) 2003-07-04 2004-07-01 柔性半导体器件和识别标签
AT04744449T ATE347149T1 (de) 2003-07-04 2004-07-01 Flexibles halbleiter-bauelement und identifikationsetikett
TW093120096A TWI354937B (en) 2003-07-04 2004-07-02 Flexible semiconductor device and identification l
US12/878,066 US8105873B2 (en) 2003-07-04 2010-09-09 Flexible semiconductor device and identification label

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Application Number Priority Date Filing Date Title
EP03102020A EP1494167A1 (fr) 2003-07-04 2003-07-04 Dispositif semiconducteur flexible et etiquette d'identification

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EP04744449A Expired - Lifetime EP1644874B1 (fr) 2003-07-04 2004-07-01 Dispositif semiconducteur flexible et etiquette d'identification

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EP (2) EP1494167A1 (fr)
JP (1) JP2007519215A (fr)
CN (1) CN100524351C (fr)
AT (1) ATE347149T1 (fr)
DE (1) DE602004003498T2 (fr)
TW (1) TWI354937B (fr)
WO (1) WO2005004049A1 (fr)

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US7566971B2 (en) 2005-05-27 2009-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

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US7687327B2 (en) * 2005-07-08 2010-03-30 Kovio, Inc, Methods for manufacturing RFID tags and structures formed therefrom
US7690105B2 (en) * 2005-08-19 2010-04-06 Coilcraft, Incorporated Method for conserving space in a circuit
US8232621B2 (en) * 2006-07-28 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8816484B2 (en) * 2007-02-09 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
GB2452732A (en) * 2007-09-12 2009-03-18 Seiko Epson Corp Smart-card chip with organic conductive surface layer for detecting invasive attack
US8106474B2 (en) * 2008-04-18 2012-01-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2012173654A2 (fr) * 2011-06-15 2012-12-20 Power Gold LLC Ensemble circuit flexible et procédé associé
US8879276B2 (en) 2011-06-15 2014-11-04 Power Gold LLC Flexible circuit assembly and method thereof
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
WO2014121300A2 (fr) * 2013-02-04 2014-08-07 American Semiconductor, Inc. Ensemble de transfert de données photoniques
US20140264938A1 (en) * 2013-03-14 2014-09-18 Douglas R. Hackler, Sr. Flexible Interconnect
US10102697B2 (en) * 2015-10-31 2018-10-16 Disney Enterprises, Inc. High-Q and over-coupled near-field RFID reader antenna for improved tag read range
US10542619B2 (en) * 2017-12-12 2020-01-21 Eastman Kodak Company Electronic element with embedded information

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Also Published As

Publication number Publication date
US8105873B2 (en) 2012-01-31
DE602004003498T2 (de) 2007-10-04
US20100328028A1 (en) 2010-12-30
US20070108521A1 (en) 2007-05-17
TW200516505A (en) 2005-05-16
EP1644874B1 (fr) 2006-11-29
CN100524351C (zh) 2009-08-05
CN1816817A (zh) 2006-08-09
JP2007519215A (ja) 2007-07-12
US7816774B2 (en) 2010-10-19
ATE347149T1 (de) 2006-12-15
DE602004003498D1 (de) 2007-01-11
EP1644874A1 (fr) 2006-04-12
TWI354937B (en) 2011-12-21
WO2005004049A1 (fr) 2005-01-13

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