EP1472722A2 - Procede de production de cellule de memoire - Google Patents

Procede de production de cellule de memoire

Info

Publication number
EP1472722A2
EP1472722A2 EP03737237A EP03737237A EP1472722A2 EP 1472722 A2 EP1472722 A2 EP 1472722A2 EP 03737237 A EP03737237 A EP 03737237A EP 03737237 A EP03737237 A EP 03737237A EP 1472722 A2 EP1472722 A2 EP 1472722A2
Authority
EP
European Patent Office
Prior art keywords
source
layer
produced
trench
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03737237A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Erhard Landgraf
Hannes Luyken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1472722A2 publication Critical patent/EP1472722A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Selon l'invention, les cellules de mémoires NROM sont disposées dans des tranchées, gravées dans le matériau semi-conducteur. La couche de mémorisation à base d'une couche de nitrure (3) entre des couches d'oxyde (2, 4) est appliquée sur les parois des tranchées, avant que les matières de dopage pour la source et le drain (7) ne soient implantées. Ce système permet de parvenir à ce que la forte sollicitation thermique du composant lors de la fabrication de la couche de mémorisation ne puisse altérer les zones d'implantation de la source et du drain, la matière de dopage concernées n'étant introduite qu'ultérieurement. Les électrodes de grille (5) en polysilicium sont reliées à des lignes de mots (11).
EP03737237A 2002-02-06 2003-01-23 Procede de production de cellule de memoire Withdrawn EP1472722A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10204873A DE10204873C1 (de) 2002-02-06 2002-02-06 Herstellungsverfahren für Speicherzelle
DE10204873 2002-02-06
PCT/DE2003/000183 WO2003067639A2 (fr) 2002-02-06 2003-01-23 Procede de production de cellule de memoire

Publications (1)

Publication Number Publication Date
EP1472722A2 true EP1472722A2 (fr) 2004-11-03

Family

ID=27674565

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03737237A Withdrawn EP1472722A2 (fr) 2002-02-06 2003-01-23 Procede de production de cellule de memoire

Country Status (7)

Country Link
US (1) US6982202B2 (fr)
EP (1) EP1472722A2 (fr)
JP (1) JP4093965B2 (fr)
CN (1) CN1628372A (fr)
DE (1) DE10204873C1 (fr)
TW (1) TW200308059A (fr)
WO (1) WO2003067639A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10324550B4 (de) 2003-05-30 2006-10-19 Infineon Technologies Ag Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung
DE102004024047A1 (de) * 2004-05-14 2005-12-08 OCé PRINTING SYSTEMS GMBH Verfahren und Vorrichtung zum Einfärben eines Applikatorelements eines elektrofotografischen Druckers oder Kopierers
JP2006080163A (ja) * 2004-09-07 2006-03-23 Toshiba Corp 不揮発性半導体記憶装置
US7053447B2 (en) * 2004-09-14 2006-05-30 Infineon Technologies Ag Charge-trapping semiconductor memory device
US7667264B2 (en) * 2004-09-27 2010-02-23 Alpha And Omega Semiconductor Limited Shallow source MOSFET
US7365382B2 (en) 2005-02-28 2008-04-29 Infineon Technologies Ag Semiconductor memory having charge trapping memory cells and fabrication method thereof
US7335939B2 (en) * 2005-05-23 2008-02-26 Infineon Technologies Ag Semiconductor memory device and method of production
US7399673B2 (en) * 2005-07-08 2008-07-15 Infineon Technologies Ag Method of forming a charge-trapping memory device
US20070057318A1 (en) * 2005-09-15 2007-03-15 Lars Bach Semiconductor memory device and method of production
US7439594B2 (en) * 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
JP5200940B2 (ja) 2006-12-15 2013-06-05 日本電気株式会社 不揮発性記憶装置
JP2009049138A (ja) * 2007-08-17 2009-03-05 Spansion Llc 半導体装置の製造方法
KR101920247B1 (ko) * 2012-09-17 2018-11-20 삼성전자 주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961188A (ja) * 1982-09-30 1984-04-07 Toshiba Corp 不揮発性半導体メモリ装置
JP2662076B2 (ja) 1990-05-02 1997-10-08 松下電子工業株式会社 不揮発性半導体記憶装置およびその製造方法
DE19639026C1 (de) * 1996-09-23 1998-04-09 Siemens Ag Selbstjustierte nichtflüchtige Speicherzelle
US5973358A (en) * 1997-07-01 1999-10-26 Citizen Watch Co., Ltd. SOI device having a channel with variable thickness
US6002151A (en) * 1997-12-18 1999-12-14 Advanced Micro Devices, Inc. Non-volatile trench semiconductor device
US6376877B1 (en) * 2000-02-24 2002-04-23 Advanced Micro Devices, Inc. Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03067639A2 *

Also Published As

Publication number Publication date
WO2003067639A2 (fr) 2003-08-14
JP2005525695A (ja) 2005-08-25
US20050032311A1 (en) 2005-02-10
JP4093965B2 (ja) 2008-06-04
US6982202B2 (en) 2006-01-03
WO2003067639A3 (fr) 2003-10-16
TW200308059A (en) 2003-12-16
CN1628372A (zh) 2005-06-15
DE10204873C1 (de) 2003-10-09

Similar Documents

Publication Publication Date Title
DE69432568T2 (de) Selbstjustierende flash-eeprom-zelle mit doppelbit-geteiltem gat
DE10129958B4 (de) Speicherzellenanordnung und Herstellungsverfahren
DE4241457B4 (de) P-leitendes floatendes Gate aus Poly-Silizium zur Verwendung bei einem Halbleiterbautransistorelement und daraus hergestelltes Flash-E2PROM
EP0783180B1 (fr) Ensemble de cellules mémoire électriquement programmable et procédé de fabrication
DE102005030845B4 (de) Nichtflüchtige NAND-Typ-Halbleiterspeichervorrichtungen mit Gräben und Verfahren zum Bilden derselben
DE10336876B4 (de) Speicherzelle mit Nanokristallen oder Nanodots und Verfahren zu deren Herstellung
DE102004006505B4 (de) Charge-Trapping-Speicherzelle und Herstellungsverfahren
DE10203762A1 (de) Nichtflüchtiges Halbleiterspeicherbauelement und Verfahren zu seiner Herstellung
DE10039441A1 (de) Speicherzelle, Speicherzellenanordnung und Herstellungsverfahren
WO2004023519A2 (fr) Nrom-finfet a densite elevee
EP0838092B1 (fr) Systeme de cellules de memoire morte programmable effa able electriquement et procede de fabrication dudit systeme
DE10204873C1 (de) Herstellungsverfahren für Speicherzelle
EP0946985B1 (fr) Agencement de cellules de memoire et son procede de fabrication
EP1535335B1 (fr) Memoire a semiconducteurs pourvue de transistors de memoire verticaux dans un ensemble champ de cellules 1 - 2f²
DE112004003019T5 (de) Nicht-flüchtiges Speicherbauelement und Verfahren zu dessen Herstellung
WO2004107435A1 (fr) Dispositif memoire a semi-conducteur nrom et procede de fabrication dudit dispositif
EP1518277B1 (fr) Procede pour produire un champ de cellule memoire nrom
WO2003026014A1 (fr) Element de memoire a semi-conducteurs, son procede de fabrication et procede permettant son fonctionnement
WO2003096425A1 (fr) Cellule de memoire flash et son procede de production
EP1514304B1 (fr) Procede de production d'un systeme de cellules de memoire nrom
EP1374308B1 (fr) Reseau de cellules de memoire comportant des cellules de memoire adressables individuellement et son procede de fabrication
DE102006026941B3 (de) Speicherzellenfeld mit nichtflüchtigen Speicherzellen und Verfahren zu dessen Herstellung
WO2003105231A1 (fr) Procede pour produire des cellules de memoire nrom comportant des transistors a tranchees
EP1192652A1 (fr) Procede de fabrication d'une cellule de memoire a semi-conducteur remanente a fenetre a effet tunnel separee
WO2003017374A2 (fr) Cellule de memoire

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040813

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT SE SI SK TR

RIN1 Information on inventor provided before grant (corrected)

Inventor name: HOFMANN, FRANZ

Inventor name: LANDGRAF, ERHARD

Inventor name: LUYKEN, HANNES

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20080822