EP1439443B9 - Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung - Google Patents

Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung Download PDF

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Publication number
EP1439443B9
EP1439443B9 EP03000815.5A EP03000815A EP1439443B9 EP 1439443 B9 EP1439443 B9 EP 1439443B9 EP 03000815 A EP03000815 A EP 03000815A EP 1439443 B9 EP1439443 B9 EP 1439443B9
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EP
European Patent Office
Prior art keywords
voltage
supply voltage
supply
vddext1
vddext2
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP03000815.5A
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German (de)
English (en)
French (fr)
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EP1439443A1 (de
EP1439443B1 (de
Inventor
Thomas Jean Ludovic Baglin
Albert Missoni
Gerhard Nebel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP03000815.5A priority Critical patent/EP1439443B9/de
Priority to PCT/EP2004/000173 priority patent/WO2004064232A2/de
Priority to KR1020057012952A priority patent/KR100654475B1/ko
Publication of EP1439443A1 publication Critical patent/EP1439443A1/de
Priority to US11/181,032 priority patent/US7501718B2/en
Application granted granted Critical
Publication of EP1439443B1 publication Critical patent/EP1439443B1/de
Publication of EP1439443B9 publication Critical patent/EP1439443B9/de
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current

Definitions

  • the invention relates to a circuit for power supply and a method for generating a supply voltage. Both the circuit and the method can be used, for example, for the power supply for an integrated circuit.
  • the generation of a supply voltage whereby two voltage sources are available, presents a number of problems.
  • the handling of two voltage sources to generate a supply voltage is more complex and difficult than the generation of a supply voltage when only one voltage source is available.
  • the applicant assumes in internal use of an embodiment for a circuit for generating a power supply, as shown in FIG. 1 is shown.
  • the circuit shown is selected between two external power sources and formed by means of the selected external supply voltage, the output voltage VDD.
  • the circuit has a first supply voltage input IN1, to which a first external supply voltage VDDEXT1 is applied, and a second supply voltage input IN2, to which a second external supply voltage VDDEXT2 is applied.
  • the two external supply voltages VDDEXT1 and VDDEXT2 are each fed to a comparator input of a comparator CMP.
  • the two external supply voltages VDDEXT1 and VDDEXT2 also at the inputs of two voltage regulators REG1 and REG2.
  • VDDEXT3 which is applied to a voltage input IN3 of the circuit
  • the external voltage VDDEXT3 forms at the same time at the operating voltage connection BA of the comparator CMP the operating voltage for the comparator CMP and also the operating voltage for a downstream inverter INV.
  • the output voltage ENREG1 generated by the comparator CMP serves as an additional control voltage for the first voltage regulator REG1 and at the same time as an input voltage for the inverter INV, which forms an inverted output voltage ENREG22 therefrom.
  • This inverted output voltage ENREG22 serves as an additional control voltage for the second voltage regulator REG2.
  • the two outputs of the voltage regulators REG1 and REG2 are connected to each other and form the supply voltage output O of the circuit for power supply.
  • the in FIG. 1 shown circuit ensures that only one of the two voltage sources and thus only one of the two external supply voltages VDDEXT1 or VDDEXT2 is activated.
  • the other voltage source is deactivated.
  • the voltage source is selected, which provides the higher supply voltage. This is because in this the probability is higher that the supply voltage provided is greater than the nominal supply voltage VDDnom and thus allows a correct regulation.
  • the comparator CMP decides which of the two external voltage sources provides the higher supply voltage.
  • the comparator CMP therefore compares the first external supply voltage VDDEXT1 with the second external supply voltage VDDEXT2.
  • the higher of the two external supply voltages VDDEXT1 and VDDEXT2 is used to supply the downstream analog components. The following situations may occur.
  • the first external supply voltage VDDEXT1 is greater than the second external supply voltage VDDEXT2:
  • the voltage ENREG1 at the comparator output assumes the value of the external voltage VDDEXT3.
  • the inverted voltage ENREG22 at the output of the inverter INV assumes the value zero.
  • the first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal supply voltage VDDnom.
  • the second voltage regulator REG2 disconnects the second external supply voltage VDDEXT2 from the supply voltage output O because the voltage ENREG22 is 0.
  • the first external supply voltage VDDEXT1 is smaller than the second external supply voltage VDDEXT2:
  • the voltage ENREG1 at the output of the comparator CMP assumes the value zero.
  • the inverted output voltage ENREG2 at the output of the inverter INV is then equal to the external voltage VDDEXT3.
  • the second regulator REG2 regulates the output voltage VDD to the value of the nominal voltage VDDnom.
  • the first voltage regulator separates the first external supply voltage VDDEXT1 from the supply voltage output O because the voltage ENREG2 is 0.
  • shown circuit for power supply has a number of disadvantages. If the two external supply voltages VDDEXT1 and VDDEXT2 are greater than the nominal voltage VDDnom, both could be used to control the supply voltage VDD. However, only the voltage which is the higher of the two voltages is used. In a system where a voltage supply is high in voltage but can not provide high current, such a solution is not optimal. In such a solution, it is possible that the voltage source is used, although the higher voltage, but the lower current supplies. Voltage sources which provide a high supply voltage but only a small current can be, for example, magnetic or electric fields.
  • both voltage sources each supply a supply voltage which is greater than the nominal voltage VDDnom and the voltage source which provides the greater voltage is switched off, the voltage regulator associated with this voltage is also switched off and the other voltage regulator is switched on. It is difficult to generate a stable supply voltage VDD while switching between the voltage regulators REG1 and REG2.
  • the two supply voltage sources supply supply voltages that are the same size, the two voltage regulators are alternately turned on and off, which may cause the entire control system to malfunction.
  • FIG. 2 shown another embodiment for a power supply known.
  • the first external supply voltage VDDEXT1 is fed via the first supply voltage input IN1 and a voltage converter 1 to the first input of a comparator CMP1.
  • the second external supply voltage VDDEXT2 is fed via the second supply voltage input IN2 and a second voltage converter 2 to the first input of a second comparator CMP2.
  • the second inputs of the first comparator CMP1 and the second comparator CMP2 are connected to the output of a reference voltage source 3, so that a reference voltage VREF is applied to them.
  • a reference voltage VREF is applied to them.
  • the external voltage VDDEXT3 which is present at the voltage input IN3, is used to control the two voltage regulators REG1 and REG2 and as the operating voltage for the two comparators CMP1 and CMP2.
  • the external voltage VDDEXT3 is applied to the input of the voltage source 3, which generates the reference voltage VREF.
  • the first external supply voltage VDDEXT1 and the second external supply voltage VDDEXT2 are compared with the reference voltage VREF to avoid a reverse current.
  • the two voltage converters 1 and 2 multiply the external supply voltages VDDEXT1 and VDDEXT2 by a factor k.
  • the reference voltage VREF * k is greater than the nominal voltage VDDnom.
  • the voltage VDDEXT1 is greater than the reference voltage VREF * k and the voltage VDDEXT2 is also greater than the reference voltage VREF * k:
  • both voltage regulators REG1 and REG2 regulate the supply voltage VDD to the value of the nominal voltage VDDnom.
  • a return current can not occur here because the voltage VDDEXT1 is greater than the reference voltage VREF * k and this in turn is greater than the nominal voltage VDDnom and this in turn is greater than or equal to the supply voltage VDD and in addition the voltage VDDEXT2 greater than the reference voltage VREF * k is greater than the nominal voltage VDDnom and in turn greater than or equal to the supply voltage VDD.
  • the voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is greater than the reference voltage VREF * k:
  • the second voltage regulator REG2 regulates the supply voltage VDD to the value of the nominal voltage VDDnom.
  • the first voltage regulator REG1 is turned off.
  • the voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is smaller than the reference voltage VREF * k:
  • both voltage regulators REG1 and REG2 are switched off.
  • the supply voltage VDD floats.
  • the voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is greater than the reference voltage VREF * k:
  • the first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal voltage VDDnom.
  • the second voltage regulator REG2 is turned off.
  • FIG. 2 shown embodiment of the circuit for power supply are compared to in FIG. 1 embodiment shown the most disadvantages avoided.
  • the embodiment shown has the following disadvantages.
  • the two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 must be exactly matched to each other, so that the value k * VREF is greater than the nominal voltage VDDnom. If this is not the case, for example, if k * VREF is less than the first external supply voltage VDDEXT1, and the nominal voltage VDDnom is again smaller than the nominal voltage VDDnom and which in turn is smaller than the second external supply voltage VDDEXT2, this will be false Tuning both regulators REG1 and REG2 is activated and a return current flows from the second external voltage source via the second supply voltage input IN2 to the supply voltage output O and from there back to the first external supply source at the first supply voltage input IN1.
  • the two voltage regulators REG1 and REG2 can be switched between different nominal voltages VDDnom1, VDDnom2, VDDnom3, etc.
  • the two voltage converters 1 and 2 can switch between different multiplication factors k1, k2, k3, etc.
  • k1, k2, k3 it becomes all the more difficult to exactly match the two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 in the manner already described, for each pair (VDDnom1, k1), (VDDnom2, k2). , (VDDnom3, k3).
  • the circuit requires more chip area, the power consumption increases and the complexity of the circuit increases.
  • An object of the invention is to provide a circuit for power supply and a method for generating a supply voltage in which no reverse current occurs. The current should flow from one power source to the supply voltage output of the circuit and not from one power source via the supply voltage output of the circuit back to the other power source.
  • the criteria for switching the current paths on and off should be selected so that a correct regulation of the supply voltage is possible in a number of different configurations.
  • the object is achieved by a circuit for power supply with the features according to claim 1 and a method for generating a supply voltage having the features according to claim 8.
  • a first voltage converter is provided, which is connected between the first supply voltage input and the first comparator.
  • a second one Voltage converter is provided, which is connected between the second power supply input and the second comparator.
  • a third voltage converter is provided, which is connected between the supply voltage output and the first comparator.
  • a fourth voltage setter is provided, which is connected between the supply voltage output and the second comparator.
  • the voltage converter are designed such that the voltage that can be applied to their inputs can be converted into a voltage proportional to this voltage with a defined proportionality factor.
  • the voltage converters can be designed in such a way that the voltage which can be applied at their inputs can be converted into a voltage reduced by a specific value.
  • the first voltage regulator, a first N-channel MOS transistor and the second voltage regulator comprises a second N-channel MOS transistor.
  • the control outputs of the two transistors are fed back to the control inputs of the two transistors.
  • a first supply voltage input IN1 is provided, which can be connected to a first voltage source, not shown, for generating a first external supply voltage VDDEXT1 is.
  • the first external supply voltage VDDEXT1 applied to the first supply voltage input IN1 is fed via a first voltage converter 1 to a first input of a first comparator CMP1.
  • the first external supply voltage VDDEXT1 is applied to the input of a voltage regulator REG1.
  • the circuit has a second supply voltage input IN2, which can be connected to a second voltage source, not shown, for generating a second external supply voltage VDDEXT2.
  • the second external supply voltage VDDEXT2 is applied via a second voltage converter 2 to a first input of a second comparator CMP2 and to an input of a second voltage regulator REG2.
  • the first voltage regulator REG1 is controlled via the signal at the output of the first comparator CMP1 with the control voltage ENREG1 and an external voltage VDDEXT3 applied to a third input IN3.
  • the outputs of the two voltage regulators REG1 and REG2 are connected to each other and lead on the one hand to the supply voltage output O of the circuit and on the other hand to the inputs of a third and fourth voltage converter 3 and 4, which in turn with the second inputs of the first and the second comparator CMP1 and CMP2 are connected.
  • the desired supply voltage VDD can be tapped off at the output O of the circuit.
  • the voltage converter 1 multiplies the first external supply voltage VDDEXT1 by the multiplier k and the voltage converter 3 is bridged by a simple line.
  • the value k * VDDEXT1 is less than the nominal voltage VDDnom and the value k * VDDEXT2 is greater than the nominal voltage VDD:
  • the supply voltage VDD is zero when switched on. Therefore, the value k * VDDEXT1 is greater than the supply voltage VDD and also the value k * VDDEXT2 is greater than the supply voltage VDD.
  • the control voltage ENREG1 at the output of the comparator CMP1 then takes the value of the voltage VDDEXT3 and the control voltage ENREG2 at the output of the second comparator CMP2 also assumes the value of the external voltage VDDEXT3, which causes the voltage regulators REG1 and REG2 to regulate.
  • the supply voltage VDD therefore now increases until it reaches the value k * VDDEXT1 and exceeds it. Then the first comparator CMP1 switches over and brings the control voltage ENREG1 to the value zero.
  • the voltage regulator REG1 is turned off.
  • the supply voltage output O is now disconnected from the first external supply voltage VDDEXT1, which is advantageous since the first external supply voltage VDDEXT1 is smaller than the supply voltage VDD. Otherwise, a current would flow from the supply voltage input IN2 to the supply voltage input IN1.
  • the supply voltage VDD continues to increase until it reaches the value of the nominal voltage VDDnom and is regulated to this value. Because the value k * VDDEXT2 is greater than the nominal supply voltage VDDnom, the control voltage ENREG2 remains at the output of the second comparator CMP2 to the value of the external voltage VDDEXT3.
  • the power supply voltage VDD is zero when the power is turned on, so that the value k * VDDEXT1 is greater than the power supply voltage VDD and the value k * VDDEXT2 is greater than the power supply voltage VDD.
  • the control voltage ENREG1 at the output of the first comparator CMP1 therefore assumes the value of the external voltage VDDEXT3 and the control voltage ENREG2 at the output of the second comparator CMP2 also the value of the external voltage VDDEXT3. Both voltage regulators REG1 and REG2 are now working.
  • the supply voltage VDD now increases until it reaches the desired nominal voltage value VDDnom without one of the two voltage regulators REG1 and REG2 being switched off, because the value k * VDDEXT1 is greater than the nominal voltage VDDnom and, at the same time, the value k * VDDEXT2 is greater as the nominal voltage VDDnom. Therefore, both voltage regulators REG1 and REG2 remain active over the entire time.
  • the value k * VDDEXT1 is smaller than the nominal voltage VDDnom and the value k * VDDEXT2 is smaller than the nominal voltage VDDnom and the first external supply voltage VDDEXT1 is smaller than the second external supply voltage VDDEXT2:
  • the supply voltage VDD when switching is equal to zero, so that the value k * VDDEXT1 is greater than the supply voltage VDD and at the same time the value k * VDDEXT2 is greater than the supply voltage VDD. Therefore, the comparator CMP1 brings the control voltage ENREG1 to the value of the external voltage VDDEXT3 and the second comparator CMP2 also applies the control voltage ENREG2 to the value of the external one Voltage VDDEXT2. Both voltage regulators REG1 and REG2 now work and ensure that the supply voltage VDD increases until the value k * VDDEXT1 is reached and exceeded.
  • the first comparator CMP1 now brings the control voltage ENREG1 to the value zero, so that the first voltage regulator REG1 is turned off.
  • the supply voltage VDD continues to increase until it reaches the value k * VDDEXT2.
  • a further increase in the supply voltage VDD does not occur because now the second comparator CMP2 sets the control voltage ENREG2 to the value zero and thus switches off the second voltage regulator REG2.
  • the condition 4.a): k * VDDEXT2 less VDDnom and k * VDDEXT1 greater VDDnom can be used to derive the behavior of the circuit from operating state 1: k * VDDEXT1 smaller VDDnom and k * VDDEXT2 larger VDDnom by the two suffixes 1 and 2 of the two external supply voltages VDDEXT1 and VDDEXT2 are interchanged.
  • both supply voltages VDDEXT1 and VDDEXT2 are greater than the nominal supply voltage VDDnom / k and one of the two voltage sources is switched off, it is easier to keep the supply voltage VDD stable than in the prior art because one of the two voltage regulators REG1 or REG2 remains in operation ,
  • Oscillating switching between the two voltage sources can only occur if the second external supply voltage VDDEXT2 is equal to the nominal voltage VDDnom or if the first external supply voltage VDDEXT1 is equal to the nominal voltage VDDnom. However, since this is a relatively rare situation, this condition will hardly occur.
  • the saturated operating state is given when the voltage VDS is greater than the voltage difference VGS - VTH.
  • NGATE is the voltage at the output of the regulator loop 5. This is especially the case when the Early effect of the NMOS transistors is minimized by making the length of the transistors large.
  • the supply voltage VDD falls by ( ⁇ 2 - 1) * (VGS - VTH), so that as the width of the NMOS transistor increases, the voltage decreases more slowly.
  • the two voltage regulators REG1 and REG2 operate in principle in the same way. Therefore, the operation of the first voltage regulator REG1 will be described below by way of example for both.
  • the control voltage ENREG1 is equal to zero
  • the resistance in the voltage regulator REG1 between its input, which is connected to the first supply voltage input IN1 and its output, which is connected to the supply output O infinitely large.
  • the control voltage ENREG1 assumes the value of the external voltage VDDEXT3 and when the supply voltage VDD is greater than the nominal voltage VDDnom, the resistance in the voltage regulator between its input and output increases until the supply voltage VDD equals the nominal voltage VDDnom. The resistance can rise to infinity.
  • control voltage ENREG1 equals the value of the external voltage VDDEXT3 and if the supply voltage VDD is less than the nominal voltage VDDnom, the resistance between the input and the output of the voltage regulator REG1 decreases until the supply voltage VDD equals the nominal voltage VDDnom is. Possibly the resistance drops to zero.
  • the nominal voltage VDDnom is a constant voltage.
  • the voltage converter generates at its output either a voltage which is reduced by a constant voltage with respect to the input voltage or a voltage which is the product of a constant multiplier k or proportionality factor with the input voltage.
  • the constant multiplier k lies between the values zero and one.
  • the comparator generates at its output a voltage which is equal to the operating voltage which is applied to its operating voltage input when the voltage applied to the non-inverting input of the comparator voltage is greater than the voltage applied to its inverting input voltage. Otherwise it generates at its output a voltage with the value zero.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
EP03000815.5A 2003-01-14 2003-01-14 Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung Expired - Lifetime EP1439443B9 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03000815.5A EP1439443B9 (de) 2003-01-14 2003-01-14 Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung
PCT/EP2004/000173 WO2004064232A2 (de) 2003-01-14 2004-01-13 Schaltung zur spannungsversorgung und verfahren zur erzeugung einer versorgungsspannung
KR1020057012952A KR100654475B1 (ko) 2003-01-14 2004-01-13 전압 공급 회로 및 공급 전압 발생 방법
US11/181,032 US7501718B2 (en) 2003-01-14 2005-07-12 Voltage supply circuit and method for generating a supply voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03000815.5A EP1439443B9 (de) 2003-01-14 2003-01-14 Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung

Publications (3)

Publication Number Publication Date
EP1439443A1 EP1439443A1 (de) 2004-07-21
EP1439443B1 EP1439443B1 (de) 2015-09-09
EP1439443B9 true EP1439443B9 (de) 2016-01-20

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EP03000815.5A Expired - Lifetime EP1439443B9 (de) 2003-01-14 2003-01-14 Schaltung zur Spannungsversorgung und Verfahren zur Erzeugung einer Versorgungsspannung

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US (1) US7501718B2 (ko)
EP (1) EP1439443B9 (ko)
KR (1) KR100654475B1 (ko)
WO (1) WO2004064232A2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7486057B2 (en) * 2005-01-24 2009-02-03 Honeywell International Inc. Electrical regulator health monitor circuit systems and methods
US8836410B2 (en) * 2007-08-20 2014-09-16 Hynix Semiconductor Inc. Internal voltage compensation circuit
US8866341B2 (en) * 2011-01-10 2014-10-21 Infineon Technologies Ag Voltage regulator
EP3273320B1 (en) 2016-07-19 2019-09-18 NXP USA, Inc. Tunable voltage regulator circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2927264C2 (de) * 1979-07-05 1981-07-30 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung mit mindestens einer durchzuschaltenden Versorgungsspannungsquelle
US5402375A (en) * 1987-11-24 1995-03-28 Hitachi, Ltd Voltage converter arrangement for a semiconductor memory
US4868417A (en) * 1988-08-23 1989-09-19 Motorola, Inc. Complementary voltage comparator
DE19716430A1 (de) * 1997-04-18 1998-11-19 Siemens Ag Schaltungsanordnung zur Erzeugung einer internen Versorgungsspannung
DE19814696C1 (de) * 1998-04-01 1999-07-08 Siemens Ag Spannungs-Überwachungseinrichtung für zwei unterschiedliche Versorgungsspannungen eines elektronischen Geräts
JP3696470B2 (ja) * 2000-02-22 2005-09-21 富士通株式会社 Ｄｃ−ｄｃ変換回路、電源選択回路、および機器装置
WO2003034383A2 (en) * 2001-10-19 2003-04-24 Clare Micronix Integrated Systems, Inc. Drive circuit for adaptive control of precharge current and method therefor

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Publication number Publication date
KR100654475B1 (ko) 2006-12-05
EP1439443A1 (de) 2004-07-21
WO2004064232A2 (de) 2004-07-29
EP1439443B1 (de) 2015-09-09
US7501718B2 (en) 2009-03-10
WO2004064232A3 (de) 2004-09-16
US20060001321A1 (en) 2006-01-05
KR20050094844A (ko) 2005-09-28

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