Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters

Definitions

• the present invention relates to a time discrete PLL-tuning system, comprising a phase detector and a voltage controlled oscillator (NCO) for tuning the frequency (fvco) thereof to a frequency equal to ⁇ /M times a reference frequency (f RE F), with M a factor indicating the number of frequency steps in which a transmitter/receiver channel distance is divided and ⁇ the number of frequency steps in which the oscillator frequency is divided.
• NCO voltage controlled oscillator
• Such a tuning system is generally known and is applied in radio's tv's, mobile telephones, etc.
• the phase detector the difference between the phase of an input signal with a predetermined frequency step (fs TE p) and the phase of a signal derived from the NCO output signal by dividing the frequency thereof with the factor ⁇ is detected, filtered en fed back to the NCO.
• the frequency step (fsTEp) is equal to a reference frequency (fREF) divided by the factor M
• the NCO frequency is tuned to ⁇ /M times said reference frequency, i.e. to the frequency ( ⁇ /M)*f RE F-
• the reference frequency may be generated by a cristaloscillator.
• the accuracy of the frequency of the tuned oscillator on the one hand and the switching speed to switch the oscillator between different frequencies on the other hand are limited as a consequence of the low sampling rate of the control loop which locks the tuned oscillatorfrequency to a frequency proportional to the fixed reference frequency.
• the bandwidth of such a the tuning system will be about fs ⁇ p 10 (instead of the theoretical Niquist criterion fs ⁇ Ep/2).
• the FLL frequency locked loop
• the PLL has a large bandwidth, a high reference frequency and low accuracy
• the PLL has a small bandwidth, a low reference frequency and high accuracy. Due to this separation, however, a disadvantage with respect to fast switching from one channel to another is introduced because the exact frequency is controlled by the slow PLL only.
• the FLL provides for a suppression of the phase noise.
• the FLL presented in this paper is based on a frequency-to-voltage converter which is critical with respect to high frequency operation. In order to apply this circuit the clock frequency (spurious) of the FLL has to be reduced via a frequency divider compared to the high frequency of the NCO. That means that the fundamental advantage of the FLL can not be fully exploited.
• the purpose of the invention is to provide for a time discrete PPL-tuning system wherein the disadvantages of the above tuning systems are avoided, and which tuning system is accurate and has a high switching speed to switch the oscillator between two different frequencies. Therefore, according to the invention the time discrete PLL-tuning system is characterized in that the sampling frequency of the phase detector is substantial equal to the reference frequency (f RE F)- In the generally known PLL-tuning systems the sampling frequency is, as mentioned above, equal to fs TE p; according to the invention the sample frequency is M*f STE p.
• the spurious component has a frequency M*fs ⁇ EP which can be chosen far beyond the range of present neighbouring transmitter/receiver channels, so that a wide band tuning system can be obtained and thus a rapid switching speed, while the frequency step can still be low, resulting in a high tuning accuracy.
• Such a high sample frequency may be realized in a PLL-tuning system in which the phase detector comprises a first frequency-to-voltage converter, which in response to the NCO signal supplies an output signal (k ⁇ fvco) proportional to the oscillator frequency (fvco), a multiplier unit which in response to said output signal (k'*fvco) of the frequency-to- voltage converter supplies a signal (k*M*f V co) proportional to the product (fvco) of the oscillator frequency and a factor M, indicating the number of frequency steps in which a transmitter/receiver channel distance is divided, a reference signal unit which in response to a reference frequency signal supplies a signal (k* ⁇ *f REF ) proportional to the product of the reference frequency (f REF ) and a factor N, N being the number of frequency steps in which de oscillator frequency is divided, and a difference circuit supplying a signal proportional to the difference of the product of the oscillator frequency (fvco) and the factor M and of
• V c K* M *j[f VC0 - ⁇ f REF ) * dt ,
• the signals M and ⁇ may be supplied in digital form and are preferably adjustable.
• the multiplier unit may comprise a first DAC (digital-to- analogue converter) with a current output to convert the signal M into a current, and a first current switch controlled by the output signal of the first frequency-to-voltage converter.
• the reference signal unit may then comprise a second frequency-to-voltage converter, and a second DAC (digital-to-analogue converter) with a current output to convert the signal ⁇ into a current to be supplied to a second current switch, which second current switch is controlled by the output signal of the second frequency-to- voltage converter.
• each of the first and second frequency-to- voltage converter comprises an exclusive-or circuit to which the signal with the oscillator frequency and with the reference frequency respectively are supplied directly and after a delay ( ⁇ ), and low-pass filter means for filtering the output signal of the exclusive-or circuit.
• the delay ( ⁇ ) may be adjustable, which is important to obtain an accurate substantially equal adjustment of both values of the delay ( ⁇ ) in both frequency-to- voltage converters.
• Fig. 1 shows a generalized block schematic diagram of the PLL-tuning system according to the invention.
• Fig. 2 shows a preferred embodiment of the PLL-tuning system according to the invention.
• Fig. 1 shows a phase detector 1 and a voltage controlled oscillator (NCO) 2.
• the output signal of the phase detector 1 is the control voltage Nc for the NCO, while the output signal with the frequency fvco forms a first input of the phase detector 1.
• a signal with the reference frequency f REF forms a second input signal of the phase detector 1.
• the phase detector 1 comprises a frequency-to-voltage converter 3, a multiplier unit 4, a reference signal unit 5, a difference circuit 6 and a low-pass filter 7.
• this signal is multiplied with a factor M, indicating the number of frequency steps fsx EP in which a transmitter/receiver channel distance is divided.
• the output signal of the multiplier 4 may be represented by k*M*f V co, with k an adjustable factor or a constant, and supplied to the difference circuit 6.
• the reference signal unit 5 supplies, in response to a reference signal with frequency f REF , an output signal, which may be represented by k* ⁇ *f REF , with N the number of frequency steps in which the oscillator frequency is divided and k an adjustable factor or a constant, and supplied too to the difference circuit 6.
• the circuits 3, 4 and 5 may so be dimensioned that the signals M*f V co and N*f REF have the same proportionality factor or constant.
• the values N and M are supplied in digital form.
• the output signal of the difference signal M*fvco- N*fREF will be integrated in the filter 7, whereafter the control signal
• V c K* M *j[f VC0 - ⁇ f REF ) *dt is obtained, with an adjustable factor or a constant.
• the bandwidth of the control loop is about fREF 10.
• the spurious component with frequency f REF is far out of the range of the transmitter/receiver channels.
• a preferred embodiment is shown in fig. 2.
• the main structure of the block schematic diagram in this figure is the same as in fig. 1.
• the frequency-to-voltage converter 3 comprises an exclusive-or circuit annex low pass filter 8.
• the output signal of the NCO is supplied to the exclusive-or circuit annex low-pass filter 8 directly and after a relatively small delay ⁇ via a delay circuit 9.
• the low- pass filtered output signal of this frequency-to- voltage converter 3 is now proportional to ⁇ *fvco-
• the multiplier unit 4 comprises a DAC (digital-to-analogue converter) 10 with a current output and a current switch 11.
• DAC digital-to-analogue converter
• I REF reference current
• M current, proportional to M*i REF and supplied to the current switch 11.
• a current ii will pass the current switch 11, which current ii is proportional to ⁇ *iREF*M*fvco-
• the reference signal unit 5 has the same structure as the combination of the frequency-to-voltage converter 3 with the multiplier unit 4 and comprises a frequency-tot- voltage converter 12, a DAC 13 with a current output and a current switch 14. Therefore, the output current i 2 is proportional to ⁇ *i RE F* ⁇ *fREF- When the same DAC's, the same current switches and the same frequency-to-voltage converters are used, the proportionality constants of ii and i 2 are also the same, so that the output signal of the difference circuit will be proportional with ⁇ *i R EF*[M*fvco-N*f RE F].
• the not only the reference signal unit 5 has the same structure as the combination of the frequency-to-voltage converter 3 with the multiplier unit 4, but also the delay ⁇ is adjustable.
• the absolute accuracy of the delay is not important because it only effects the loop gain of the control loop which is a rather insensitive parameter.
• the dominant aspect for accuracy of the NCO frequency is the relative matching of the two delays in the different branches of the phase detector 1 and the accuracy of the DAC's.
• the most accurate implementation of the delay is a digital implementation with D-flipflops.
• phase detector 1 can be simplified by replaced by the frequency-to- voltage converter 3 and the multiplier 4, steered by the value M only.
• phase detector 1 can be simplified by the reference signal unit 5 steered by the value N only.

Landscapes

• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Priority Applications (1)

Applications Claiming Priority (4)

Publications (1)

Family

ID=8171358

Family Applications (1)

Country Status (6)

Families Citing this family (13)

Family Cites Families (7)

• 2001
  • 2001-04-04 WO PCT/EP2001/003826 patent/WO2001080427A1/en not_active Application Discontinuation
  • 2001-04-04 KR KR1020017016090A patent/KR20020029867A/ko not_active Application Discontinuation
  • 2001-04-04 JP JP2001577704A patent/JP2003531549A/ja active Pending
  • 2001-04-04 EP EP01936184A patent/EP1279231A1/en not_active Withdrawn
  • 2001-04-04 CN CN01800968A patent/CN1366734A/zh active Pending
  • 2001-04-13 US US09/834,837 patent/US6509802B2/en not_active Expired - Fee Related

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events