EP1256263A2 - Procede et appareil d'alimentation en courant d'un microprocesseur a gestion de chaleur integree et d'interference electromagnetique - Google Patents

Procede et appareil d'alimentation en courant d'un microprocesseur a gestion de chaleur integree et d'interference electromagnetique

Info

Publication number
EP1256263A2
EP1256263A2 EP01944108A EP01944108A EP1256263A2 EP 1256263 A2 EP1256263 A2 EP 1256263A2 EP 01944108 A EP01944108 A EP 01944108A EP 01944108 A EP01944108 A EP 01944108A EP 1256263 A2 EP1256263 A2 EP 1256263A2
Authority
EP
European Patent Office
Prior art keywords
circuit board
conductive
substrate
component
board assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01944108A
Other languages
German (de)
English (en)
Inventor
Joseph Ted Ii Dibene
David Hartke
James Hjerpe Kaskade
Carl E. Hoge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Incep Technologies Inc
Original Assignee
Incep Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Incep Technologies Inc filed Critical Incep Technologies Inc
Publication of EP1256263A2 publication Critical patent/EP1256263A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/181—Enclosures
    • G06F1/182—Enclosures with special features, e.g. for use in industrial environments; grounding or shielding against radio frequency interference [RFI] or electromagnetical interference [EMI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1092—Plug-in assemblages of components, e.g. IC sockets with built-in components, e.g. intelligent sockets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10325—Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10704—Pin grid array [PGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other

Definitions

  • the present invention relates to electronic systems, and in particular to a system and method for providing power to a component such as a processor while providing an integrated approach to managing thermal dissipation and electromagnetic interference.
  • the lowered operating voltage of the processor places greater demands on the power regulating circuitry and the conductive paths providing power to the processor.
  • processors require supply voltage regulation to within 10% of nominal. I-n order to account for impedance variations in the path from the power supply to the processor itself, this places greater demands on the power regulating circuitry, which must then typically regulate power supply voltages to within 5% of nominal.
  • Lower operating voltages have also lead engineers away from centralized power supply designs to distributed power supply architectures in which power is bussed where required at high voltages and low current, where it is converted to the low- voltage, high-current power required by the processor by nearby power conditioning circuitry.
  • FIG. 1 is a plot of a typical transient response 102 at the interface between the voltage regulator and the processor, and comparing that response with nominal 104 and minimum 106 supply voltages.
  • the transient interface voltage includes an initial spike which must not extend below an acceptable margin 108 above the minimum supply voltage, and a more sustained voltage droop 110.
  • I-n order to retain the supply voltage within acceptable limits 104 and 106 and to reduce variations in supplied power to the processor, the power and ground planes, power and ground vias, and capacitor pads must be designed to ensure low inductance power delivery paths to the processor.
  • FIG. 2 is a diagram of an exemplary distributed power supply system 200.
  • the power supply system 200 includes a motherboard 202 having a power supply unit 206 such as a DC/DC voltage regulator mounted thereon.
  • the motherboard 202 has a plurality of signal traces, including a first signal trace having a high- voltage/low- current (HV/LC) power signal 204 (which could also be supplied by a wire, for example).
  • the power supply unit 206 accepts the HN/LC power signal and via electrical circuitry including components 208, converts it to a conditioned high- current/low- voltage (HC/LV) signal 210 that is provided to a second signal trace in the motherboard 202.
  • HV/LC high- voltage/low- current
  • HC/LV conditioned high- current/low- voltage
  • a socket 214 is electrically coupled to the motherboard 202 via a first electrical connection 212, such as a ball grid array (BGA).
  • the socket 214 includes internal electrical connections for providing the HC/LV signal to pins 216 electrically coupled between the socket 214 and a power regulation module 218.
  • the power regulation module 218 is electrically coupled to a substrate 222 via a second electrical coupling 220 such as a BGA.
  • the processor (e.g. the die) 226 is electrically coupled to the substrate 222 via a third electrical coupling 224.
  • the HC/LV signal is provided to the processor via the circuit path described above. As described earlier distributed power systems such as is illustrated in FIG. 1 still result in unacceptable impedances that cause voltage drops in the power distribution path.
  • surge currents are managed by placing decoupling capacitors 228 and other components throughout the power delivery subsystem, including on the power regulation module 218, on the motherboard, on the processor die package, and on the die itself. This not only increases costs, but consumer critical silicon area, chip package and board real estate. Further, for microprocessors operating at more than 200 MHz, the only serviceable capacitor is an on-die capacitor, or one that is very close to the die. On-die capacitors are common in PC-class processors. The need for higher performance and increased functional integration in smaller processor dies has also lead to higher heat-flux concentrations in certain areas of the processor die. hi some cases, the resulting surface energy densities approach unmanageable levels. Processor reliability is exponentially dependent on the operating temperature of the die junction. Lowering temperatures in the order of 10- 15 degrees centigrade can double the processor lifespan. Thermal management issues now present some of the largest obstacles to further processor miniaturization and increases in processor speed.
  • EMI Electromagnetic interference
  • the processor 226 is by far the largest source of electromagnetic energy . Containing radiated and conducted emissions at the source (at the processor package) would make the system design easier for computer OEMs. Because of the generation of higher order harmonics, Federal Communications Commission (FCC) regulations require emission testing at frequencies up to five times the processor clock frequency or 40 GHz, whichever is lower.
  • FCC Federal Communications Commission
  • the primary component of EMI is a radiated electromagnetic wave which gets smaller as frequencies increase.
  • EMI management which generally is performed on the chassis level rather than the component level, is typically accomplished by reducing the size of openings in the system, effectively blocking the electromagnetic waves. However, using smaller apertures introduces thermal management problems because of decreased airflow.
  • Another method for reducing EMI is to ground any heat sinks.
  • Noise coupled from the processor package to the heat sink may cause the heat sink to act as an antenna and re-radiate the noise.
  • it is typically not possible to ground the heatsink through the processor package.
  • the grounding of the heatsink may reduce EMI, this technique is typically insufficient to meet EMI requirements, and additional shielding is typically necessary.
  • the present invention discloses a modular circuit board assembly and a method for making same.
  • the modular circuit board assembly comprises a substrate, having a component mounted thereon, a circuit board, including a circuit for supplying power to the component, and at least one conductive interconnect device disposed between the substrate and the circuit board, the conductive interconnect device configured to electrically couple the circuit to the component.
  • the circuit board includes a voltage regulation module (VRM) and a plurality of non-compressible conductive standoffs are used to mount the circuit board to the processor substrate.
  • VRM voltage regulation module
  • This embodiment provides a modular package in which the mechanical standoffs serve many purposes. First, they provide a low inductance path directly to the processor, rather than the higher inductance path through the substrate, socket and other elements depicted in FIG. 2. Second, they provide the proper z-axis (typically vertical) physical relationship between the substrate and the circuit board. The modular assembly can be plugged into a socket on the motherboard, and all of the pins on the socket can be used as signal pins instead of power pins. This also allows the processor to be easily separated from the motherboard, even while providing power, if desired. This embodiment also provides the advantage of permitting a robust, consistent thermal and mechanical interface to a heatsink or other thermal dissipation device.
  • Compressible or other compliant interfaces can be used to manage the physical and thermal connection between the circuit board, VRM components and other components on the circuit board, as well as the processor. These interfaces can provide a compression thermal coupling for the thermal interface of the microprocessor that can be adapted to a wide range of operating requirements.
  • the conductive interconnect device comprises concentric conductive spring devices disposed about the periphery of the component. Since this embodiment does not require the use of an interposer board, it is more compact, and easier and less expensive to manufacture. This embodiment also permits the top surfaces of the VRM circuit board and the processor to be substantially co-planar, allowing a better surface for physical and thermal mating with the heat sink.
  • the spring action provided by the conductive interconnect device provides a low-inductance electrical connection and a flexible mechanical spring force to control the thermal and mechanical interface between the heat sink, the processor, and the VRM board.
  • Another advantage of this embodiment is that screws are not required to make the electro-mechanical connection between the VRM board and the substrate. Instead, mechanical connection can be accomplished by spring fingers and similar simple devices. Further, the spring fingers can be applied as the last step in assembly.
  • the present invention includes an architecture that differs from conventional microprocessor packaging architectures in that it addresses all the significant off-chip requirements that affect the performance and reliability of the microprocessor using symbiotic relationships between architecture elements.
  • the architecture uses a low cost, coaxial interconnection and physically integrates the high current delivery capability of the coaxial connection with custom designed power regulators to provide self-contained and physically separable power delivery modules that can be connected to interposer boards, OLGAs, CLGAs or other area array packages.
  • Microprocessor and power regulator thermal dissipation requirements are both satisfied by using an integrated heatsink that provides a thermal power dissipation path for both sources of heat.
  • the integrated architecture also includes an electrically conductive frame and associated fittings and hardware that electrically couples with the heatsink and encases the microprocessor, power delivery module and other circuits to minimize and contain EMI within the package rather than within the chassis.
  • the present invention boosts the volumetric form factor efficiency of the microprocessor.
  • signal integrity/performance, manufacturability, reliability and cost effectiveness are also improved.
  • the architecture is suitable for the generation of three dimensional solutions for microprocessor and electronic circuits configurations that are pre-packaged on, or pre- connected to, interposer boards, OLGAs using BUM technology, CLGAs, Flip-Chip Pin Grid Arrays (FC-PGAs), Flip Chip Ball Grid Arrays (FC-BGAs), as well as other electronic circuits substrates and bare chips.
  • the architecture provides packaging solutions that include custom designed modules, interconnections and component hardware that are physically separable but can also be interconnected and combined to form connectable modules or packages that permits direct attachment of lidded or unlidded substrates bonded to microprocessors or other electronic circuits including, but not limited to, multi-chip modules.
  • This architecture is extendable to direct chip attach of microprocessors or microcircuits into custom designed and integrated cavity package formats that can also be configured to function as test sockets.
  • FIG. 1 is a plot of a typical transient response at an interface between a voltage regulator and a processor
  • FIG. 2 is a diagram of an exemplary distributed power supply system
  • FIG. 3 is a diagram of a typical microprocessor or electronic circuit package
  • FIG. 4 is a diagram of a circuit board
  • FIG. 5 is a diagram showing the combined elements of FIG. 3 and FIG. 4;
  • FIG. 6 A is a diagram showing one embodiment the power regulation module of one embodiment of the present invention.
  • FIG. 6B is a diagram showing an assembly following connection of conductive standoffs to a circuit board through plated-through holes
  • FIG. 7 is diagram showing a substrate assembly
  • FIG. 8 is a diagram a modular circuit board assembly
  • FIG. 9 is a diagram showing an assembled modular circuit board assembly
  • FIG. 10 is a diagram showing an integrated heatsink system
  • FIGs. 11 A is a diagram showing the integrated heatsink system positioned above the modular circuit board assembly
  • FIG. 1 IB is a diagram showing the integrated heatsink system interconnected with the modular circuit board assembly
  • FIG. 12 is a diagram showing the integrated i-PAK structure with an electrically conductive frame to minimize EMI;
  • FIG. 13 is a diagram presenting a view of a second embodiment of the power delivery module
  • FIG. 14 is a diagram presenting a perspective view of the conductive interconnect device
  • FIG. 15 is a diagram showing an edge view of the power regulator and delivery module following attachment of a conductive interconnect device
  • FIG. 16 is a diagram showing a second embodiment of the substrate assembly
  • FIG. 17 is a diagram illustrating the power regulator module positioned and aligned over the substrate assembly
  • FIG. 18 is a diagram presenting the power regulator module and substrate assembly
  • FIG. 19 is a diagram showing one embodiment of an integrated thermal power dissipation system
  • FIG. 20 is a diagram illustrating one embodiment of the present invention with including the power regulator, substrate assembly, and the integrated thermal power dissipation system;
  • FIGs. 21 A-21B are diagrams of the assembly of FIG. 20 further modified to minimize EMI;
  • FIG. 22 is a diagram illustrating one embodiment of a Monolithic Enabling Module
  • FIGs. 23 A-23D are diagrams illustrating one embodiment of a method for electrically coupling the microprocessor circuits to the substrate
  • FIG. 24 is a diagram illustrating another embodiment of an integrated thermal power dissipation module
  • FIG. 25 is a diagram showing the use of an integrated thermal power dissipation module with the Monolithic Enabling Module
  • FIG. 26 is a diagram showing a modification of the Monolithic Enabling Module and integrated thermal power dissipation module with an EMI reduction frame assembly;
  • FIG. 27 is a diagram showing another embodiment of a portion of the conductive interconnect device.
  • FIG. 28 is a diagram further illustrating a second portion of the conductive interconnect device with a split wedge washer and screw fastener
  • FIG. 29 is a diagram showing the assembled conductive interconnect device
  • FIG. 30 is a diagram showing a further embodiment of the conductive interconnect device
  • FIG. 31 is a diagram showing a cross-sectional view showing an implementation of the embodiment of the conductive interconnect device illustrated in FIG. 30;
  • FIG. 32 is a diagram showing exemplary method steps used to practice one embodiment of the present invention.
  • FIG. 33 is a diagram showing exemplary method steps used to practice a further embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a typical microprocessor or electronic circuit package 300.
  • a lid 304 which is usually composed of copper or other high thermal conductivity material is bonded to a substrate 302 using adhesive or metallurgical connection at junction 306.
  • a microprocessor or electronic circuit 310 Also bonded to the substrate 302 is a microprocessor or electronic circuit 310.
  • the connection between the substrate and the processor 310 can be made using solder balls (bumps) known as "flip-chip” or C-4 (controlled collapse chip connection).
  • the physical gap between the substrate 302 and the processor 310 is occupied by a polymeric composite called an underfill.
  • the underfill adds mechanical strength to the joint formed between the substrate 302 and the processor 310 and functions to encapsulate the processor 310 in a manner analogous to a liquid encapsulant or a mold compound.
  • the space between the back surface of the processor and the underside of the lid 304 is occupied by a thermal grease known as Thermal Interface Material -1, (TIM-1).
  • TUM-l provides a thermal power dissipation path from the back surface of the processor 310 to the inner surface of the lid 304.
  • the outer surface of the lid 304 is coated with a thermal grease 312 known as T ⁇ M-2.
  • the underside of the substrate 302 contains an array of metal pads 314 that are electrically connected to the solder balls of the processor 310.
  • the substrate 302 can be a Built-up Multilayer (BUM), an Organic Land Grid Array (OLGA) or an inorganic substrate known as a Ceramic Land Grid Array (CLGA).
  • BUM Built-up Multilayer
  • OLGA Organic Land Grid
  • FIG. 4 is a diagram illustrating a circuit board 402 with an array of metal pins 404 on the underside.
  • the pins 404 are connected to the top surface of the circuit board through internal vias.
  • a surface mount socket 406 accommodates and makes electrical connection between the pins 404 and an array of solder balls 408.
  • FIG. 5 shows the elements depicted in FIGs. 3 and 4 connected and stacked together, and placed on a motherboard 502.
  • microprocessors typically obtain power from power conditioning modules (e.g. power regulators and/or DC/DC converters) which are disposed at a distance from the microrprocessor though circuit paths in the motherboard 502.
  • Power delivery proceeds from the power regulator through the motherboard 502 into the surface mount socket 406, through pins 404 to the circuit board 402 through metal pads 314, the substrate 302 and finally through the C-4 connection to the electronic circuit 310.
  • This route provides a lengthy path through several connections that can impair signal integrity and produce high electrical impedance.
  • hundreds of power delivery connections (pins) may be need to provide high current to the microprocessor or electronic circuits 310.
  • This design places constraints on the multi-layer substrate 302, because power must be brought through many different layers before reaching the processor circuit 310 itself.
  • FIG. 6 A is a diagram showing one embodiment of the power regulation module 600 of the present invention.
  • the power regulator module 600 comprises a circuit board 602.
  • the circuit board 602 includes a power conditioning, regulation, or supplying circuit that is configured to supply power to a power dissipating element such as a processor (not shown in FIG. 6).
  • the circuit board 602 can include components such as components 608A and 608B (collectively referred to hereinafter as component(s) 608) that can be part of the power conditioning circuit, or may be for the purpose of performing other functions.
  • Thermal vias 606 are arranged within the circuit board 602 to provide an electrical path from a first or under surface 614A of circuit board 602 to a second or upper surface 614B of the circuit board 602.
  • Thermal vias 606 can thus provide an electrical path for the components(s) 608 from the lower surface of the circuit board 614A to the upper side 614B of the circuit board 602, from layer to layer within the circuit board 602. Thermal vias 606 can also provide thermal coupling 608 to transfer heat from the first surface of the circuit board 614A to the second surface of the circuit board 614B .
  • the circuit board 602 also includes an aperture 604, through which the processor is disposed upon assembly.
  • the circuit board 602 also includes one or more plated-through holes 610 (e.g. copper-plated), hi one embodiment, the plated through holes 610 are disposed proximate to and symmetrically about the aperture 604.
  • One or more circuit board conductive surfaces e.g.
  • the circuit board conductive surfaces 616 comprise a circuit board first conductive surface 616A and a circuit board second conductive surface 616B, and the conductive interconnect devices 612 include a first portion 612A and a second portion 612B separated by a dielectric portion 612C.
  • first portion 612A is electrically coupled to circuit board first conductive surface 616A and the second portion 612B is electrically coupled to the circuit board second conductive surface 616B.
  • the conductive interconnect device is a conductive standoff or a spacer.
  • the conductive interconnect device 612 provides serves dual purposes. First, it provides mechanical coupling between the circuit board 602 and the substrate 302, providing sufficient separation between the circuit board 602 and the substrate 302.
  • the conductive interconnect device 612 may also be configured not only to separate the circuit board 602 and the substrate 302, but with suitable attachment devices, to keep the circuit board 602 and the substrate 302 together.
  • the other function provided by the conductive interconnect device 612 is to provide one or more conductive paths from the circuit board 602 to the substrate 302. Typically, two conductive paths are provided, including a first conductive path for a power signal and a second conductive path for a ground.
  • FIG. 6B is a diagram showing the assembly following connection of the conductive standoffs 612 to the circuit board 602 through the plated-through holes 610.
  • FIG. 7 is a diagram showing a substrate assembly 700 of the present invention.
  • the substrate assembly 700 is similar to the substrate assembly discussed with reference to FIGs. 3-5, but with important differences that are described herein.
  • This substrate assembly 700 is part of an integrated architecture alternatively referred to hereinafter as the i-PAK architecture, h this embodiment, the area of the substrate is enlarged relative to the size of substrate 302 in FIG. 5, to accommodate plated through-holes 704 and an array of pins 706.
  • a first (top) surface of the substrate 702 includes a first conductive surface
  • FIG. 8 is a diagram showing the modular circuit board assembly 800, including the substrate assembly 700 and the power regulation/delivery module 600. Fasteners 802 mechanically and electrically connect to the modular circuit board assembly 800 to the substrate assembly 700.
  • FIG. 9 shows the assembled modular circuit board assembly 800.
  • FIG. 10 is a diagram showing an integrated heatsink system 1000 for the integrated architecture for the i-PAK modular circuit board assembly 800.
  • the heat sink system 1000 includes a thermally conductive and compressibly compliant interface material 1002 such as a TI-M-2 thermal grease, a high thermal conductivity spacer plate 1004 that precisely fits into the cutout in 604, a large planar heatsink 1006 and a further thermally conductive and compressibly compliant interface material 1008 such as thermal grease.
  • the spacer plate 1004 can be physically connected to the heatsink 1006 or can be thermally connected to 1006 using a plate 1010.
  • FIG. 11 A is a diagram showing the integrated heatsink system 1000 positioned above the modular circuit board assembly 800.
  • FIG. 1 IB is a diagram showing the integrated heatsink system 1000 after connecting the connection of the heatsink system 1000 with the modular circuit board assembly 800.
  • This integrated i-PAK architecture physically connects a thermal power dissipation path from the top of the microprocessor lid 304, through TIM-2 1002, through the spacer plate 1004 to the bottom surface of the heatsink 1006.
  • Also connected to the heat sink 1006 is the surface of the power regulation module 600 through thermal grease 1008 or other suitable interface.
  • FIG. 1 IB also illustrates how the modular circuit board assembly 800 may be coupled to the integrated heat sink system 1000.
  • the heat sink 1006 or plate 1010 may include an indentation 1106 in which a fastening device 1102 is inserted and secured.
  • the fastening device 1102 couples to an extension member 1104.
  • the extension member couples to a second fastening device 1108.
  • FIG. 12 is a diagram showing the incorporation of an electrically conductive frame 1202 that substantially surrounds the periphery of the processor 310, and is physically connected to the integrated heatsink 1006.
  • This frame 1202 when connected to the heatsink 1006 and subsequently connected to a stiffener board 1206 or motherboard and held together by fastener springs 1204, forms a three dimensional enclosure that captures electromagnetic radiation generated by the microprocessor, power regulator and associated circuitry at the package level instead of at the chassis level.
  • the frame 1202 is also electrically coupled to the integrated heatsink 1000. This combination (e.g.
  • the present invention can be practiced in another embodiment that achieves many of the advantages of the i-PAK architecture, but in a smaller package.
  • FIG. 13 is a diagram presenting a view of the bottom surface 614A of another embodiment of the power delivery module 1300.
  • the power delivery module 1300 includes a power delivery module circuit board 1310.
  • a portion (preferably the center) of the power delivery module circuit board 1310 includes an aperture 1302 and conductive surfaces 1306 and 1304.
  • the conductive surfaces are concentric metal rings.
  • Conductive surfaces 1306 and 1304 connect to power and ground in the regulator and delivery module 1300.
  • conductive surfaces 1306 and 1304 function much like the circuit board first conductive surface 616 A and the circuit board second conductive surface 616B, respectively, in that they provide a path for providing power and ground, respectively, to the processor 310.
  • FIG. 14 is a diagram presenting a perspective view of a second embodiment of the conductive interconnect device 1400.
  • This second embodiment of the conductive interconnect device is described by two characteristics. First, unlike the previously described embodiment, this embodiment of the conductive interconnect device surrounds the component. Second, unlike the previously described embodiment, this embodiment of the conductive interconnect device establishes electrical connection between the power delivery module 1300 and it's associated circuits and the substrate by use of compressibility in the z (vertical) axis.
  • the conductive standoff device 1400 includes a first conductive standoff portion 1402 and a second conductive standoff portion 1404. hi the illustrated embodiment, the first 1402 and second conductive standoff 1404 portions are arranged concentrically.
  • the conductive interconnect device 1400 includes a plurality of compressible conductive springs (e.g. microsprings). The plurality of compressible conductive springs may include a first (inner) plurality of compressible conductive springs 1402 and a second (outer) plurality of compressible conductive springs 1404.
  • the first conductive standoff portion 1402 and the second conductive standoff portion 1404 are aligned with and can be electrically connected to the power delivery module circuit board 602 conductive surfaces 1306 and 1304, respectively. This can be accomplished by a number of methods, including conventional soldering, reflow soldering, bonding, friction techniques.
  • FIG. 14 illustrates but one embodiment of the conductive interconnect device.
  • Other conductive interconnect device embodiments are also possible and are within the scope of the present invention, particularly those which include either contact achieved through compressibility along the z-axis or which substantially surround the component.
  • FIG. 15 is a drawing showing an edge view of the power regulator and delivery module 602 following attachment of the inner plurality of compressible springs 1402 and the outer plurality of compressible springs 1404 to the bottom surface of the power delivery module 602 at conductive surfaces 1304 and 1306. Also shown are two of the through-holes 1308 in the power delivery module. These through-holes 1308 are used for screw-type connections but are not needed for other connections including, but not limited to, clips, clamps or fasteners.
  • FIG. 16 is a diagram showing an embodiment of a substrate assembly 1600 for use with the power regulator and delivery module circuit board 602 with the compressible springs 1402 and 1404.
  • the substrate assembly 1600 can be either a BUM or a CLGA substrate or similar.
  • the substrate 1600 illustrated in FIG. 16 does not include a package lid 304 or thermal grease 312 (TIM-2).
  • TIM-2 thermal grease 312
  • the substrate illustrated in FIG. 16 includes two precisely sized substantially non-conductive standoffs 1604 A and 1604B.
  • the non-conductive standoffs 1604 include a first portion 1604A which is coupled to the substrate 1602 near the processor 1606, and a second portion 1604B which extends from the substrate 1602.
  • the processor 1606 is electrically coupled to the substrate 1602. This can be accomplished with C-4 connections 1608 to an array of metal pads (not shown) on the top surface of the substrate 1602.
  • An underfill 1610 encapsulates the processor 1606.
  • Conductive pins 1612 are electrically connected to the substrate 1602, and through circuit paths in the substrate 1602, metal pads, and C-4 connections, to the processor 1606.
  • Two (or more) conductive surfaces 1616 and 1614 are located on the top surface 1620 of the substrate 1602.
  • the conductive surfaces 1616 and 1614 provide for electrical contact between the conductive standoff member 1400 (and hence the circuit board 602) ' and the substrate 1620.
  • the conductive surfaces 1616 and 1614 are concentric metal window frame areas, complimentary in shape, size, and location to the conductive surfaces 1306 and 1304.
  • the inner frame area or ring 1614 is configured to accept the inner compressible springs 1402 and the outer frame area or ring 1616 is configured to make electrical contact with the outer compressible springs 1404 when the circuit board 1310 is aligned and mated to the substrate assembly 1600.
  • FIG. 16 also illustrates through holes 1618, that align and compliment through holes 1302 on the circuit board 1310. These holes are used for connecting the substrate assembly 1600 with the circuit board 1310, but are not needed for other connecting techniques, including, but not limited to those techniques using clips, clamps, or fasteners.
  • FIG. 17 is a diagram illustrating the power regulator module 1300 (depicted in FIG. 15) positioned and aligned over the substrate assembly 1600.
  • the edges of the cutout 1302 in the circuit board 1310 align with the standoffs 1604.
  • the standoff 1604 includes first portion 1604 A or a shoulder that is disposed to prevent the inner compressible springs 1402 and the outer compressible springs 1404 from bottoming out (potentially permitting undesirable contact between the bottom surfaces of the power regulator module 1300 and the top surfaces of the substrate assembly 1600, circuit board 1602 or components thereon).
  • the standoff 1604 also includes a second portion 1604B of a vertical dimension selected such that when the power regulator module 1300 is mounted on the substrate assembly, the top surface of the second portion 1604B is substantially coplanar with the top surface of the power regulator module 1300, thereby presenting a substantially planar surface for inclusion of a heat dissipating device such as a heat sink, if desired.
  • FIG. 18 is a diagram presenting an illustration of the configuration of FIG. 17 following placement of the power regulator and delivery module 1300 onto the substrate assembly 1600.
  • the conductive surfaces 1614 and 1616 on the substrate 1602 align and physically touch inner compressible springs 1402 and outer compressible springs 1404, respectively.
  • Fasteners which can include clips, pins, clamps or other forms of mechanical joining are used to connect the power delivery module 1300 to the substrate assembly 1600.
  • FIG. 18 shows an embodiment wherein apertures 1308 and 1618 align together to form a space in which a fastener may be inserted to affix the circuit board 1310 and the substrate 1602 together.
  • FIG. 18 also shows an embodiment wherein the circuit board 1310 includes an aperture 1802 to accept a circuit board fastener 1804.
  • An adaptation member 1806 is coupled to the circuit board 1310 via the fastener 1804.
  • FIG. 19 is a diagram showing one embodiment of an integrated thermal power dissipation system 1900 for use in the micro i-PAK architecture.
  • An integrated heatsink 1902 is thermally coupled to a high thermal conductivity spacer plate 1904 to form a monolithic unit.
  • the spacer plate 1904 is not needed.
  • a thermal grease (e.g. T ⁇ M-1) 1906 physically contacts the underside of the spacer plate or contacts the underside of the heatsink 1902 if the spacer plate 1904 is not used.
  • a second thermal grease 1908 contacts the underside of the heatsink 1902 away from the spacer plate 1904 or T ⁇ M-1 1906, if the spacer plate 1904 is not used.
  • alignment fasteners 1910 are affixed within recesses 1912. Although not necessary to practice the present invention, recesses 1912 provide clearance for the integrated heatsink 1902. Other embodiments using fasteners with heads designed to be flush with the bottom surface of the integrated heatsink 1902 or to fit within specially designed recesses 1912 are also possible.
  • the fasteners 1910 are placed through the apertures or holes 1618 and 1308 as described below.
  • FIG. 20 is a diagram illustrating the configuration of the micro i-PAK architecture following the attachment of the integrated thermal power dissipation system to the substrate 1602 and power regulator and delivery module 1300.
  • the top surface of the microprocessor 1606 physically contacts the thermal grease 1906 which contacts the spacer plate 1904 (if needed).
  • the base of the integrated heatsink 1902 contacts the top surface 1912 of the non-conductive standoff 1604.
  • the non- conductive standoff 1604 absorbs the weight of the heat sink 1902 and the spacer plate 1904, and to eliminates the mechanical stress that would otherwise be placed upon the C-4 connections 1608 by the integrated thermal power dissipation system 1900.
  • the thermal grease 1908 occupies the gap between the circuit board 1310 and the heatsink 1902 to provide a thermal power dissipation path from the power regulator and delivery module to the integrated heatsink 1902.
  • the fasteners 1910 may protrude into recesses 1912 located in the heatsink 1902.
  • Nuts or similar devices 2002 are affixed to the fastening devices 1910 to bring the substrate 1602 and the circuit board 1310 together, and bring the heatsink, circuit board 1310, and substrate 1602 into alignment.
  • the heat sink 1902 includes recesses 2004 that accept the fastener 1804 and affix the heat sink to the circuit board 1310 (and hence, the substrate 1602, which is attached to the circuit board 1310 by the alignment fasteners and the nuts 2002).
  • FIG. 21 A shows an extension of the integrated architecture for the micro i-
  • PAK architecture to incorporate a frame assembly for reducing EMI 2102.
  • the EMI frame 2102 mechanically connects to the integrated heatsink 1902 via fastener 1804 to form an enclosure that can be configured with accompanying hardware and an electrically conductive stiffener board or motherboard to form a three dimensional enclosure for the microprocessor or electronic circuits, power regulator and delivery module and associated components.
  • Clips 2104 can be used to further mechanically couple the heatsink 1902 to the remainder of the assembly. This configuration provides EMI containment at the package level, in this case, micro i-PAK, rather than at the chassis level.
  • FIG. 2 IB illustrates a modified embodiment of the integrated architecture in which the integrated heatsink 1902 is coupled to the remainder of the assembly via clips 2104 alone. Different combination of screws, dowels, clips and the like can be used to align the elements of the integrated assembly and affix them together.
  • the bottom surface of the circuit board 1310 resides on the shoulder 1604A of the standoff 1604 to provide precise electrical connection between the conductive surfaces 1304 and 1306 and conductive surfaces 1616 and 1614, via second conductive standoff portion 1404 and first conductive standoff portion 1402, respectively.
  • the electrical connection shown in FIG. 18 between the power delivery module 1300 and the substrate 1602 with microprocessor or electronic circuits can take a variety of forms and need not be limited to spring connections with fasteners.
  • the connection can include, but is not limited to, solder bonding, mechanical joining or diffusion bonding.
  • a dielectric adhesive layer can be pre-applied to either the circuit board 1310 or substrate 1602 to provide mechanical strength between the two surfaces in a manner similar to the use of underfill for solder bump (C-4) protection.
  • MoEM Monolithic Enabling Module
  • IPVR in-package- voltage regulation
  • FIG. 22 is a diagram illustrating one embodiment of the MoEM 2200.
  • the MoEM includes a substrate 2202 and an IPVR module 2204 both of which are permanently configured to be connected electrically and mechanically to each other.
  • An array usually configured as, but not limited to metal pins 2206, is positioned on the underside of the substrate 2202 to form electrical paths through the substrate 2204 to an array of, but not limited to, metal pads 2208 located in the central portion of the top surface of the substrate 2202.
  • a portion of the metal pads 2208 are power and ground connections that are electrically connected to the IVPR module 2204 through metal planes in the substrate 2202.
  • Standoffs 2214 are positioned on the top surface of the substrate 2202 to protrude slightly above the surface of the IVPR module 2204.
  • the array of metal pads 2208 correspond to the input/output footprint of the microprocessor or electronic circuits 2210 which is configured with an array of solder bumps 2212 that are permanently bonded to the microprocessor 2210 and form the input/output connection for the electronic circuits.
  • Each of the solder bumps in the array of solder bumps 2212 are disposed to make electrical contact with a respective metal pad 2208.
  • the array of metal pads 2208 can be configured as micro-socket pins to accept the array of solder bumps 2212 of the microprocessor or electronic circuits 2210 .
  • the MoEM 2200 then functions as a test socket for the microprocessor 2210 or as a package wherein the microprocessor is not permanently attached to the MoEM 2200 and can be mechanically removed.
  • FIGs. 23A-23D are diagrams illustrating one embodiment of a method for attaching the microprocessor or electronic circuits 2210 into the substrate 2202 when not configured as a test socket.
  • the microprocessor 2210 is positioned over a cavity formed by the substrate 2202, and standoffs 2214.
  • the microprocessor 2210 is placed onto the array of metal pads
  • solder bumps 2212 physically contact the metal pads 2208.
  • the solder bumps 2212 and pads 2208 form metallurgical connections using the C-4, reflow soldering method.
  • FIG. 23C illustrates the application of an underfill 2302 which can be a thermoset or thermoplastic resin loaded with dielectric fillers.
  • FIG. 23D is a diagram showing the completed connection after the underfill is cured or hardened 2304.
  • FIG. 24 is a diagram illustrating an integrated thermal power dissipation module 2400.
  • the module 2400 comprises an integrated heatsink, 2402, a thermal grease such as TIM-1 2404 and second thermal grease 2406. Alignment pins or screws 2408 can be glued, brazed, or otherwise attached to the integrated heatsink 2402.
  • FIG. 25 is a diagram showing the attachment of the integrated heatsink 2402 with thermal greases 2404 and 2406 to the MoEM 2200.
  • the base of the integrated heatsink 2402 is positioned vertically by the standoffs 2214.
  • the thermal grease, TIM-1, 2404 directly contacts the back surface of the microprocessor or electronic circuits 2210 to form a direct thermal power dissipation path to the integrated heat sink 2402.
  • the top surface of the IVPR module 2204 directly contacts the thermal grease 2406 to form a thermal power dissipation path from the top surface to the integrated heat sink. Because the vertical standoffs 2214 support the integrated heatsink 2402, minimal compressive force is exerted by the weight of the heatsink 2402 into the solder bump connections 2212.
  • a high thermal conductivity spacer plate (not shown) can be physically and mechanically attached to the integrated heatsink 2402 and configured to contact the thermal grease (TIM-1) 2404.
  • FIG. 26 is a diagram showing an extension of the integrated arcl itecture for the MoEM to incorporate the EMI reduction frame assembly 2602.
  • the EMI frame 2602 electrically and mechanically connects to the integrated heatsink 2402 to form an enclosure that can be configured with accompanying hardware and an electrically conductive stiffener board to form a three dimensional enclosure for the circuitry associated with the microprocessor or electronic circuits.
  • FIG. 27 is a diagram showing another embodiment of the conductive interconnect device 2700 similar to that which is disclosed in FIG. 6 as element 612.
  • a power pin 2702 is mounted to substrate 2704 through a connection device such as solder or press pin 2706 which connects electrically to inter-plane 2708 in the substrate 2704.
  • Solder or press pin 2706 is connected to plated through-hole 2710 electrically and mechanically.
  • a dielectric insulator 2712 isolates the power pin 2702 from a ground portion 2718.
  • the hollow center section 2716 of the power pin 2702 is threaded for accepting a screw. Additionally, tapered top portion 2714 is constructed to allow an electrical joint attachment.
  • FIG. 28 is a diagram illustrating a split- wedge washer and screw fastener construction for use with the constructive standoff device illustrated in FIG. 27.
  • the split-wedge washer 2802 includes a lip portion 2804 for a circuit board in contact therewith toward the substrate 2704.
  • Wedge section 2806 includes a taper 2806 substantially adapted to the taper 2714 of the power pin 2702.
  • Split section 2808 allows the washer 2802 to expand and contract along a circumferential axis as the matching taper portions are forced together as the screw 2810 is inserted into the center section 2716.
  • FIG. 29 is a diagram showing the attachment of the elements of FIG. 28 with the structure shown in FIG. 29 and integrated with a circuit board 2902 having, for example, power conditioning circuitry.
  • the split-wedge washer 2802 engages electrically and mechanically to the side of plated through hole 2906 in the circuit board 2902 by having taper section 2806 of the washer 2802 spread outward to force against the interior surface of the plated through hole 2906.
  • FIG. 30 illustrates a low inductance conductive 'frame' standoff sub-assembly
  • a sheet metal frame is bent and joined at one corner to form an outer ground frame 3002 with solder tabs 3010 for mounting permanently a circuit board (either INCEP board or main board).
  • a dielectric material such as dielectric tape 3006 is attached to this structure as an insulator.
  • Inner frame 3004 is made in similar fashion to the outer frame 3002 but carries current (e.g. from a positive terminal of power supply) to supply power to the component.
  • Mounting holes 3008 are supplied to mount to one side of the assembly to make mechanical and electrical connection. Due to the dimensions of the construction, and the current paths for the electrical interconnect, a very low inductance can be achieved resulting in a low voltage drop between the power supply and load for low frequency switching applications.
  • FIG. 31 is a diagram presenting an cross sectional view showing one implementation of the low inductance frame standoff sub-assembly 3000.
  • a processor 3110 is electrically coupled to a substrate 3112, which is electrically coupled to an interface board 3102, which is coupled to a main board 3104.
  • Power and ground connectivity is supplied from circuit board 3108 to the interface board 3102 by the inner 3004 and outer 3002 frame members, and thence to the processor via substrate 3112.
  • the interface board 3102 is to remove any need to mount power directly to the main board which can improve rout ability and cost on the main board.
  • FIG. 32 is a diagram presenting illustrative method steps used to practice one embodiment of the present invention.
  • At least one conductive interconnect device is mounted 3202 between a substrate having a component mounted thereto and a circuit board having a power circuit.
  • a electrically conductive surface on the substrate is electrically coupled with an electrically conductive surface on the circuit board through the conductive interconnect device, as shown in block 3204.
  • FIG. 33 is a diagram presenting illustrative method steps used to practice another embodiment of the present invention.
  • a first power circuit signal is accepted 3302 in a power circuit implemented on a circuit board.
  • a second power signal is generated 3304 from the first power signal, h one embodiment, the first power signal is a high-voltage/low-current signal, and the second power signal is low- voltage/high- current signal. In another embodiment, the second power signal is a conditioned or regulated modification of the first power signal.
  • the second power signal is supplied 3306 from the power circuit to the component on a substrate via at least one conductive interconnect device mechanically coupling the circuit board to the substrate.
  • the present invention discloses a three-dimensional interconnection architecture for electronic circuits, such as microprocessors, that integrates power delivery, thermal power dissipation, Electromagnetic Interference (EMI) reduction, signal integrity/performance, manufacturability, reliability, cost effectiveness and form factor optimization.
  • EMI Electromagnetic Interference

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Abstract

L'invention concerne une architecture d'emballage de microprocesseur utilisant un ensemble de carte de circuit modulaire qui produit du courant à un microprocesseur, tandis qu'il génère également une interférence électromagnétique (EMI) et thermique intégrée. Ledit ensemble de carte de circuit modulaire comprend un substrat pourvu d'un composant, une carte de circuit comprenant un circuit d'alimentation du composant et au moins un dispositif d'interconnexion conducteur disposé entre le substrat et la carte de circuit, ledit dispositif d'interconnexion étant configuré pour coupler électriquement le circuit au composant.
EP01944108A 2000-02-18 2001-02-16 Procede et appareil d'alimentation en courant d'un microprocesseur a gestion de chaleur integree et d'interference electromagnetique Withdrawn EP1256263A2 (fr)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US18347400P 2000-02-18 2000-02-18
US183474P 2000-02-18
US18676900P 2000-03-03 2000-03-03
US186769P 2000-03-03
US18777700P 2000-03-08 2000-03-08
US187777P 2000-03-08
US19605900P 2000-04-10 2000-04-10
US196059P 2000-04-10
US21981300P 2000-07-21 2000-07-21
US219813P 2000-07-21
US23297100P 2000-09-14 2000-09-14
US232971P 2000-09-14
PCT/US2001/005067 WO2001065344A2 (fr) 2000-02-18 2001-02-16 Procede et appareil d'alimentation en courant d'un microprocesseur a gestion de chaleur integree et d'interference electromagnetique

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EP (1) EP1256263A2 (fr)
JP (1) JP2003529921A (fr)
KR (1) KR100699094B1 (fr)
CN (1) CN1419803A (fr)
AU (1) AU2001266551A1 (fr)
CA (1) CA2400568A1 (fr)
MX (1) MXPA02008042A (fr)
WO (1) WO2001065344A2 (fr)

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KR100699094B1 (ko) 2007-03-21
WO2001065344A3 (fr) 2002-04-25
AU2001266551A1 (en) 2001-09-12
CA2400568A1 (fr) 2001-09-07
MXPA02008042A (es) 2004-09-06
WO2001065344A2 (fr) 2001-09-07
KR20020092961A (ko) 2002-12-12
JP2003529921A (ja) 2003-10-07
WO2001065344B1 (fr) 2002-06-27
CN1419803A (zh) 2003-05-21

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