EP1252734A1 - Procede et dispositif pour generer des mots de codes ovsf - Google Patents

Procede et dispositif pour generer des mots de codes ovsf

Info

Publication number
EP1252734A1
EP1252734A1 EP01900474A EP01900474A EP1252734A1 EP 1252734 A1 EP1252734 A1 EP 1252734A1 EP 01900474 A EP01900474 A EP 01900474A EP 01900474 A EP01900474 A EP 01900474A EP 1252734 A1 EP1252734 A1 EP 1252734A1
Authority
EP
European Patent Office
Prior art keywords
code
word
calculation
ovsf
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01900474A
Other languages
German (de)
English (en)
Inventor
Markus Doetsch
Peter Jung
Joerg Plechinger
Michael Schneider
Patrick Feyfant
Tideya Kella
Peter Schmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1252734A1 publication Critical patent/EP1252734A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/10—Code generation
    • H04J13/12—Generation of orthogonal codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/004—Orthogonal
    • H04J13/0044—OVSF [orthogonal variable spreading factor]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70703—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation using multiple or variable rates

Definitions

  • the invention relates to a device and a method for generating OVSF code words for CDMA methods, in particular in the field of mobile radio technology.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • FDMA Frequency Division Multiple Access
  • the CDMA process is clearly a process in which several interlocutors speak in one room, with two interlocutors each speaking in their own language. This is achieved by the use of orthogonal codes with var i ablem spreading factor, so-called OVSF codes.
  • the OVSF codes ensure the orthogonality between different transmissions in a physical transmission channel.
  • the OVSF codes make it possible to transmit data simultaneously over several data channels with different data transmission rates r by using different codes with different spreading factors.
  • the spreading factor is the number of code chips per data symbol.
  • the product of data rate and spreading factor is constant and corresponds to the chip rate of the system, for example 3.84 MHz for UMTS.
  • OVSF codes are periodic codes whose period is the same as
  • OVSF codes are most clearly shown in a code tree structure.
  • the code assignment rule of OVSF codes which ensures the orthogonality between the physical data transmission channels, is that if a branch of the code tree is used for coding, all preceding and subsequent branches in the tree structure are prohibited for further coding. If, for example, the code C 4 , ⁇ of the OVSF code tree shown in FIG. 1 is assigned for coding a channel, are the codes C 2 , ⁇ , C ⁇ , ⁇ , C 8 , ⁇ and C 8/2 blocked until the assigned code C, ⁇ is released again.
  • the invention provides a method for generating an OVSF code word from code tree index data of a specific OVSF code within a predetermined OVSF tree, with a first code tree index data (i) the spreading factor of the OVSF code and a second code tree index data (j ) indicates the position of the OVSF code in the case of OVSF codes with the same spreading factor within the OVSF code tree, the method comprising the following steps: calculating a calculation index as a function of the second code tree index date (j),
  • Buffering the calculated calculation index as a binary data word with several data bits calculating the word width of the binary data word, bit-wise interchanging the data bits of the data word to form a calculation basis, logically linking the calculation base with a number variable to form a link data word, and logically reducing the link data word to generate the OVSF code word.
  • the calculation index is preferably calculated by subtracting the second code tree index data (j) by 1.
  • the calculation base is logically AND-linked with the number variable bit by bit.
  • the linking data word is logically reduced by multi-level XOR linking of adjacent data bits.
  • the number variable is generated by a modulo counter, the modulo basis of which corresponds to the spreading factor of the OVSF code word to be generated.
  • the invention also provides a code word generator for OVSF codes with a buffer device for writing in a calculation index as a binary calculation index data word, a calculation device which bit-by-bit swaps the data bits of the calculation index data word to generate a calculation base, and a counter to generate a number variable , and with a logic circuit which has a plurality of AND gates for the bitwise logical AND combination of the generated number variable with the calculation basis for a combination data word and a plurality of XOR gates for the logical reduction of the formed combination data word to code word chips of the OVSF code word.
  • the code value generator preferably has an input buffer for reading in a first code tree index data Index date (i) and a second code tree index date (j), the first code tree index date (i) the spreading factor of the OVSF code and the second code tree index date (j) the position of the OVSF code at the OVSF -Codes with the same spreading factor within the OVSF code tree.
  • a subtraction device is preferably provided which reduces the second code tree index data (j) by 1 for calculating the calculation index.
  • the counter is a modulo counter, the modulo counting base of which is adjustable.
  • the modulo count base corresponds to the spreading factor of the OVSF code word to be generated.
  • a calculation unit is provided which is used to calculate the data word width of the calculation index data word.
  • the calculated data word width of the calculation index data word is stored in a buffer.
  • an output buffer is provided, in which the code word data bits generated by the logic circuit are buffered in order to form the OVSF code word.
  • the counter is preferably clocked at the code chip frequency.
  • FIG. 2 shows a block diagram of a CDMA transmission device in which the code word generator according to the invention is used for OVSF codes;
  • FIG. 3 shows a preferred embodiment of the code word generator according to the invention for OVSF codes
  • FIG. 4 shows a logic reduction circuit which forms part of the code word generator according to the invention for OVSF codes
  • FIG. 5 shows a flowchart to explain the method according to the invention for generating OVSF code words.
  • the code word generator 1 forms part of a CDMA transmission device.
  • a data source 2 of the CDMA transmission device generates data symbols which are fed to a spreading circuit 4 via a line 3.
  • the spreading circuit 4 is used for oversampling each data bit at an oversampling rate which corresponds to the spreading factor.
  • the spread data are fed via line 5 to a multiplication device 6, in which the spread data are multiplied by the generated OVSF code word present on line 7.
  • the oversampled data bits and the generated OVSF code word bits with the value range ⁇ 0.1 ⁇ are converted or mapped before multiplication to the antipodal value range ⁇ - 1, -! ⁇ .
  • the oversampled data bits and the generated OVSF code word bits are first linked to one another by a logic circuit and then mapped or converted to the antipodal value range ⁇ -l; + lj.
  • the logic circuit is preferably an EXOR logic circuit or an equivalence
  • the coded transmission signal formed in this way is output by the multiplication device 6 to a signal processing circuit 9 via a line 8.
  • the signal conditioning circuit 9 prepares the coded transmission signal for transmission over the transmission channel.
  • the processed transmission signal is emitted by the signal processing circuit 9 via the line 10 for further transmission.
  • a clock generator 11 supplies the spreading circuit 4 and the code word generator 1 via lines 12, 13 with a chip clock signal.
  • the code word generator 1 is present on a signal bus 14 for data exchange with a DSP (digital signal processor) or a microcontroller.
  • DSP digital signal processor
  • the code word generator 1 has two input registers 15, 16, via which data from the bus 14 are read.
  • the input register 16 serves to temporarily store a calculation index as a binary calculation index data word.
  • the data word width N of the calculation mdex data word buffered in the register 16 is stored in the input register 15.
  • the code word generator 1 also contains a calculation device 17 which, in order to generate a calculation basis, interchanges the data bits of the calculation index data word buffered in the register 16 bit by bit.
  • the calculation device 17 reads in the calculation index data word stored in the memory register 16 via data lines 18, the calculation device 17 via lines 19 receives a control signal which indicates the data word width of the calculation index data word.
  • the modulo number base N of a modulo counter 21 is set via control lines 20 in accordance with the data word width of the binary calculation index data word.
  • the modulo counter 21 is supplied with the clock signal via the clock line 13.
  • the modulo counter 21 is connected on the output side via data lines 22 to a logic circuit which consists of a plurality of AND gates 23 and XOR gates 25 connected downstream via lines 24.
  • the AND gates 23 link the output data bit lines 22 of the
  • Modulo counter 21 bit by bit with data bit output lines 26 of the calculation device 17.
  • the calculation basis generated in the calculation device 17 is applied to the output data lines 26.
  • the AND gates 23 link the number variable present on the output lines 22 bit by bit with the calculation base present on the lines 26 to form a logic data word which is logically reduced by the XOR gates 25 to a code word data bit of the OVSF code word.
  • the code word data bits generated bit by bit are stored via lines 26 in an output buffer memory 27, which outputs the generated OVSF code word to the multiplication device 6 via line 7.
  • the OVSF code to be formed is first determined within the code tree structure by means of a code assignment algorithm.
  • the OVSF code C 4 , 3 is to be generated by the code generator 1.
  • the selected OVSF code is determined by its two code tree index data I, j.
  • the first code tree index date i corresponds to the spreading factor of the OVSF code, for example 4, and the second code tree index date j indicates the position of the OVSF code within those OVSF codes that have the same spreading factor within the OVSF Own code tree.
  • a calculation index is determined from the second code tree index data j for further calculation.
  • the calculation index calculated in this way is written into the input register 16 of the code word generator 1 via the bus 14.
  • the data word width of the calculation index N is calculated by forming the dual logarithm of the first code tree index data i. If the OVSF code to be formed is C 4 , 3 and is therefore the first code tree index date i 4 corresponding to the spreading factor and the second code tree index date j corresponding to the position of the OVSF code is 3, the calculated calculation index is 2.
  • the binary Data width N of the calculated calculation index is also 2 and is written into register 15 as calculation index data word width N.
  • the calculation device 17 for generating a calculation phase requires the data word width of the binary calculation index stored in the register 16 in order to selectively interchange the data bits of the calculation index step by step.
  • the calculation basis generated by the calculation device 17 is logically AND-linked bit by bit using a plurality of AND gates to the counting variable formed by the modulo counter 21.
  • the basis of the modulo counter is adjustable and corresponds to the spreading factor.
  • a logic binary logic data word is formed by the AND gates 23 and is supplied to a logic reduction circuit 25 via signal lines 24.
  • the data bits of the link data word which are buffered, for example, in a register 28, are paired starting with the least significant bit LSB using XOR Gate 29, 30, 31, 32 logically XOR linked to form a codeword data bit of the OVSF codeword.
  • the code word data bit formed by the logical reduction reaches an output memory via line 26, in which the code word data bits formed are combined to form the OVSF code word.
  • the pairing of the adjacent data bits of the link data word formed by the logic AND circuit can also begin with the most significant bit MSB.
  • an OVSF code word by the code word generator is shown using an example. If the assignment algorithm specifies the formation of the OVSF code C 4 , 3 with the first code word index date 4 and the second code word index date 3, the calculation index and the word length N of the calculation index are first calculated.
  • the calculation device 17 calculates the calculation basis for 01 by bit-by-bit swapping of the data bits of the calculation index data word.
  • the modulo count basis of the modulo counter 21 is set to the word length N and the counter is initialized to the initial count values 00.
  • the first code word chip bit Codei of the OVSF code word is calculated therefrom by logical reduction using an XOR gate.
  • the counter is then incremented and a new logic data word Tmp is created by a logical AND operation of the Counter calculated with the calculation basis.
  • the next code word chip bit code 2 of the OVSF code word is calculated by logical reduction of the link data word and written into the output register 27.
  • the counter is then incremented again, the logical link data word Tmp is formed and the third code word data bit of the OVSF code word is generated by a logical XOR link.
  • the OVSF code word thus generated by the code word generator 1 according to the invention which is formed from the four generated code word chip bits (Code ⁇ code 4 ), corresponds to the code word prescribed by the code tree shown in FIG. 1.
  • Code word C 43 0101
  • the code word generator 1 according to the invention shown in FIG. 3 is very simple to implement in terms of circuitry, since it only consists of registers 15, 16, a modulo counter 21, several AND gates, several XOR gates and the calculation device 17.
  • the calculation device 17 can be implemented in a simple manner by means of shift registers and simple control logic.
  • FIG. 5 shows a flowchart of the method according to the invention for generating an OVSF code word.
  • a step S1 the code tree index data i, j of the desired OVSF codes are read.
  • the first code tree index date i corresponds to the spreading factor of the OVSF code and the second code word index date j corresponds to the position of the position of the OVSF code.
  • step S2 A calculation index is calculated from the second code tree index data j of the OVSF code by subtraction.
  • the data word width N of the calculation index is also calculated in step S2.
  • the calculation base B is also determined in step S2 by bit-by-bit swapping of the data bits of the calculation index data word.
  • B bit reverse (calculation index, N) The N significant bits of the calculation index are swapped or swapped.
  • step S2 After the calculation basis has been determined in step S2, the modulo basis of the modulo
  • Counter 21 set according to the spreading factor SF of the OVSF code word to be generated, and the modulo counter initialized to the initial count value 0.
  • step S4 the calculation base B formed by the calculation device 17 is linked logically and with the count value of the modulo counter 21.
  • the logic operation is done bit by bit by several logical AND gates.
  • the logical AND link forms a link data word, which is logically reduced in step S5 by a plurality of XOR gates 25 to a code word data bit of the OVSF code word.
  • step S6 the code word data bit formed is written into the output memory 27 and the modulo counter 21 is incremented.
  • step S8 it is checked whether the modulo counter has again reached the initial initialization value 0 and the loop has therefore been run through enough times according to the spreading factor SF of the OVSF code word.
  • step S9 the OVSF code word composed in the output memory 27 from the code word data bits formed is read out and output to the multiplication device 6 via the line 7 shown in FIG. 2.
  • the code word generator for OVSF codes according to the invention can be further simplified in terms of circuitry in that the computing operations carried out by the computing device 17 are carried out by the DSP processor connected to the bus 14.
  • the method according to the invention and the generator according to the invention for generating an OVSF code word can generate the associated OVSF code word from the code tree index data i, j in a quick and reliable manner without circuitry complexity.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention concerne un générateur de mots de codes de facteur d'étalement variable orthogonaux (OVSF), comprenant : un dispositif de mémoire temporaire (16) pour inscrire un indice de calcul en tant que mot de données binaire de l'indice de calcul ; un dispositif de calcul (17) qui, pour produire une base (B) de calcul, transpose par bits les bits de données significatifs du mot de données de l'indice de calcul ; un compteur (21) pour générer une variable (Z) de comptage ; et un circuit logique qui présente plusieurs portes ET pour la liaison ET par bits des variables (Z) de comptage générées avec la base (B) de calcul pour la création d'un mot de données de la liaison. Ce circuit logique présente également plusieurs portes XOR pour la réduction logique du mot de données de la liaison créé en bits de données du mot de code OVSF.
EP01900474A 2000-02-04 2001-01-22 Procede et dispositif pour generer des mots de codes ovsf Withdrawn EP1252734A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10004873A DE10004873A1 (de) 2000-02-04 2000-02-04 Verfahren und Vorrichtung zur Erzeugung von OVSF-Codeworten
DE10004873 2000-02-04
PCT/EP2001/000668 WO2001058070A1 (fr) 2000-02-04 2001-01-22 Procede et dispositif pour generer des mots de codes ovsf

Publications (1)

Publication Number Publication Date
EP1252734A1 true EP1252734A1 (fr) 2002-10-30

Family

ID=7629780

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01900474A Withdrawn EP1252734A1 (fr) 2000-02-04 2001-01-22 Procede et dispositif pour generer des mots de codes ovsf

Country Status (6)

Country Link
US (1) US6646579B2 (fr)
EP (1) EP1252734A1 (fr)
JP (1) JP2003522473A (fr)
CN (1) CN1288863C (fr)
DE (1) DE10004873A1 (fr)
WO (1) WO2001058070A1 (fr)

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US7248698B2 (en) 2001-04-06 2007-07-24 Interdigital Technology Corporation System for generating pseudorandom sequences
US6552996B2 (en) 2001-09-18 2003-04-22 Interdigital Communications Corporation OVSF code system and methods
GB2381169B (en) * 2001-10-15 2005-03-23 Ubinetics Ltd OVSF code generation
US7054294B2 (en) * 2001-11-29 2006-05-30 Telefonaktiebolaget Lm Ericsson (Publ) Orthogonal variable spreading code (OVSF) allocation telecommunications network
JP3896873B2 (ja) * 2002-03-07 2007-03-22 日本電気株式会社 可変通信システム
KR100511294B1 (ko) * 2002-10-26 2005-08-31 엘지전자 주식회사 비동기 코드분할 다중접속 통신 시스템의 심벌 매핑 및채널화 장치
BR0318691B1 (pt) * 2003-12-29 2014-02-04 Métodos para fabricar um pneu, e para controlar uma disposição de um material elastomérico não curado sobre um suporte rígido
US7706427B2 (en) * 2005-08-18 2010-04-27 Agere Systems Inc. Method and apparatus for compact OVSF despreading
US7894327B2 (en) * 2005-08-23 2011-02-22 Agere Systems Inc. Buffer-based generation of OVSF code sequences
US7729235B2 (en) * 2005-09-27 2010-06-01 Mediatek Inc. Method and apparatus for OVSF code generation
CN1988428B (zh) * 2005-12-23 2011-04-06 中兴通讯股份有限公司 宽带码分多址系统正交可变扩频因子码生成的方法和装置
US7970215B2 (en) * 2007-03-30 2011-06-28 Intel Corporation Automatic generation of compact code tables
KR101459044B1 (ko) 2008-01-10 2014-11-07 서강대학교산학협력단 무선 통신 시스템에서 이단 방식을 이용하여 효율적으로ｏｖｓｆ 코드를 생성하는 장치 및 방법
US8891351B2 (en) 2011-09-26 2014-11-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Orthogonal variable spreading factor code sequence generation
FR3036203B1 (fr) * 2015-05-13 2017-05-19 Inside Secure Procede de securisation d’une comparaison de donnees lors de l’execution d’un programme

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JP3317866B2 (ja) * 1996-12-20 2002-08-26 富士通株式会社 スペクトル拡散通信システム
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Also Published As

Publication number Publication date
DE10004873A1 (de) 2001-08-23
CN1288863C (zh) 2006-12-06
US6646579B2 (en) 2003-11-11
WO2001058070A1 (fr) 2001-08-09
JP2003522473A (ja) 2003-07-22
CN1397121A (zh) 2003-02-12
US20030105532A1 (en) 2003-06-05

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