EP1252734A1

EP1252734A1 - Method and device for generating ovsf code words

Info

Publication number: EP1252734A1
Application number: EP01900474A
Authority: EP
Inventors: Markus Doetsch; Peter Jung; Joerg Plechinger; Michael Schneider; Patrick Feyfant; Tideya Kella; Peter Schmidt
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2000-02-04
Filing date: 2001-01-22
Publication date: 2002-10-30
Also published as: CN1397121A; CN1288863C; DE10004873A1; JP2003522473A; US20030105532A1; WO2001058070A1; US6646579B2

Abstract

A code word generator for OVSF codes, comprising an intermediate memory device (16) which is used to input a calculation index as a binary calculation index data word, a calculation device (17) which permutes the significant data bits of the calculation index data word bit-by-bit so that a calculation basis (B) can be generated, a counter (21) for producing a counting variable (Z) and provided with a logic circuit comprising several AND gates for bit-by-bit linkage of the counting variables (Z) generated with the calculation basis (B) in order to form a linking data word and several XOR gates for logical reduction of the linking data word to form code word data bits of the OVSF code word.

Description

description

Method and device for generating OVSF code words

The invention relates to a device and a method for generating OVSF code words for CDMA methods, in particular in the field of mobile radio technology.

The CDMA process (CDMA: Code Division Multiple Access) is a process for channel access, particularly in cellular systems for the mobile radio sector. In this case, a narrowband signal is spread to a broadband signal by means of a code. This is done in that a digital data stream to be transmitted is not transmitted directly as a consequence of the bit values 0 and 1, but the digital useful data values 0 and 1 are represented by a sequence of n likewise binary symbols, so-called code chips. CDMA is more interference-proof than TDMA (Time Division Multiple Access) or FDMA (Frequency Division Multiple Access) because it is less prone to fading. CDMA also makes optimal use of the existing frequency spectrum by dispensing with guard bands and guard time. The CDMA process is clearly a process in which several interlocutors speak in one room, with two interlocutors each speaking in their own language. This is achieved by the use of orthogonal codes with var ⁱ ablem spreading factor, so-called OVSF codes. The OVSF codes ensure the orthogonality between different transmissions in a physical transmission channel. The OVSF codes make it possible to transmit data simultaneously over several data channels with different data transmission rates ^r by using different codes with different spreading factors. The spreading factor is the number of code chips per data symbol. The product of data rate and spreading factor is constant and corresponds to the chip rate of the system, for example 3.84 MHz for UMTS. OVSF codes are periodic codes whose period is the same as

Duration of the symbol is. OVSF codes have so far been generated using the following recursive relationship.

-1.1 = 0

OVSF codes are most clearly shown in a code tree structure.

1 shows an example of an OVSF code tree, the spreading factor of which ranges from 1 to 8. The code assignment rule of OVSF codes, which ensures the orthogonality between the physical data transmission channels, is that if a branch of the code tree is used for coding, all preceding and subsequent branches in the tree structure are prohibited for further coding. If, for example, the code C ₄ , ι of the OVSF code tree shown in FIG. 1 is assigned for coding a channel, are the codes C ₂ , ι, Cι, _ι , C ₈ , ι and C _8/2 blocked until the assigned code C, ι is released again.

The previously known methods for generating OVSF codes generate the OVSF code word using the recursive description above. However, this recursive calculation rule requires a high level of computational effort and many arithmetic operations. Such OVSF code word generators according to the prior art are therefore very complex in terms of circuitry and require a large amount of memory space.

It is therefore the object of the present invention to provide an apparatus and a method for generating OVSF code words in which the OVSF code word is generated with very little circuitry outlay.

This object is achieved according to the invention by a method with the features specified in claim 1 and by a device with the features specified in claim 6.

The invention provides a method for generating an OVSF code word from code tree index data of a specific OVSF code within a predetermined OVSF tree, with a first code tree index data (i) the spreading factor of the OVSF code and a second code tree index data (j ) indicates the position of the OVSF code in the case of OVSF codes with the same spreading factor within the OVSF code tree, the method comprising the following steps: calculating a calculation index as a function of the second code tree index date (j),

Buffering the calculated calculation index as a binary data word with several data bits, calculating the word width of the binary data word, bit-wise interchanging the data bits of the data word to form a calculation basis, logically linking the calculation base with a number variable to form a link data word, and logically reducing the link data word to generate the OVSF code word.

The calculation index is preferably calculated by subtracting the second code tree index data (j) by 1.

In a preferred development, the calculation base is logically AND-linked with the number variable bit by bit.

In a preferred development, the linking data word is logically reduced by multi-level XOR linking of adjacent data bits.

In a preferred embodiment of the method according to the invention, the number variable is generated by a modulo counter, the modulo basis of which corresponds to the spreading factor of the OVSF code word to be generated.

The invention also provides a code word generator for OVSF codes with a buffer device for writing in a calculation index as a binary calculation index data word, a calculation device which bit-by-bit swaps the data bits of the calculation index data word to generate a calculation base, and a counter to generate a number variable , and with a logic circuit which has a plurality of AND gates for the bitwise logical AND combination of the generated number variable with the calculation basis for a combination data word and a plurality of XOR gates for the logical reduction of the formed combination data word to code word chips of the OVSF code word.

The code value generator preferably has an input buffer for reading in a first code tree index data Index date (i) and a second code tree index date (j), the first code tree index date (i) the spreading factor of the OVSF code and the second code tree index date (j) the position of the OVSF code at the OVSF -Codes with the same spreading factor within the OVSF code tree.

A subtraction device is preferably provided which reduces the second code tree index data (j) by 1 for calculating the calculation index.

In a preferred development, the counter is a modulo counter, the modulo counting base of which is adjustable.

In a preferred development, the modulo count base corresponds to the spreading factor of the OVSF code word to be generated.

In a further preferred development, a calculation unit is provided which is used to calculate the data word width of the calculation index data word.

In a preferred development, the calculated data word width of the calculation index data word is stored in a buffer.

In a further preferred embodiment of the code word generator according to the invention, an output buffer is provided, in which the code word data bits generated by the logic circuit are buffered in order to form the OVSF code word.

The counter is preferably clocked at the code chip frequency.

In addition, preferred embodiments of the method according to the invention and of the code word generator according to the invention for OVSF codes according to the invention are described with reference to me described on the accompanying figures to explain features essential to the invention.

Show it:

1 shows the structure of an OVSF code tree;

FIG. 2 shows a block diagram of a CDMA transmission device in which the code word generator according to the invention is used for OVSF codes;

3 shows a preferred embodiment of the code word generator according to the invention for OVSF codes;

4 shows a logic reduction circuit which forms part of the code word generator according to the invention for OVSF codes;

5 shows a flowchart to explain the method according to the invention for generating OVSF code words.

As can be seen from FIG. 2, the code word generator 1 according to the invention for OVSF codes forms part of a CDMA transmission device. A data source 2 of the CDMA transmission device generates data symbols which are fed to a spreading circuit 4 via a line 3. The spreading circuit 4 is used for oversampling each data bit at an oversampling rate which corresponds to the spreading factor. In the embodiment shown in FIG. 2, the spread data are fed via line 5 to a multiplication device 6, in which the spread data are multiplied by the generated OVSF code word present on line 7. The oversampled data bits and the generated OVSF code word bits with the value range {0.1} are converted or mapped before multiplication to the antipodal value range {- 1, -!}. In an alternative embodiment, the oversampled data bits and the generated OVSF code word bits are first linked to one another by a logic circuit and then mapped or converted to the antipodal value range {-l; + lj. The logic circuit is preferably an EXOR logic circuit or an equivalence

Logic formwork

The coded transmission signal formed in this way is output by the multiplication device 6 to a signal processing circuit 9 via a line 8. The signal conditioning circuit 9 prepares the coded transmission signal for transmission over the transmission channel. The processed transmission signal is emitted by the signal processing circuit 9 via the line 10 for further transmission.

A clock generator 11 supplies the spreading circuit 4 and the code word generator 1 via lines 12, 13 with a chip clock signal. The code word generator 1 is present on a signal bus 14 for data exchange with a DSP (digital signal processor) or a microcontroller.

3 shows a preferred embodiment of the code word generator 1 according to the invention. The code word generator 1 has two input registers 15, 16, via which data from the bus 14 are read. The input register 16 serves to temporarily store a calculation index as a binary calculation index data word. The data word width N of the calculation mdex data word buffered in the register 16 is stored in the input register 15. The code word generator 1 also contains a calculation device 17 which, in order to generate a calculation basis, interchanges the data bits of the calculation index data word buffered in the register 16 bit by bit. For this purpose, the calculation device 17 reads in the calculation index data word stored in the memory register 16 via data lines 18, the calculation device 17 via lines 19 receives a control signal which indicates the data word width of the calculation index data word. The modulo number base N of a modulo counter 21 is set via control lines 20 in accordance with the data word width of the binary calculation index data word. The modulo counter 21 is supplied with the clock signal via the clock line 13. The modulo counter 21 is connected on the output side via data lines 22 to a logic circuit which consists of a plurality of AND gates 23 and XOR gates 25 connected downstream via lines 24. The AND gates 23 link the output data bit lines 22 of the

Modulo counter 21 bit by bit with data bit output lines 26 of the calculation device 17. The calculation basis generated in the calculation device 17 is applied to the output data lines 26. The AND gates 23 link the number variable present on the output lines 22 bit by bit with the calculation base present on the lines 26 to form a logic data word which is logically reduced by the XOR gates 25 to a code word data bit of the OVSF code word. The code word data bits generated bit by bit are stored via lines 26 in an output buffer memory 27, which outputs the generated OVSF code word to the multiplication device 6 via line 7.

The mode of operation of the code word generator for OVSF codes shown in FIG. 3 is explained below with reference to the code tree shown in FIG. 1.

The OVSF code to be formed is first determined within the code tree structure by means of a code assignment algorithm. For example, the OVSF code C ₄ , ₃ is to be generated by the code generator 1. The selected OVSF code is determined by its two code tree index data I, j. The first code tree index date i corresponds to the spreading factor of the OVSF code, for example 4, and the second code tree index date j indicates the position of the OVSF code within those OVSF codes that have the same spreading factor within the OVSF Own code tree. With a spread factor of 4 there are four different OVSF codes, for example the third OVSF code with a spreading factor of 4 C _{4 /} = 0101. A calculation index is determined from the second code tree index data j for further calculation. In the indexing chosen in FIG. 1, this is preferably done by subtracting 1 from the second code tree index data j. The calculation index calculated in this way is written into the input register 16 of the code word generator 1 via the bus 14. The data word width of the calculation index N is calculated by forming the dual logarithm of the first code tree index data i. If the OVSF code to be formed is C ₄ , ₃ and is therefore the first code tree index date i 4 corresponding to the spreading factor and the second code tree index date j corresponding to the position of the OVSF code is 3, the calculated calculation index is 2. The binary Data width N of the calculated calculation index is also 2 and is written into register 15 as calculation index data word width N. The calculation device 17 for generating a calculation phase requires the data word width of the binary calculation index stored in the register 16 in order to selectively interchange the data bits of the calculation index step by step.

Calculation index 0000000 10

Basis of calculation 0000000 01

Calculation index 00000 A _n - _! A _n - ₂ An A

Calculation basis 00000 ... A ₀ A _x ... A _n - ₂ A _n -ι The data bits of the calculation index data word, whose word length N is 2 in the example shown, are assigned bit by bit in decimal notation as follows:

The calculation basis generated by the calculation device 17 is logically AND-linked bit by bit using a plurality of AND gates to the counting variable formed by the modulo counter 21. The basis of the modulo counter is adjustable and corresponds to the spreading factor.

A logic binary logic data word is formed by the AND gates 23 and is supplied to a logic reduction circuit 25 via signal lines 24.

FIG. 4 shows an exemplary embodiment of a logic reduction circuit 25 of the code word generator 1 according to the invention for a data word width N = 5. The data bits of the link data word, which are buffered, for example, in a register 28, are paired starting with the least significant bit LSB using XOR Gate 29, 30, 31, 32 logically XOR linked to form a codeword data bit of the OVSF codeword. The code word data bit formed by the logical reduction reaches an output memory via line 26, in which the code word data bits formed are combined to form the OVSF code word. The pairing of the adjacent data bits of the link data word formed by the logic AND circuit can also begin with the most significant bit MSB.

For further clarification, the formation of an OVSF code word by the code word generator according to the invention is shown using an example. If the assignment algorithm specifies the formation of the OVSF code C ₄ , ₃ with the first code word index date 4 and the second code word index date 3, the calculation index and the word length N of the calculation index are first calculated.

C ₄₃ = 0101

ι = j = 3

Calculation index = j-1 = 2

Word length N = ldi = ld4 = 2

The calculation device 17 calculates the calculation basis for 01 by bit-by-bit swapping of the data bits of the calculation index data word. The modulo count basis of the modulo counter 21 is set to the word length N and the counter is initialized to the initial count values 00.

Calculation basis 01 counter: = 00

A logic data link Tmp = 00 is calculated by logically ANDing the counter value and the calculation basis. The first code word chip bit Codei of the OVSF code word is calculated therefrom by logical reduction using an XOR gate.

Tmp = 00 & 01 = 00 Codei = 0 XOR 0 = 0

The counter is then incremented and a new logic data word Tmp is created by a logical AND operation of the Counter calculated with the calculation basis. The next code word chip bit code _{2 of} the OVSF code word is calculated by logical reduction of the link data word and written into the output register 27.

Counter: = 01 Tmp = 01 & 01 = 01 Code ₂ = 0 XOR1 = 1

The counter is then incremented again, the logical link data word Tmp is formed and the third code word data bit of the OVSF code word is generated by a logical XOR link.

Counter: = 10

Tmp = 10 & 01 = 00

Code ₃ = 0 XOR 0 = 0

Finally, the counter is incremented again, the link data word Tmp is formed and the last code word chip bit code _{4 of} the OVSF code word is generated.

Counter: = 11

Tmp = 11 & 01 = 01

Code ₄ = 0 XOR 1 = 1

The OVSF code word thus generated by the code word generator 1 according to the invention, which is formed from the four generated code word chip bits (Codeχ code ₄ ), corresponds to the code word prescribed by the code tree shown in FIG. 1.

Code word C ₄₃ = 0101 The code word generator 1 according to the invention shown in FIG. 3 is very simple to implement in terms of circuitry, since it only consists of registers 15, 16, a modulo counter 21, several AND gates, several XOR gates and the calculation device 17. The calculation device 17 can be implemented in a simple manner by means of shift registers and simple control logic.

5 shows a flowchart of the method according to the invention for generating an OVSF code word. In a step S1, the code tree index data i, j of the desired OVSF codes are read. The first code tree index date i corresponds to the spreading factor of the OVSF code and the second code word index date j corresponds to the position of the position of the OVSF code.

After the reading, several calculations are carried out in step S2. A calculation index is calculated from the second code tree index data j of the OVSF code by subtraction.

Calculation index = j-1

The data word width N of the calculation index is also calculated in step S2.

N = ld (i)

where i = 1, 2, 4, 8, ... SFmax

The calculation base B is also determined in step S2 by bit-by-bit swapping of the data bits of the calculation index data word.

B = bit reverse (calculation index, N) The N significant bits of the calculation index are swapped or swapped.

After the calculation basis has been determined in step S2, the modulo basis of the modulo

Counter 21 set according to the spreading factor SF of the OVSF code word to be generated, and the modulo counter initialized to the initial count value 0.

In step S4, the calculation base B formed by the calculation device 17 is linked logically and with the count value of the modulo counter 21. The logic operation is done bit by bit by several logical AND gates. The logical AND link forms a link data word, which is logically reduced in step S5 by a plurality of XOR gates 25 to a code word data bit of the OVSF code word.

In step S6, the code word data bit formed is written into the output memory 27 and the modulo counter 21 is incremented.

In step S8 it is checked whether the modulo counter has again reached the initial initialization value 0 and the loop has therefore been run through enough times according to the spreading factor SF of the OVSF code word.

In step S9, the OVSF code word composed in the output memory 27 from the code word data bits formed is read out and output to the multiplication device 6 via the line 7 shown in FIG. 2.

In an alternative embodiment, the code word generator for OVSF codes according to the invention can be further simplified in terms of circuitry in that the computing operations carried out by the computing device 17 are carried out by the DSP processor connected to the bus 14. The method according to the invention and the generator according to the invention for generating an OVSF code word can generate the associated OVSF code word from the code tree index data i, j in a quick and reliable manner without circuitry complexity.

Such a simple implementation in terms of circuitry is particularly advantageous with high spreading factors, for example SF = 512.

As a result, the miniaturization of a mobile telecommunication terminal that uses the CDMA method can be significantly promoted.

LIST OF REFERENCE NUMBERS

1 OVSF code generator

2 data source

3 line

4 spreading circuit

5 line

6 multiplication device

7 lines

8 lines

9 Signal processing

10 output lines

11 clock generator

12, 13 clock lines

14 bus

15 registers

16 registers

17 calculation device

18 lines

19 lines 0 lines 1 modulo counter 2 lines 3 AND logic circuit 4 lines 5 XOR logic circuit 6 lines 7 output registers 8 buffers 9, 30, 31, 32 XOR gates

Claims

claims

1. Method for generating an OVSF code word from code tree index data (i, j) of a specific OVSF code within an OVSF code tree, with a first code tree index data (i) the spreading factor SF of the OVSF code and a second code tree Index date (j) indicates the position of the OVSF code in the OVSF codes with the same spreading factor SF within the OVSF code tree, the method comprising the following steps:

(a) calculating a calculation index depending on the second code tree index date (j);

(b) temporarily storing the calculated calculation index as a binary data word with a plurality of data bits; (c) calculating the data word width N of the calculation index data word;

(d) bitwise swapping the significant data bits of the calculation index data word to form a calculation basis B; (e) logically linking the calculation base B with a counting variable Z to form a link data word; (f) Logically reducing the link data word to generate the OVSF code word.

2. The method of claim 1, d a d u r c h g e k e n n z e i c h n e t that the calculation index is calculated by subtracting the second code word index data (j) by 1.

3. The method of claim 2, d a d u r c h g e k e n n z e i c h n e t that the calculation base B with the count variable Z is logically AND-linked bit by bit.

4. The method according to any one of the preceding claims, characterized in that the link data word is logically reduced by multilevel XOR linking of adjacent data bits.

5. The method according to any one of the preceding claims, that the counting variable Z is generated by a modulo counter (21), the modulo base of which corresponds to the spreading factor SF of the OVSF code word to be generated.

6. Codeword generator for OVSF codes with: a buffer device (16) for writing a calculation index as a binary calculation index data word; a calculation device (17) which, in order to generate a calculation base B, swaps the significant data bits of the calculation index data word bit by bit; a counter (21) for generating a count variable Z; and with a logic circuit which comprises a plurality of AND gates (23) for the bit-wise AND linkage of the generated count variable Z with the calculation base B to form a link data word and a plurality of XOR gates (25) for the logical reduction of the link data word formed to codeword chip bits of the OVSF Has code word.

7. code word generator according to claim 6, g e k e n n z e i c h n e t d u r c h an input buffer for reading a first code tree index date (i) and a second code tree index date

wherein the first code tree index date (i) indicates the spreading factor SF of the OVSF code and the second code tree index date (j) indicates the position of the OVSF code in the OVSF codes with the same spreading factor SF within the OVSF code tree.

8. Codeword generator according to one of the preceding claims 6 or 7, characterized by a subtraction device which reduces the second code tree index data (j) by 1 for calculating the calculation index.

9. Code word generator according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the counter (21) is a modulo counter, the modulo counting base is adjustable.

10. Code word generator according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the modulo count base corresponds to the spreading factor SF of the OVSF code word to be generated.

11. Code word generator according to one of the preceding claims, g e k e n n z e i c h n e t d u r c h a calculation unit for calculating the data word width N of the calculation index data word.

12. Code word generator according to one of the preceding claims, g e k e n n z e i c h n e t d u r c h an intermediate memory (15) in which the data word width N of the calculation index data word is stored.

13. Code word generator according to one of the preceding claims, g e k e n n z e i c h n e t d u r c h an output memory (27) in which the code word chips generated by the logic circuit (23, 25) are stored to form the OVSF code word.

14. Codeword generator according to one of the preceding claims 1-13, characterized in that the generated code word chips are multiplied in a multiplication device (6) by oversampled data bits which are emitted by a spreading circuit (4).

15. Codeword generator according to one of the preceding claims 1-13, so that the generated codeword chips are logically linked in a logic circuit with oversampled data bits, which are emitted by a spreading circuit (4).

16. Codeword generator according to claim 14 or 15, so that the oversampling of the data bits in the spreading circuit (4) and the generation of the codeword chips takes place synchronously in a chip clock which is generated by a clock generator (11).

17. Codeword generator according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the modulo counter (21) is clocked with the code chip frequency.