KR101459044B1 - Apparatus and Method for Efficiently Generating OVSF Code using 2-Stage Scheme in Wireless Communication System - Google Patents

Abstract

The present invention relates to an apparatus and method for generating an OVSF code quickly and efficiently by generating a short codeword from a single code index of a binary representation and spreading it to generate a long codeword, A zero counter for counting the number of zeros before a 1 appears in any one direction of the input code index of the code index, a code from the first position to the last position in the code index of the code index according to the number of zeros An index decomposer for generating a first code index and a second code index, a first code generator for generating a first code word from the first code index, a second code generator for generating a second code word from the second code index, And combining the first codeword and the second codeword to determine a length of the first codeword and a length of the second codeword This is multiplied by comprising code combiner to generate a final codeword having a length value.

WCDMA, wireless communication, two-stage spreading, Orthogonal Variable Spreading Factor (OVSF)

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for efficiently generating an OVSF code using a two-stage method in a wireless communication system,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OVSF (Orthogonal Variable Spreading Factor) code generator and a method thereof for transmitting and receiving a communication signal in a wireless communication system such as a Wideband Code Division Multiple Access (WCDMA) The present invention relates to an apparatus and method for generating OVSF codes quickly and efficiently by generating two short code words from an index and generating a long code word by spreading the codewords.

The OVSF code is a channel code adopted as a universal mobile telecommunication system (UMTS) standard by the 3rd Generation Project Partnership (3GPP), a mobile communication standardization organization. The OVSF channel code provides codewords with orthogonality maintained so that multiple connections can be made in the same slot in the same cell, thereby simultaneously providing various flexible services having various data rates required in third generation wireless communication such as WCDMA I will.

In order to provide an OVSF code, a method of using a variable length Walsh code or a method of using a tree structure has appeared. However, such a method is based on a Hadamard transformation using two indices including a spreading factor and a code number in order to represent a specific OVSF code. Therefore, a large amount of code is stored according to the size of the maximum spreading factor There is a problem that the memory required for the system increases exponentially and the allocation of the available codes becomes heavy.

Thus, an OVSF code generation algorithm has emerged that can display both the spreading factor and the code number of the codeword of each layer using only one code index. This allows not only the necessary codewords to be directly generated from the binary representation of a single code index but also the orthogonality of the two other codewords can be determined by comparison of a single code index so that the memory requirement is small and the processing speed Can be expected.

OVSF code generation methods based on such a single code index have been variously studied. However, OVSF code generation devices having more efficient and faster processing speed for allocating multiple connections smoothly to a large number of user terminals in mobile communication such as WCDMA A method is required.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an apparatus and a method for decoding a binary representation of a binary expression having a length of L + 1 from a single code index [a ₀ , a ₁ , .., a _L ] The present invention provides an apparatus and method for generating an OVSF code by quickly and efficiently generating a codeword of 2 ^L by applying a two-stage spreading method.

It is another object of the present invention to provide a method and apparatus for generating OVSF code having a length of (L + 1) by using two indexes generated from a single code index having a length of The present invention provides an apparatus and method for generating an OVSF code capable of generating two short codewords each having 2 ^N and 2 ^(LN) and combining them again to generate one long codeword having a length of 2 ^L.

In order to accomplish the above object, according to one aspect of the present invention, there is provided an apparatus for generating a code for wireless communication, the apparatus comprising: A zero counter for counting the number of zeros before; An index decomposer for generating a first code index and a second code index using a code from the first position to the last position in the direction according to the number of zeros; A first code generator for generating a first code word from the first code index; A second code generator for generating a second code word from the second code index; And a code combiner for combining the first codeword and the second codeword to generate a final codeword having a length multiplied by the length of the first codeword and the length of the second codeword.

The final codeword may be an OVSF code for multiple access of mobile communication terminals.

The index cracker comprises:

Equation

Where a first code index is indexed by INDEX1, a second code index by INDEX2, M is the number of zeros, N is a predetermined natural number, and the input code index is a binary set [a ₀ , a ₁ , a ₂ , .., a _L ]) of the first code index and the second code index.

Wherein the first code generator generates the first code word having a length of 2 ^(LN) , where L + 1 is the length of the input code index and N is a predetermined natural number, and the second code generator , And 2 ^(N) , respectively.

The first code generator and the second code generator may use only XOR logic.

Wherein the first code generator and the second code generator comprise: a first logic stage for performing an XOR operation on an initial value and an initial value in one direction of an input index; And a second logic stage for performing an XOR operation on the next value in the direction of the input index and 1 and an XOR operation on the output value of the first logic stage and 1, For each value in this direction, an XOR operation with 1 and an XOR operation with each of the output values of the previous stage of the logic stage may be performed to generate a code word having a length of 2 ^(K) .

The code combiner, 2 ^(LN) from the second code word of the first code word and a second ^(N) length (wherein, L + 1 is a length and N is a predetermined natural number of the input code index) length 2 ^{Lt; RTI ID = 0.0 > (L)} < / RTI >

The code combiner may perform an XNOR operation with all the values of the second codeword for each value of the sequential values of all values in either direction of the first codeword.

Wherein the code combiner comprises: a first shift register sequentially outputting the first codeword by one bit; A second shift register for receiving the second codeword and outputting the bit value sequentially as one bit while inputting the bit value to be finally output; A second shift register for holding a bit value output from the first shift register until the first shift register sequentially outputs each bit value of the second codeword and outputs all bit values; And logic for XORing an output bit value of the first shift register and an output bit value of the second shift register output from the repeater.

According to another aspect of the present invention, there is provided a code generation apparatus for wireless communication using a two-stage spreading method, wherein a code generation means generates a first code word and a second code word from two indices, The first codeword and the second codeword are combined to generate a final codeword having a length multiplied by the length of the first codeword multiplied by the length of the second codeword, , And can be determined from the code index according to the number of consecutive values from either end of the code index of the binary representation.

According to another aspect of the present invention, there is provided a code generation method for a wireless communication using a two-stage spreading method, comprising: generating a first code word and a second code word from two indices; And combining the first codeword and the second codeword to produce a final codeword having a length multiplied by the length of the first codeword multiplied by the length of the second codeword, The indices can be determined from the code index according to the number of consecutive values from either end of the code index of the binary representation.

According to the apparatus and method for generating an OVSF code according to the present invention, two short codewords having lengths of 2 ^N and 2 ^(LN) are generated using two indices generated from a single code index having a length of (L + 1) And by combining them again, a long codeword having a length of 2 ^L is generated so that a long OVSF code can be easily and quickly generated by applying a two-stage spreading scheme hierarchically.

Further, according to the apparatus and method for generating an OVSF code according to the present invention, it is possible to generate a very large spreading factor code only by adding a register and an XOR gate for generating a long OVSF code, thereby minimizing additional hardware complexity can do.

According to the apparatus and method for generating an OVSF code according to the present invention, when supporting a plurality of systems having different maximum lengths of OVSF codes, it is preferable to use some hardware according to the maximum code length required by each system By designing, power consumption can be reduced or hardware complexity can be reduced. In the case of a code generator other than the two-stage spreading method, a code generator as many as the number of systems to be supported must be provided, or even a system supporting a maximum length by using a short- Should be used. In the former case, the complexity increases. In the latter case, the power consumption is large. However, in the present invention, it is easy to design so that some hardware is not used according to the maximum code length, Can be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Like reference symbols in the drawings denote like elements.

1 is a block diagram of an OVSF code generation apparatus 100 according to an embodiment of the present invention. 1, an apparatus 100 for generating an OVSF code according to an exemplary embodiment of the present invention includes a zero counter 110, an index decomposer 120, a first code generator 130, A second code generator 140, and a code combiner 150.

The OVSF code generation apparatus 100 according to an exemplary embodiment of the present invention generates an OVSF channelization code used in a transceiver of a wireless communication system such as WCDMA using a two-stage spreading scheme. To this end, two code words having relatively shorter length than the last code word are first generated in the code generators 130 and 140, and two code words are generated in the code generators 130 and 140 The generated short codewords are combined and the final codeword of length multiplied by the two codewords is generated as OVSF codes for multiple access of mobile communication terminals. The two index input to the code generator (130, 140), respectively (INDEX1, INDEX2) include, for either one (for example, a single code index in the binary representation _{[a 0, a 1, a} 2, .., a L] , left MSB: Most Significant Bit) different value from the end of the (e. g., 1) consecutive values of the out until (e. g., 0) single code index type according to the number (M) of [a _0, a ₁ , a ₂ , .., a _L ]. The zero counter 110 calculates the number M of consecutive values (for example, 0) as described above and outputs the number M to the index decomposer 120. The index decomposer 120 calculates a single code index a ₀ , a ₁ , a ₂ , .., a _L ].

Even when a short code word is generated by the code generators 130 and 140 as described above, it can be generated by the two-stage spreading method using the structure of the OVSF code generating apparatus 100 as needed, It is possible to easily generate a very long code by applying various hierarchical structures of < RTI ID = 0.0 > As described above, in the present invention, it is possible to quickly and efficiently generate a long OVSF code while reducing hardware complexity and power consumption by applying a two-stage spreading scheme.

Hereinafter, the operation of the OVSF code generation apparatus 100 according to an embodiment of the present invention will be described with reference to the flowchart of FIG. 2, the block diagram of FIG. 3, and FIG.

First, the zero counter 110 receives a single code index [a ₀ , a ₁ , a ₂ , .., a _L ] of the binary representation (S 210). Accordingly, the zero counter 110 counts the number (M) of zeros from the left to the right of the single code index [a ₀ , a ₁ , a ₂ , .., a _L ] (S220). According to the single indexing technique, the length SF of a code generated by a single code index [a ₀ , a ₁ , a ₂ , .., a _L ] is represented by SF (Spreading Factor) = 2 ^LM , Can be. Here, the zero counter 110 is assumed to count the number of 0's (M) before a 1 is output from the left to the right of a single code index [a ₀ , a ₁ , a ₂ , .., a _L However, the present invention is not limited thereto. In some cases, the number of zeros (M) before the 1 is outputted in the right-to-left direction may be substituted. Alternatively, it may be replaced by counting the number of 1's before the zero is emitted in either direction.

The index decomposer 120 determines the final position in the same direction from the next 1 position of the first 1 in a single code index [a ₀ , a ₁ , a ₂ , .., a _L ] (LSB: Least Significant Bit) to generate a first code index INDEX1 and a second code index INDEX2. A first code index INDEX1 having a length LN and a second code index INDEX1 having a length N can be generated as shown in Equation 1 below. In Equation (1), N is a predetermined natural number smaller than L.

[Equation 1]

That is, M = in the case of LN (S230), the second index code (INDEX2) is a single code index _{[a 0, a 1, a} 2, .., a L] and then the position of the first one of the (a _{M + 1} in the same direction as from the position) and a _{M + N} to the configuration of N codes, the first code index (INDEX1) is the other of a single code index [a _0, a _1, a _2, .., a _{L] M} a _{+ N + 1} to a _L and M 0 (S240). In addition, M> from the case of LN, a second index code (INDEX2) is a single index code, and then the position of the first one of _{[a 0, a 1, a} 2, .., a L] (a M + 1 position) is composed of a a _L to M + NL and 0's in the same direction, a first index code (INDEX1) is of a LN of 0 (S250).

FIG. 3 is an example of logic 300 for implementing the first and second code generators 130, 140 of FIG. Referring to FIG. 3, the logic 300 for generating fixed codes in the first and second code generators 130 and 140 may include only XOR logic according to an embodiment of the present invention. That is, the logic 300 for generating fixed codes according to an exemplary embodiment of the present invention may include a first logic stage 310, a second logic stage 320, and a third logic stage 330 .

The first logic stage 310 receives the initial values a ₁ and a ₁ (for example, from left to right) in any one of the indexes [a ₁ , a ₂ , .., a _K ] (b ₁ ) and outputs the result b ₂ .

The second logic stage 320 performs an XOR operation on the following values a ₂ and 1 (b ₁ ) in the same direction as the direction of the input arbitrary index [a ₁ , a ₂ , .., a _K ] , And performs an XOR operation on the output value of the first logic stage 310 and a ₂ to output the respective results b ₃ and b ₄ .

The third logic stage 330 also performs an XOR operation on the next values a ₃ and 1 (b ₁ ) as in the second logic stage 320 and performs the XOR operation on the output values of the first logic stage 310 and the second logic stage 320, And also outputs a result b ₅ , b ₆ , b ₇ , b ₈ for each of the output values of b ₁ , a ₂ , and a ₃ . This process is similarly repeated by the next stage logic stage so that for each of the values in the same direction of the index [a ₁ , a ₂ , .., a _K ] of K length, b ₁₎ and the XOR operation and the output value of the logic stage of the previous stage and perform an XOR operation of each of the 2 ^(K) codewords b _1, b _2, having a length of b _3, .., b ₂ ^K Can be generated.

Using the logic 300 for generating the fixed code, the first code generator 130 generates a first code word having a length of 2 ^(LN) from the first code index INDEX1 made of (LN) bit code And the second code generator 140 may generate a second code word having a length of 2 ^(N) from the second code index INDEX2 made of (N) bit code (S260).

4 is a specific block diagram of the code combiner 150 of FIG. 4, a code combiner 150 combines two code words from a first code generator 130 and a second code generator 140 in a Kronecker scheme to generate a final code word 1 shift register 151, a second shift register 152, a repeater 153, and XNOR arithmetic logic 154.

The first shift register 151 receives the first codeword of length 2 ^(LN) generated by the first code generator 130 and sequentially outputs the first codeword to the right by one bit. For example, the first shift register 151 sequentially outputs one bit from the LSB (for example, the right end bit) to the MSB (for example, the left end bit) of the first code word in synchronization with the predetermined clock signal do.

The second shift register 152 receives the second codeword of length 2 ^(N) generated by the second code generator 140 and cyclically inputs the output bit value to the position of the bit value to be finally output Outputs one bit to the right sequentially. Here, the second shift register 152 sequentially outputs one bit from the LSB to the MSB of the second codeword at a period different from that of the first shift register 151 in synchronization with another clock signal. That is, after the second shift register 152 outputs 2 ^(N) bits by one bit, the first shift register 151 is controlled to output the next bit.

To this end, the repeater 153 outputs the first shift register 152 until the second shift register 152 sequentially outputs each bit value of the second codeword of 2 ^(N) length (bit) (154) while holding the bit value output from the bit line selector (151).

The XNOR operation logic 154 XORs the output bit value of the first shift register 151 and the output bit value of the second shift register 152 output from the repeater 153 and outputs the final OVSF code word ). The final OVSF codeword at this time has a length 2 ^(L) of the length 2 ^(LN) of the first codeword multiplied by the length 2 ^(N) of the second codeword.

That is, while all values of the second codeword output from the second shift register 152 are sequentially output to the XNOR operation logic 154 by one bit, the repeater 153 outputs the output of the first shift register 151 The sequential values of all the values of one codeword are output to the XNOR operation logic 154 so that the XNOR operation logic 154 performs 2 ^(LN) XNOR operations on the second codeword 2 ^(N) bits . In other words, for each bit of the first codeword of length 2 ^(LN) , 2 ^(N) bits of the second codeword are recursively XORed to produce a final OVSF codeword of length 2 ^(L) . The XNOR operation logic 154 inverts and outputs 2 ^(N) bits of the second code word when the value of each bit of the first code word is 0, on the basis of the characteristic of the XNOR (Exclusive NOR: exclusive inverse) . When each bit value of the first code word is 1, 2 ^(N) bits of the second code word are output as they are.

As described above, according to the present invention, the number of consecutive values M from the left end of a single code index [a ₀ , a ₁ , a ₂ , .., a _L ] ^(LN) and a second codeword of length 2 ^(N) from the two indices INDEX1 and INDEX2, respectively, if the two indices INDEX1 and INDEX2 are short, And generating a final OVSF code word having a length 2 ^(L) obtained by multiplying the first codeword and the second codeword by the length of the first codeword multiplied by the length of the second codeword The long channel OVSF code can be generated easily and quickly and efficiently. Such a two-stage spreading scheme can be used to generate two indices (INDEX1, INDEX2), such as by hierarchically applying a longer OVSF code efficiently.

In case of supporting multiple systems with different maximum lengths of OVSF codes, it is necessary to add registers and XOR gates according to the maximum code length required by each system, Power consumption can be reduced by designing that some hardware can be controlled so as to be easy to generate, even when a system requiring a code of a shorter length is supported.

The functions used in the methods and apparatuses disclosed herein may be embodied as computer readable codes on a computer readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, a hard disk, a removable storage device, And the like. In addition, the computer-readable recording medium may be distributed over a network-connected computer system so that computer-readable code can be stored and executed in a distributed manner.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

The code generation apparatus according to the present invention can be used in a transceiver of a CDMA communication system using an OVSF code.

1 is a block diagram of an OVSF code generation apparatus according to an embodiment of the present invention.

2 is a flowchart for explaining the operation of the OVSF code generating apparatus of FIG.

Figure 3 is an example of logic for the implementation of the first and second code generators of Figure 1;

4 is a specific block diagram of the code combiner of FIG.

Claims (11)

A zero counter for counting the number of zeros before a 1 appears in either direction of the input code index of the binary representation; An index decomposer for generating a first code index and a second code index using a code from the first position to the last position in the direction according to the number of zeros; A first code generator for generating a first code word from the first code index; A second code generator for generating a second code word from the second code index; And Generating a final codeword having a length of a value obtained by multiplying the first codeword and the second codeword by the length of the first codeword and the length of the second codeword, And a code generation unit for generating a code for wireless communication. The apparatus of claim 1, wherein the final codeword includes an OVSF code for multiple access of mobile communication terminals. 2. The apparatus according to claim 1, Equation

Where a first code index is indexed by INDEX1, a second code index by INDEX2, M is the number of zeros, N is a predetermined natural number, and the input code index is a binary set [a ₀ , a ₁ , a ₂ , .., a _L ]) Wherein the first code index and the second code index are determined based on the first code index and the second code index. The method according to claim 1, The first code generator generates the first code word having a length of 2 ^(LN) , where L + 1 is the length of the input code index and N is a predetermined natural number, And the second code generator generates the second code word having a length of 2 ^(N) . 2. The apparatus of claim 1, wherein the first code generator and the second code generator comprise: Code generating device for wireless communication, characterized by using only XOR logic. 2. The apparatus of claim 1, wherein the first code generator and the second code generator comprise: A first logic stage for performing an XOR operation on an initial value in one direction of an input index and 1; And A second logic stage for performing an XOR operation on the next value in the direction of the input index and 1 and an XOR operation on the output value of the first logic stage and 1, An XOR operation with 1 and XOR operation with each of the output values of the logic stage of the previous stage are performed to all the values in the direction of the input index of ^K length to obtain a code ^having a length of 2 ^(K) And generates a word by using the generated code. 2. The apparatus of claim 1, wherein the code combiner comprises: 2 ^(LN), the length of the first code word and a 2 ^(N) wherein the 2 2 ^(L) from the code word length of (wherein, L + 1 is a length and N is a predetermined natural number of the input code index) length To generate the final codeword of the code. 2. The apparatus of claim 1, wherein the code combiner comprises: And performs an XNOR operation with all values of the second codeword for each value sequentially of all values in either direction of the first codeword. 2. The apparatus of claim 1, wherein the code combiner comprises: A first shift register sequentially outputting the first codeword by one bit; A second shift register for receiving the second codeword and sequentially outputting the bit value to be output as a bit value to be finally output, one bit at a time; A second shift register for holding a bit value output from the first shift register until the first shift register sequentially outputs each bit value of the second codeword and outputs all bit values; And A logic that XNORs an output bit value of the first shift register and an output bit value of the second shift register output from the repeater And a code generator for generating a code for wireless communication. A code generation apparatus for wireless communication using a two-terminal spreading method, Generating a first code word and a second code word from the two indices, respectively, using code generation means, Combining the first codeword and the second codeword using code combining means to generate a final codeword having a length multiplied by the length of the first codeword and the length of the second codeword, Wherein the two indices are determined from the code index according to the number of consecutive values from one end of the code index of the binary representation. A code generation method for wireless communication using a two-terminal spreading method, Generating a first codeword and a second codeword from the two indices, respectively; And Generating a final codeword having a length of a length of the first codeword multiplied by a length of the second codeword by combining the first codeword and the second codeword, Wherein the two indices are determined from the code index according to the number of consecutive values from either end of the code index of the binary representation.

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