EP1252657A1 - Dispositif de transistor mos a effet de champ - Google Patents

Dispositif de transistor mos a effet de champ

Info

Publication number
EP1252657A1
EP1252657A1 EP01913571A EP01913571A EP1252657A1 EP 1252657 A1 EP1252657 A1 EP 1252657A1 EP 01913571 A EP01913571 A EP 01913571A EP 01913571 A EP01913571 A EP 01913571A EP 1252657 A1 EP1252657 A1 EP 1252657A1
Authority
EP
European Patent Office
Prior art keywords
effect transistor
mos field
field effect
semiconductor
transistor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01913571A
Other languages
German (de)
English (en)
Inventor
Jenoe Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1252657A1 publication Critical patent/EP1252657A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Definitions

  • the present invention relates to a MOS field-effect transistor arrangement in which the body region of a MOS transistor is connected to a semiconductor body and is at a fixed potential via the latter.
  • MOS field-effect transistor arrangements which, on the one hand, have a small area and have low capacitances, but on the other hand can carry large currents.
  • MOS field-effect transistor arrangements which largely meet these requirements are known to be implemented in SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084 to 1090). In such SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084 to 1090). In such SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084
  • MOS field effect transistor arrangements in SOI technology however, the body area should be at a fixed potential, so that no so-called “kink effects”, that is to say kinks and discontinuities in the current / voltage characteristic, occur.
  • kink effects that is to say kinks and discontinuities in the current / voltage characteristic.
  • MOS field effect transistor arrangements using SOI technology it has so far not been possible to keep the body region at a fixed potential, since this adjoins the insulator, so that it has hitherto not seemed possible without great effort to fix the body region with a fixed one Supply potential.
  • This object is achieved according to the invention in a MOS field-effect transistor arrangement of the type mentioned at the outset in that the source, drain and gate of the MOS transistor are embedded between a semiconductor column which projects away from the semiconductor body and forms the body region and a filling insulator which surrounds this semiconductor column and is arranged on the semiconductor body are.
  • the MOS field-effect transistor arrangement according to the invention has a “sidewall transistor structure”: a semiconductor column made of, for example, p-conducting silicon is located on the surface of a semiconductor body which is likewise made of p-conducting Tenden silicon can exist, and is embedded there on this surface in a filling insulator, such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride, etc.).
  • a filling insulator such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride, etc.).
  • silicon it is of course also possible to choose another suitable semiconductor material, such as an Aj- by compound semiconductor or SiC, etc. It is also possible to provide a semiconductor body and a semiconductor column of the n-type of conduction instead of the p-type of conduction.
  • trenches or trenches for the source and drain are driven into the boundary region between the semiconductor column and the filling insulator surrounding it and filled in a p-type semiconductor column with n + -conducting polycrystalline silicon, so that n.
  • n In the semiconductor column itself by diffusion -conducting zones for source and drain are created.
  • a gate trench Between the trenches for source and drain there is a gate trench, the walls and bottom of which are covered with an insulating layer made of silicon dioxide, for example, and which, like the source and drain trenches, is otherwise filled with n + -conducting polycrystalline silicon.
  • the gate trench can be provided in such a way that it touches or also cuts the trenches for source and / or drain.
  • the channel of the field effect transistor is formed by the side wall of the semiconductor column.
  • the depth of the gate, source and drain trenches determines the channel width, while the channel length is determined by the distance between source and drain on the side wall of the semiconductor column along the gate trench.
  • MOS field-effect transistor arrangement it is possible to achieve large ratios between the channel width W and the channel length L in a very small area, ie to achieve large values for W / L and to have small capacitances for the conductors.
  • the body region which is formed by the semiconductor column can easily be at a fixed potential via the semiconductor body which is connected to the body region.
  • the invention advantageously enables the production of n-channel and p-
  • the semiconductor column can thus have the n and p conductivity types in the same way.
  • the n- and p-channel field effect transistors can easily be supplied with a suitable body voltage via the associated p- or n-type semiconductor bodies.
  • the source, drain and gate electrodes made of polycrystalline silicon can be easily wired in a three-layer connection system in the MOS field-effect transistor arrangement according to the invention if suitable contact holes are provided between the individual levels of the polycrystalline silicon. These levels can easily be wired in a multi-layer metallization.
  • Materials with a low dielectric constant or a combination of such materials such as silicon dioxide, undoped polycrystalline silicon, etc., are suitable as the filling insulator.
  • a p- (or n-) conductive semiconductor column is first produced by etching on a surface thereof, the semiconductor body having the same conductivity type as the semiconductor column.
  • a filling insulator made of, for example, silicon dioxide is then attached to the column.
  • a trench for source is then introduced in the boundary region between the filling insulator and this starting semiconductor column by isotropic etching. This trench is filled with n + conductive polycrystalline silicon.
  • the trench for drain is etched and filled with n + conductive polycrystalline silicon. This is followed by the etching for the drain level.
  • the trench for gate is etched and the gate insulation layer is produced.
  • a trench is then placed in the trench Filled with n-type polycrystalline silicon for the gate level, which is then structured.
  • there is a multi-layer metallization for source, drain and gate is first produced by etching on a surface thereof, the semiconductor body having the same conductivity type as the semiconductor column.
  • a filling insulator made of, for example, silicon dioxide
  • MOS field effect transistors with an L / W ratio of approximately 0.1 ⁇ m / 5 ⁇ m, the area requirement corresponding to a conventional lateral field effect transistor with a corresponding L / W ratio of 0.1 / 1.
  • MOS field-effect transistors according to the present invention are particularly suitable for logic ICs and for low-voltage CMOS ICs with a high operating speed, as are used in particular in telecommunications or in portable computers.
  • the etching of the trenches for source, drain and gate does not necessarily have to be rectangular, but can also take other forms: it can be oval, T-shaped or trapezoidal, for example.
  • Fig. 2 shows a section AA through Fig. 1, which in turn a section BB of
  • Fig. 2 represents, and
  • FIG. 3 shows a schematic representation of the MOS field effect transistor arrangement according to the invention for CMOS ICs.
  • FIG. 1 shows a p-type silicon body 1, on which a p-type output silicon column 2 is formed by etching.
  • This starting silicon column 2 is surrounded by a filling insulator 3 made of, for example, silicon dioxide.
  • a filling insulator 3 made of, for example, silicon dioxide.
  • silicon an Aj by semiconductor or silicon carbide (SiC) etc. can also be used.
  • Trenches 4, 5 and 6 for drain, source and gate are introduced into the boundary region between the starting silicon column 2 and the filling insulator 3, so that only a remaining silicon column 7 remains from the starting silicon column 2 (see FIG. 2 ).
  • the trenches 4, 5 are filled with n -conducting polycrystalline silicon, from which n-dopant diffuses into the remaining silicon column 7, in order to form a drain zone in the area of the trench 4 and a source zone in the area of the trench 5.
  • the source zone and the drain zone can also be implanted.
  • the trench 6 is lined with an insulating layer 8 of, for example, silicon dioxide or silicon nitride and then filled with n-type polycrystalline silicon to form a gate electrode 9.
  • silicon dioxide silicon nitride can optionally also be used, so that an "MNS" structure is present.
  • a sidewall transistor structure composed of a source electrode 10 made of the n + -type polycrystalline silicon in the trench 5, a drain electrode 11 made of the n + -type polycrystalline silicon in the trench 4, the gate electrode 9 and the gate insulator 8, wherein the n-channel is guided along the side wall of the gate insulator 8 in the remaining silicon column 7.
  • the residual silicon column 7, like the starting silicon column 2, is directly connected to the silicon body 1, it is at the same potential as this silicon body 1.
  • the body region of the MOS field effect transistor arrangement has the same potential as the silicon body 1 , ie a fixed potential if the silicon body 1 is at this fixed potential, which is easily possible. In this way, so-called kink effects can be reliably avoided with the MOS field-effect transistor arrangement according to the invention, which offers comparable advantages to SOI technology.
  • the W / L ratio is determined by the depth of the trenches 4, 5, 6 with respect to the channel width W and by the distance between the trench 5 and the Trench 4 along the side wall of the trench 6 is determined with respect to the channel length L. It is thus possible to achieve large W / L ratios in a very small area, since the trenches have a small diameter and have a considerable depth reachable.
  • the production of the MOS field effect transistor arrangement according to the invention is relatively simple, since after structuring the silicon body 1 to form the silicon column 2 and after attaching the filling insulator 3, only conventional etching techniques for forming the trenches 4, 5 and 6 and filling them with polycrystalline silicon are used.
  • the metallization of the MOS field effect transistor arrangement according to the invention can also be carried out using the usual measures.
  • Materials with low dielectric constants such as in particular silicon dioxide or undoped polycrystalline silicon, are preferably used for the filling insulator.
  • FIG. 3 schematically shows a CMOS structure for the MOS field-defect transistor arrangement according to the invention.
  • a p-type region 12 in the n-type silicon body 1 which also forms a silicon column which is correspondingly p-doped.
  • This p-doped region can be set to zero potential, for example, while there is a positive potential + U CC of 3 V on the silicon body 1.
  • an n-channel MOS field-effect transistor 13 can be implemented in a CMOS arrangement in addition to a p-channel MOS field-effect transistor 14.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un dispositif de transistor MOS à effet de champ, la source, le drain et la grille de ce dispositif de transistor étant intégrés entre une colonne à semi-conducteurs (7) s'étendant en saillie par rapport à un corps à semi-conducteurs (1) et formant la zone de corps, et un isolateur de charge (3) disposé sur le corps à semi-conducteurs (1) et entourant cette colonne à semi-conducteurs (7).
EP01913571A 2000-02-04 2001-02-02 Dispositif de transistor mos a effet de champ Withdrawn EP1252657A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10004872A DE10004872C1 (de) 2000-02-04 2000-02-04 MOS-Feldeffekttransistoranordnung und Verfahren zur Herstellung
DE10004872 2000-02-04
PCT/DE2001/000441 WO2001057926A1 (fr) 2000-02-04 2001-02-02 Dispositif de transistor mos a effet de champ

Publications (1)

Publication Number Publication Date
EP1252657A1 true EP1252657A1 (fr) 2002-10-30

Family

ID=7629779

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01913571A Withdrawn EP1252657A1 (fr) 2000-02-04 2001-02-02 Dispositif de transistor mos a effet de champ

Country Status (5)

Country Link
US (1) US6777726B2 (fr)
EP (1) EP1252657A1 (fr)
JP (1) JP2003522418A (fr)
DE (1) DE10004872C1 (fr)
WO (1) WO2001057926A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7489488B2 (en) * 2005-10-19 2009-02-10 Littelfuse, Inc. Integrated circuit providing overvoltage protection for low voltage lines
US7515391B2 (en) * 2005-10-19 2009-04-07 Littlefuse, Inc. Linear low capacitance overvoltage protection circuit
US10636902B2 (en) * 2018-09-13 2020-04-28 Ptek Technology Co., Ltd. Multiple gated power MOSFET device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910564A (en) * 1987-07-01 1990-03-20 Mitsubishi Denki Kabushiki Kaisha Highly integrated field effect transistor and method for manufacturing the same
JPH01151268A (ja) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp 半導体装置の製造方法
US5281547A (en) * 1989-05-12 1994-01-25 Oki Electric Industry Co., Ltd. Method for manufacturing a field effect transistor
DE69213539T2 (de) * 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
US5512517A (en) * 1995-04-25 1996-04-30 International Business Machines Corporation Self-aligned gate sidewall spacer in a corrugated FET and method of making same
JPH09283766A (ja) * 1996-04-18 1997-10-31 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6635534B2 (en) * 2000-06-05 2003-10-21 Fairchild Semiconductor Corporation Method of manufacturing a trench MOSFET using selective growth epitaxy

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0157926A1 *

Also Published As

Publication number Publication date
US20030030102A1 (en) 2003-02-13
JP2003522418A (ja) 2003-07-22
US6777726B2 (en) 2004-08-17
WO2001057926A1 (fr) 2001-08-09
DE10004872C1 (de) 2001-06-28

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