EP1252657A1 - Mos field effect transistor arrangement - Google Patents

Mos field effect transistor arrangement

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Publication number
EP1252657A1
EP1252657A1 EP01913571A EP01913571A EP1252657A1 EP 1252657 A1 EP1252657 A1 EP 1252657A1 EP 01913571 A EP01913571 A EP 01913571A EP 01913571 A EP01913571 A EP 01913571A EP 1252657 A1 EP1252657 A1 EP 1252657A1
Authority
EP
European Patent Office
Prior art keywords
effect transistor
mos field
field effect
semiconductor
transistor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01913571A
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German (de)
French (fr)
Inventor
Jenoe Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1252657A1 publication Critical patent/EP1252657A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Definitions

  • the present invention relates to a MOS field-effect transistor arrangement in which the body region of a MOS transistor is connected to a semiconductor body and is at a fixed potential via the latter.
  • MOS field-effect transistor arrangements which, on the one hand, have a small area and have low capacitances, but on the other hand can carry large currents.
  • MOS field-effect transistor arrangements which largely meet these requirements are known to be implemented in SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084 to 1090). In such SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084 to 1090). In such SOI technology (cf., for example, Stephen C. kuhne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084
  • MOS field effect transistor arrangements in SOI technology however, the body area should be at a fixed potential, so that no so-called “kink effects”, that is to say kinks and discontinuities in the current / voltage characteristic, occur.
  • kink effects that is to say kinks and discontinuities in the current / voltage characteristic.
  • MOS field effect transistor arrangements using SOI technology it has so far not been possible to keep the body region at a fixed potential, since this adjoins the insulator, so that it has hitherto not seemed possible without great effort to fix the body region with a fixed one Supply potential.
  • This object is achieved according to the invention in a MOS field-effect transistor arrangement of the type mentioned at the outset in that the source, drain and gate of the MOS transistor are embedded between a semiconductor column which projects away from the semiconductor body and forms the body region and a filling insulator which surrounds this semiconductor column and is arranged on the semiconductor body are.
  • the MOS field-effect transistor arrangement according to the invention has a “sidewall transistor structure”: a semiconductor column made of, for example, p-conducting silicon is located on the surface of a semiconductor body which is likewise made of p-conducting Tenden silicon can exist, and is embedded there on this surface in a filling insulator, such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride, etc.).
  • a filling insulator such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride, etc.).
  • silicon it is of course also possible to choose another suitable semiconductor material, such as an Aj- by compound semiconductor or SiC, etc. It is also possible to provide a semiconductor body and a semiconductor column of the n-type of conduction instead of the p-type of conduction.
  • trenches or trenches for the source and drain are driven into the boundary region between the semiconductor column and the filling insulator surrounding it and filled in a p-type semiconductor column with n + -conducting polycrystalline silicon, so that n.
  • n In the semiconductor column itself by diffusion -conducting zones for source and drain are created.
  • a gate trench Between the trenches for source and drain there is a gate trench, the walls and bottom of which are covered with an insulating layer made of silicon dioxide, for example, and which, like the source and drain trenches, is otherwise filled with n + -conducting polycrystalline silicon.
  • the gate trench can be provided in such a way that it touches or also cuts the trenches for source and / or drain.
  • the channel of the field effect transistor is formed by the side wall of the semiconductor column.
  • the depth of the gate, source and drain trenches determines the channel width, while the channel length is determined by the distance between source and drain on the side wall of the semiconductor column along the gate trench.
  • MOS field-effect transistor arrangement it is possible to achieve large ratios between the channel width W and the channel length L in a very small area, ie to achieve large values for W / L and to have small capacitances for the conductors.
  • the body region which is formed by the semiconductor column can easily be at a fixed potential via the semiconductor body which is connected to the body region.
  • the invention advantageously enables the production of n-channel and p-
  • the semiconductor column can thus have the n and p conductivity types in the same way.
  • the n- and p-channel field effect transistors can easily be supplied with a suitable body voltage via the associated p- or n-type semiconductor bodies.
  • the source, drain and gate electrodes made of polycrystalline silicon can be easily wired in a three-layer connection system in the MOS field-effect transistor arrangement according to the invention if suitable contact holes are provided between the individual levels of the polycrystalline silicon. These levels can easily be wired in a multi-layer metallization.
  • Materials with a low dielectric constant or a combination of such materials such as silicon dioxide, undoped polycrystalline silicon, etc., are suitable as the filling insulator.
  • a p- (or n-) conductive semiconductor column is first produced by etching on a surface thereof, the semiconductor body having the same conductivity type as the semiconductor column.
  • a filling insulator made of, for example, silicon dioxide is then attached to the column.
  • a trench for source is then introduced in the boundary region between the filling insulator and this starting semiconductor column by isotropic etching. This trench is filled with n + conductive polycrystalline silicon.
  • the trench for drain is etched and filled with n + conductive polycrystalline silicon. This is followed by the etching for the drain level.
  • the trench for gate is etched and the gate insulation layer is produced.
  • a trench is then placed in the trench Filled with n-type polycrystalline silicon for the gate level, which is then structured.
  • there is a multi-layer metallization for source, drain and gate is first produced by etching on a surface thereof, the semiconductor body having the same conductivity type as the semiconductor column.
  • a filling insulator made of, for example, silicon dioxide
  • MOS field effect transistors with an L / W ratio of approximately 0.1 ⁇ m / 5 ⁇ m, the area requirement corresponding to a conventional lateral field effect transistor with a corresponding L / W ratio of 0.1 / 1.
  • MOS field-effect transistors according to the present invention are particularly suitable for logic ICs and for low-voltage CMOS ICs with a high operating speed, as are used in particular in telecommunications or in portable computers.
  • the etching of the trenches for source, drain and gate does not necessarily have to be rectangular, but can also take other forms: it can be oval, T-shaped or trapezoidal, for example.
  • Fig. 2 shows a section AA through Fig. 1, which in turn a section BB of
  • Fig. 2 represents, and
  • FIG. 3 shows a schematic representation of the MOS field effect transistor arrangement according to the invention for CMOS ICs.
  • FIG. 1 shows a p-type silicon body 1, on which a p-type output silicon column 2 is formed by etching.
  • This starting silicon column 2 is surrounded by a filling insulator 3 made of, for example, silicon dioxide.
  • a filling insulator 3 made of, for example, silicon dioxide.
  • silicon an Aj by semiconductor or silicon carbide (SiC) etc. can also be used.
  • Trenches 4, 5 and 6 for drain, source and gate are introduced into the boundary region between the starting silicon column 2 and the filling insulator 3, so that only a remaining silicon column 7 remains from the starting silicon column 2 (see FIG. 2 ).
  • the trenches 4, 5 are filled with n -conducting polycrystalline silicon, from which n-dopant diffuses into the remaining silicon column 7, in order to form a drain zone in the area of the trench 4 and a source zone in the area of the trench 5.
  • the source zone and the drain zone can also be implanted.
  • the trench 6 is lined with an insulating layer 8 of, for example, silicon dioxide or silicon nitride and then filled with n-type polycrystalline silicon to form a gate electrode 9.
  • silicon dioxide silicon nitride can optionally also be used, so that an "MNS" structure is present.
  • a sidewall transistor structure composed of a source electrode 10 made of the n + -type polycrystalline silicon in the trench 5, a drain electrode 11 made of the n + -type polycrystalline silicon in the trench 4, the gate electrode 9 and the gate insulator 8, wherein the n-channel is guided along the side wall of the gate insulator 8 in the remaining silicon column 7.
  • the residual silicon column 7, like the starting silicon column 2, is directly connected to the silicon body 1, it is at the same potential as this silicon body 1.
  • the body region of the MOS field effect transistor arrangement has the same potential as the silicon body 1 , ie a fixed potential if the silicon body 1 is at this fixed potential, which is easily possible. In this way, so-called kink effects can be reliably avoided with the MOS field-effect transistor arrangement according to the invention, which offers comparable advantages to SOI technology.
  • the W / L ratio is determined by the depth of the trenches 4, 5, 6 with respect to the channel width W and by the distance between the trench 5 and the Trench 4 along the side wall of the trench 6 is determined with respect to the channel length L. It is thus possible to achieve large W / L ratios in a very small area, since the trenches have a small diameter and have a considerable depth reachable.
  • the production of the MOS field effect transistor arrangement according to the invention is relatively simple, since after structuring the silicon body 1 to form the silicon column 2 and after attaching the filling insulator 3, only conventional etching techniques for forming the trenches 4, 5 and 6 and filling them with polycrystalline silicon are used.
  • the metallization of the MOS field effect transistor arrangement according to the invention can also be carried out using the usual measures.
  • Materials with low dielectric constants such as in particular silicon dioxide or undoped polycrystalline silicon, are preferably used for the filling insulator.
  • FIG. 3 schematically shows a CMOS structure for the MOS field-defect transistor arrangement according to the invention.
  • a p-type region 12 in the n-type silicon body 1 which also forms a silicon column which is correspondingly p-doped.
  • This p-doped region can be set to zero potential, for example, while there is a positive potential + U CC of 3 V on the silicon body 1.
  • an n-channel MOS field-effect transistor 13 can be implemented in a CMOS arrangement in addition to a p-channel MOS field-effect transistor 14.

Abstract

The invention relates to an MOS field effect transistor arrangement in which the source, drain and gate are embedded between a semiconductor pillar (7) which extends away from a semiconductor body (1) and forms the body region; and a filling insulator which surrounds said semiconductor pillar (7) and is situated on the semiconductor body (1).

Description

Beschreibung description
MOS-FeldeffekttransistoranordnungMOS field effect transistor arrangement
Die vorliegende Erfindung betrifft eine MOS-Feldeffekttransistoranordnung, bei der der Bodybereich eines MOS-Transistors mit einem Halbleiterkorper verbunden ist und über diesen auf festem Potential liegt.The present invention relates to a MOS field-effect transistor arrangement in which the body region of a MOS transistor is connected to a semiconductor body and is at a fixed potential via the latter.
Es ist schon seit langem das Bestreben, MOS-Feldeffekttransistoranordnungen zu realisieren, die einerseits kleinflächig gestaltet sind und geringe Kapazitäten aufweisen, jedoch andererseits große Ströme zu führen vermögen. MOS-Feldeffekttran- sistoranordnungen, die diese Forderungen weitgehend erfüllen, sind bekanntlich in der SOI-Technik ausgeführt (vgl. hierzu beispielsweise Stephen C. Kühne, u.a. "SOI MOSFET with Buried Body Strap by Wafer Bonding" in IEEE Transactions on Electron Devices, Band 45, Nr. 5, Mai 1998, Seiten 1084 bis 1090). Bei solchenFor a long time, efforts have been made to implement MOS field-effect transistor arrangements which, on the one hand, have a small area and have low capacitances, but on the other hand can carry large currents. MOS field-effect transistor arrangements which largely meet these requirements are known to be implemented in SOI technology (cf., for example, Stephen C. Kühne, inter alia “SOI MOSFET with Buried Body Strap by Wafer Bonding” in IEEE Transactions on Electron Devices, volume 45, No. 5, May 1998, pages 1084 to 1090). In such
MOS-Feldeffekttransistoranordnungen in SOI-Technik sollte aber der Bodybereich auf festem Potential liegen, damit keine sogenannten "Kink-Effekte", also Knicke und Unstetigkeiten in der Strom /Spannungskennlinie auftreten. Bei MOS-Feldef- fekttransistoranordnungen in SOI-Technik ist es bisher aber nicht gelungen, den Bodybereich auf festem Potential zu halten, da dieser an den Isolator angrenzt, so daß es bisher ohne großen Aufwand nicht möglich zu sein scheint, den Bodybereich mit einem festen Potential zu versorgen.MOS field effect transistor arrangements in SOI technology, however, the body area should be at a fixed potential, so that no so-called “kink effects”, that is to say kinks and discontinuities in the current / voltage characteristic, occur. In MOS field effect transistor arrangements using SOI technology, however, it has so far not been possible to keep the body region at a fixed potential, since this adjoins the insulator, so that it has hitherto not seemed possible without great effort to fix the body region with a fixed one Supply potential.
Es ist daher Aufgabe der vorliegenden Erfindung, eine MOS-Feldeffekttransi- storanordnung der eingangs genannten Art in einer zur SOI-Technik ähnlichen Technik zu realisieren, bei der aber der Bodybereich ohne weiteres auf festem Potential gehalten werden kann.It is therefore an object of the present invention to implement a MOS field-effect transistor arrangement of the type mentioned at the outset in a technology similar to SOI technology, but in which the body area can be easily kept at a fixed potential.
Diese Aufgabe wird bei einer MOS-Feldeffekttransistoranordnung der eingangs ge- nannten Art erfindungsgemäß dadurch gelöst, daß Source, Drain und Gate des MOS-Transistors zwischen eine vom Halbleiterkorper wegragende und den Bodybereich bildende Halbleitersäule und einen diese Halbleitersäule umgebenden und auf dem Halbleiterkorper angeordneten Füllisolator eingebettet sind.This object is achieved according to the invention in a MOS field-effect transistor arrangement of the type mentioned at the outset in that the source, drain and gate of the MOS transistor are embedded between a semiconductor column which projects away from the semiconductor body and forms the body region and a filling insulator which surrounds this semiconductor column and is arranged on the semiconductor body are.
Die erfindungsgemäße MOS-Feldeffekttransistoranordnung weist eine "Seitenwand- Transistor-Struktur" auf: eine Halbleitersäule aus beispielsweise p-leitendem Silizium befindet sich auf der Oberfläche eines Halbleiterkörpers, der ebenfalls aus p-lei- tendem Silizium bestehen kann, und ist dort auf dieser Oberfläche in einen Füllisolator, wie z.B. Siliziumdioxid oder einen anderen geeigneten Isolator (Siliziumnitrid oder Siliziumdioxid und Siliziumnitrid usw.) eingebettet.The MOS field-effect transistor arrangement according to the invention has a “sidewall transistor structure”: a semiconductor column made of, for example, p-conducting silicon is located on the surface of a semiconductor body which is likewise made of p-conducting Tenden silicon can exist, and is embedded there on this surface in a filling insulator, such as silicon dioxide or another suitable insulator (silicon nitride or silicon dioxide and silicon nitride, etc.).
Anstelle von Silizium kann selbstverständlich auch ein anderes geeignetes Halbleitermaterial, wie beispielsweise ein AjjjBy-Verbindungshalbleiter oder SiC usw. gewählt werden. Ebenso ist es möglich, einen Halbleiterkorper und eine Halbleitersäule des n-Leitungstyps anstelle des p-Leitungstyps vorzusehen.Instead of silicon, it is of course also possible to choose another suitable semiconductor material, such as an Aj- by compound semiconductor or SiC, etc. It is also possible to provide a semiconductor body and a semiconductor column of the n-type of conduction instead of the p-type of conduction.
Parallel zu dieser Halbleitersäule sind in den Grenzbereich zwischen der Halbleitersäule und dem diese umgebenden Füllisolator Trenche bzw. Gräben für Source und Drain eingetrieben und bei einer p-leitenden Halbleitersäule mit n+-leitendem polykristallinem Silizium gefüllt, so daß in der Halbleitersäule selbst durch Diffusion n-leitende Zonen für Source und Drain entstehen.In parallel to this semiconductor column, trenches or trenches for the source and drain are driven into the boundary region between the semiconductor column and the filling insulator surrounding it and filled in a p-type semiconductor column with n + -conducting polycrystalline silicon, so that n. In the semiconductor column itself by diffusion -conducting zones for source and drain are created.
Zwischen den Trenches für Source und Drain befindet sich ein Gate-Trench, dessen Wände und Boden mit einer Isolierschicht aus beispielsweise Siliziumdioxid bedeckt sind und der im übrigen wie die Source- und Drain-Trenche mit n+-leitendem polykristallinem Silizium gefüllt ist. Dabei kann der Gate-Trench so vorgesehen sein, daß er die Trenche für Source und/oder Drain berührt oder auch schneidet.Between the trenches for source and drain there is a gate trench, the walls and bottom of which are covered with an insulating layer made of silicon dioxide, for example, and which, like the source and drain trenches, is otherwise filled with n + -conducting polycrystalline silicon. The gate trench can be provided in such a way that it touches or also cuts the trenches for source and / or drain.
Bei einer solchen Anordnung wird der Kanal des Feldeffekttransistors durch die Seitenwand der Halbleitersäule gebildet. Die Tiefe der Gate- und Source- sowie Drain-Trenche bestimmt die Kanalweite, während die Kanallänge durch den Ab- stand zwischen Source und Drain auf der Seitenwand der Halbleitersäule längs des Gate-Trenches bestimmt ist.With such an arrangement, the channel of the field effect transistor is formed by the side wall of the semiconductor column. The depth of the gate, source and drain trenches determines the channel width, while the channel length is determined by the distance between source and drain on the side wall of the semiconductor column along the gate trench.
Mit der erfindungsgemäßen MOS-Feldeffekttransistoranordnung ist es möglich, auf sehr kleiner Fläche große Verhältnisse zwischen der Kanalweite W und der Ka- nallänge L zu realisieren, also große Werte für W/L zu erzielen und kleine Kapazitäten für die Leiter zu haben.With the MOS field-effect transistor arrangement according to the invention, it is possible to achieve large ratios between the channel width W and the channel length L in a very small area, ie to achieve large values for W / L and to have small capacitances for the conductors.
Von großer Bedeutung ist, daß bei der erfindungsgemäßen MOS-Feldeffekttransi- storanordnung der Bodybereich, der durch die Halbleitersäule gebildet wird, ohne weiteres über den Halbleiterkorper, der mit dem Bodybereich verbunden ist, auf festem Potential liegen kann. Die Erfindung ermöglicht in vorteilhafter Weise die Herstellung n-Kanal- und von p-It is of great importance that in the MOS field effect transistor arrangement according to the invention, the body region which is formed by the semiconductor column can easily be at a fixed potential via the semiconductor body which is connected to the body region. The invention advantageously enables the production of n-channel and p-
Kanal-Feldeffekttransistoren. Die Halbleitersäule kann also in gleicher Weise den n- und den p-Leitfähigkeitstyp haben. Die n- und p-Kanal-Feldeffekttransistoren können dabei ohne weiteres über die zugehörigen p- bzw. n-leitenden Halbleiterkorper mit einer geeigneten Bodyspannung versorgt werden.Channel field effect transistors. The semiconductor column can thus have the n and p conductivity types in the same way. The n- and p-channel field effect transistors can easily be supplied with a suitable body voltage via the associated p- or n-type semiconductor bodies.
In einer Weiterbildung der Erfindung ist es möglich, auf einem Halbleiterkorper Halbleitersäulen verschiedenen Leitungstyps für wenigstens einen n-Kanal-MOS- Feldeffekttransistor und einen p-Kanal-MOS-Feldeffekttransistor in einer CMOS- Anordnung zu realisieren. Hierzu braucht lediglich die den Halbleiterkorper bildende "Substratzone" für den n-Kanal-MOS-Feldeffekttransistor - wie eingangs erläutert - p-dotiert zu werden, während für die Substratzone eines p-Kanal-MOS-Feldef- fekttransistors eine n-Dotierung vorgesehen wird.In a development of the invention, it is possible to implement semiconductor columns of different conductivity types for at least one n-channel MOS field-effect transistor and one p-channel MOS field-effect transistor in a CMOS arrangement on a semiconductor body. For this purpose, only the "substrate zone" forming the semiconductor body for the n-channel MOS field-effect transistor needs to be p-doped, as explained at the beginning, while n-doping is provided for the substrate zone of a p-channel MOS field-effect transistor ,
Die Source-, Drain- und Gateelektroden aus polykristallinem Silizium können bei der erfindungsgemäßen MOS-Feldeffekttransistoranordnung ohne weiteres in einem dreilagigen Verbindungssystem verdrahtet werden, wenn zwischen den einzelnen Ebenen des polykristallinen Siliziums geeignete Kontaktlöcher vorgesehen werden. Diese Ebenen können in einer mehrlagigen Metallisierung ohne weiteres ver- drahtet werden.The source, drain and gate electrodes made of polycrystalline silicon can be easily wired in a three-layer connection system in the MOS field-effect transistor arrangement according to the invention if suitable contact holes are provided between the individual levels of the polycrystalline silicon. These levels can easily be wired in a multi-layer metallization.
Als Füllisolator sind Materialien mit niedriger Dielektrizitätskonstanten oder eine Kombination solcher Materialien geeignet, wie beispielsweise Siliziumdioxid, undotiertes polykristallines Silizium usw.Materials with a low dielectric constant or a combination of such materials, such as silicon dioxide, undoped polycrystalline silicon, etc., are suitable as the filling insulator.
Bei einem Verfahren zum Herstellen der erfindungsgemäßen MOS-Feldeffekttransi- storanordnung wird zunächst durch Ätzen auf einer Oberfläche von dieser eine p- (oder n-)leitende Halbleitersäule hergestellt, wobei der Halbleiterkorper den gleichen Leitungstyp wie die Halbleitersäule hat. Anschließend wird um die Säule ein Füllisolator aus beispielsweise Siliziumdioxid angebracht. Im Grenzbereich zwischen dem Füllisolator und dieser Ausgangs-Halbleitersäule wird sodann durch isotropes Ätzen ein Trench für Source eingebracht. Dieser Trench wird mit einer Füllung aus n+-leitendem polykristallinem Silizium versehen. Nach Strukturierung und Zwischenisolierung wird der Trench für Drain geätzt und mit einer Füllung aus n+-leitendem polykristallinem Silizium versehen. Es schließt sich sodann das Ätzen für die Drainebene an. Nach einer weiteren Zwischenisolierung wird der Trench für Gate geätzt und die Gate-Isolierschicht hergestellt. In den Trench wird sodann eine Füllung aus n -leitendem polykristallinem Silizium für die Gate-Ebene eingebracht, welche anschließend strukturiert wird. Schließlich folgt noch eine mehrlagige Metallisierung für Source, Drain und Gate.In a method for producing the MOS field-effect transistor arrangement according to the invention, a p- (or n-) conductive semiconductor column is first produced by etching on a surface thereof, the semiconductor body having the same conductivity type as the semiconductor column. A filling insulator made of, for example, silicon dioxide is then attached to the column. A trench for source is then introduced in the boundary region between the filling insulator and this starting semiconductor column by isotropic etching. This trench is filled with n + conductive polycrystalline silicon. After structuring and intermediate insulation, the trench for drain is etched and filled with n + conductive polycrystalline silicon. This is followed by the etching for the drain level. After further intermediate insulation, the trench for gate is etched and the gate insulation layer is produced. A trench is then placed in the trench Filled with n-type polycrystalline silicon for the gate level, which is then structured. Finally, there is a multi-layer metallization for source, drain and gate.
Mit der Erfindung ist es möglich, MOS-Feldeffekttransistoren mit einem L/W- Verhältnis von etwa 0, 1 μm/5 μm herzustellen, wobei der Flächenbedarf einem herkömmlichen lateralen Feldeffekttransistor mit einem entsprechenden Verhältnis L/ W von 0, 1/ 1 entspricht.With the invention it is possible to manufacture MOS field effect transistors with an L / W ratio of approximately 0.1 μm / 5 μm, the area requirement corresponding to a conventional lateral field effect transistor with a corresponding L / W ratio of 0.1 / 1.
MOS-Feldeffekttransistoren nach der vorliegenden Erfindung eignen sich besonders für Logik-IC's und für Kleinspannungs-CMOS-IC's mit hoher Arbeitsgeschwindigkeit, wie sie insbesondere in der Telekommunikation oder bei tragbaren Computern eingesetzt werden.MOS field-effect transistors according to the present invention are particularly suitable for logic ICs and for low-voltage CMOS ICs with a high operating speed, as are used in particular in telecommunications or in portable computers.
Es sei noch angemerkt, daß der Querschnitt der Ausgangs-Halbleitersäule vor demIt should also be noted that the cross section of the output semiconductor column before the
Ätzen der Trenche für Source, Drain und Gate nicht unbedingt rechteckig zu sein braucht, sondern auch andere Formen annehmen kann: er kann nämlich beispielsweise oval, T-förmig oder auch trapezförmig sein.The etching of the trenches for source, drain and gate does not necessarily have to be rectangular, but can also take other forms: it can be oval, T-shaped or trapezoidal, for example.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 eine Schnittdarstellung der erfindungsgemäßen MOS-Feldeffekttransi- storanordnung,1 is a sectional view of the MOS field effect transistor arrangement according to the invention,
Fig. 2 einen Schnitt AA durch die Fig. 1, welche ihrerseits einen Schnitt BB vonFig. 2 shows a section AA through Fig. 1, which in turn a section BB of
Fig. 2 darstellt, undFig. 2 represents, and
Fig. 3 eine schematische Darstellung der erfindungsgemäßen MOS-Feldeffekttran- sistoranordnung für CMOS-IC's.3 shows a schematic representation of the MOS field effect transistor arrangement according to the invention for CMOS ICs.
Fig. 1 zeigt einen p-leitenden Siliziumkörper 1 , auf dem durch Ätzen eine p-leitende Ausgangs-Siliziumsäule 2 gebildet ist. Diese Ausgangs-Siliziumsäule 2 wird mit einem Füllisolator 3 aus beispielsweise Siliziumdioxid umgeben. Anstelle von Silizi- um kann auch ein AjjjBy-Halbleiter oder Siliziumcarbid (SiC) usw. verwendet werden. In den Grenzbereich zwischen der Ausgangs-Siliziumsäule 2 und den Füllisolator 3 sind Trenche 4, 5 und 6 für Drain, Source bzw. Gate eingebracht, so daß von der Ausgangs-Siliziumsäule 2 lediglich eine Rest-Siliziumsäule 7 zurückbleibt (vgl. Fig. 2).1 shows a p-type silicon body 1, on which a p-type output silicon column 2 is formed by etching. This starting silicon column 2 is surrounded by a filling insulator 3 made of, for example, silicon dioxide. Instead of silicon, an Aj by semiconductor or silicon carbide (SiC) etc. can also be used. Trenches 4, 5 and 6 for drain, source and gate are introduced into the boundary region between the starting silicon column 2 and the filling insulator 3, so that only a remaining silicon column 7 remains from the starting silicon column 2 (see FIG. 2 ).
Die Trenche 4, 5 werden mit n -leitendem polykristallinem Silizium gefüllt, aus welchem n-Dotierstoff in die Rest-Siliziumsäule 7 diffundiert, um dort im Bereich des Trenches 4 eine Drainzone und im Bereich des Trenches 5 eine Sourcezone zu bilden. Die Sourcezone und die Drainzone können aber auch implantiert werden.The trenches 4, 5 are filled with n -conducting polycrystalline silicon, from which n-dopant diffuses into the remaining silicon column 7, in order to form a drain zone in the area of the trench 4 and a source zone in the area of the trench 5. The source zone and the drain zone can also be implanted.
Der Trench 6 wird mit einer Isolierschicht 8 aus beispielsweise Siliziumdioxid oder Siliziumnitrid ausgekleidet und sodann mit n -leitendem polykristallinem Silizium zur Bildung einer Gateelektrode 9 gefüllt. Anstelle von Siliziumdioxid kann gegebenenfalls auch Siliziumnitrid verwendet werden, so daß eine "MNS"-Struktur vor- liegt.The trench 6 is lined with an insulating layer 8 of, for example, silicon dioxide or silicon nitride and then filled with n-type polycrystalline silicon to form a gate electrode 9. Instead of silicon dioxide, silicon nitride can optionally also be used, so that an "MNS" structure is present.
Es liegt damit eine Seitenwand-Transistor-Struktur aus einer Sourceelektrode 10 aus dem n+-leitendem polykristallinem Silizium im Trench 5, einer Drainelektrode 11 aus dem n+-leitendem polykristallinem Silizium im Trench 4, der Gateelektrode 9 und dem Gateisolator 8 vor, wobei der n-Kanal längs der Seitenwand des Gateisolators 8 in der Rest-Siliziumsäule 7 geführt ist.There is therefore a sidewall transistor structure composed of a source electrode 10 made of the n + -type polycrystalline silicon in the trench 5, a drain electrode 11 made of the n + -type polycrystalline silicon in the trench 4, the gate electrode 9 and the gate insulator 8, wherein the n-channel is guided along the side wall of the gate insulator 8 in the remaining silicon column 7.
Da die Rest-Siliziumsäule 7 wie die Ausgangs-Siliziumsäule 2 direkt mit dem Siliziumkörper 1 zusammenhängt, befindet sie sich auf demselben Potential wie dieser Siliziumkörper 1. Mit anderen Worten, der Bodybereich der MOS-Feldeffekttransi- storanordnung hat das gleiche Potential wie der Siliziumkörper 1, also ein festes Potential, wenn sich der Siliziumkörper 1 auf diesem festen Potential befindet, was ohne weiteres möglich ist. Auf diese Weise können mit der erfindungsgemäßen MOS-Feldeffekttransistoranordnung, welche vergleichbare Vorteile wie die SOI- Technik bietet, sogenannte Kink-Effekte zuverlässig vermieden werden.Since the residual silicon column 7, like the starting silicon column 2, is directly connected to the silicon body 1, it is at the same potential as this silicon body 1. In other words, the body region of the MOS field effect transistor arrangement has the same potential as the silicon body 1 , ie a fixed potential if the silicon body 1 is at this fixed potential, which is easily possible. In this way, so-called kink effects can be reliably avoided with the MOS field-effect transistor arrangement according to the invention, which offers comparable advantages to SOI technology.
Wie aus den Fig. 1 und 2 ersichtlich ist, wird bei der erfindungsgemäßen MOS-Fel- deffekttransistoranordnung das W/L- Verhältnis durch die Tiefe der Trenche 4, 5, 6 bezüglich der Kanalweite W und durch den Abstand zwischen dem Trench 5 und dem Trench 4 längs der Seitenwand des Trenches 6 bezüglich der Kanallänge L bestimmt. Es ist damit möglich, auf sehr kleiner Fläche große W/L- Verhältnisse zu realisieren, da bei kleinem Durchmesser der Trenche diese eine beträchtliche Tiefe erreichen können.As can be seen from FIGS. 1 and 2, in the MOS field defect transistor arrangement according to the invention, the W / L ratio is determined by the depth of the trenches 4, 5, 6 with respect to the channel width W and by the distance between the trench 5 and the Trench 4 along the side wall of the trench 6 is determined with respect to the channel length L. It is thus possible to achieve large W / L ratios in a very small area, since the trenches have a small diameter and have a considerable depth reachable.
Die Herstellung der erfindungsgemäßen MOS-Feldeffekttransistoranordnung ist relativ einfach, da nach Strukturierung des Siliziumkörpers 1 zur Bildung der Siliziumsäule 2 und nach Anbringung des Füllisolators 3 lediglich übliche Ätztechniken zur Bildung der Trenche 4, 5 und 6 und deren Füllung mit polykristallinem Silizium zur Anwendung gelangen. Auch die Metallisierung der erfindungsgemäßen MOS-Feldeffekttransistoranordnung kann mit den üblichen Maßnahmen vorgenommen werden.The production of the MOS field effect transistor arrangement according to the invention is relatively simple, since after structuring the silicon body 1 to form the silicon column 2 and after attaching the filling insulator 3, only conventional etching techniques for forming the trenches 4, 5 and 6 and filling them with polycrystalline silicon are used. The metallization of the MOS field effect transistor arrangement according to the invention can also be carried out using the usual measures.
In bevorzugter Weise werden für den Füllisolator Materialien mit niedriger Dielektrizitätskonstanten verwendet, wie insbesondere Siliziumdioxid oder undotiertes polykristallines Silizium.Materials with low dielectric constants, such as in particular silicon dioxide or undoped polycrystalline silicon, are preferably used for the filling insulator.
Fig. 3 zeigt schematisch eine CMOS-Struktur für die erfindungsgemäße MOS-Fel- deffekttransistoranordnung. Hier befindet sich in dem n-leitenden Siliziumkörper 1 noch zusätzlich ein p-leitendes Gebiet 12, das auch eine Siliziumsäule bildet, die entsprechend p-dotiert ist. Dieses p-dotierte Gebiet kann beispielsweise auf Nullpotential gelegt werden, während am Siliziumkörper 1 ein positives Potential +UCC von 3 V liegt.3 schematically shows a CMOS structure for the MOS field-defect transistor arrangement according to the invention. Here, there is additionally a p-type region 12 in the n-type silicon body 1, which also forms a silicon column which is correspondingly p-doped. This p-doped region can be set to zero potential, for example, while there is a positive potential + U CC of 3 V on the silicon body 1.
Auf diese Weise kann ein n-Kanal-MOS-Feldeffekttransistor 13 neben einem p-Ka- nal-MOS-Feldeffekttransistor 14 in einer CMOS-Anordnung realisiert werden. In this way, an n-channel MOS field-effect transistor 13 can be implemented in a CMOS arrangement in addition to a p-channel MOS field-effect transistor 14.

Claims

Patentansprüche claims
1. MOS-Feldeffekttransistoranordnung, bei der der Bodybereich eines MOS- Transistors mit einem Halbleiterkorper (1) verbunden ist und über diesen auf festem Potential liegt, dadurch gekennzeichnet, daß1. MOS field-effect transistor arrangement in which the body region of a MOS transistor is connected to a semiconductor body (1) and is at a fixed potential via this, characterized in that
Source, Drain und Gate des MOS-Transistors zwischen eine vom Halbleiterkorper (1) wegragende und den Bodybereich bildende Halbleitersäule (2) und einen diese Halbleitersäule (2) umgebenden und auf dem Halbleiterkorper angeordneten Füllisolator (3) eingebettet sind.The source, drain and gate of the MOS transistor are embedded between a semiconductor column (2) protruding from the semiconductor body (1) and forming the body region and a filling insulator (3) surrounding this semiconductor column (2) and arranged on the semiconductor body.
1010
2. MOS-Feldeffekttransistoranordnung nach Anspruch 1, dadurch gekennzeichnet, daß2. MOS field effect transistor arrangement according to claim 1, characterized in that
Source und Drain durch in den Grenzbereich zwischen der Halbleitersäule (2) und dem Füllisolator (3) eingebrachte Trenche (4, 5), durch aus den Trenchen (4, 5) diffundierte oder implantierte Sourcezone und Drainzone und die Tren¬Source and drain through trenches (4, 5) introduced into the boundary region between the semiconductor column (2) and the filling insulator (3), through source zone and drain zone diffused or implanted from the trenches (4, 5) and the trenches
15 che füllendes leitendes Material (10, 11) gebildet sind.15 che filling conductive material (10, 11) are formed.
3. MOS-Feldeffekttransistoranordnung nach Anspruch 2, dadurch gekennzeichnet, daß3. MOS field effect transistor arrangement according to claim 2, characterized in that
Gate durch einen zwischen den Trenchen (4, 5) für Source und Drain vorgese- 20 henen zusätzlichen und über einen Gateisolator (8) isolierten sowie mit leitendem Material (9) gefüllten Trench (6) gebildet ist.Gate is formed by an additional trench (6) provided between the trenches (4, 5) for source and drain and insulated via a gate insulator (8) and filled with conductive material (9).
4. MOS-Transistoranordnung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß4. MOS transistor arrangement according to one of claims 1 to 3, characterized in that
„j. auf den Halbleiterkorper (1) Säulen verschiedenen Leitungstyps für wenigstens einen n-Kanal-MOS-Feldeffekttransistor (13) und einen p-Kanal-MOS- Feldeffekttransistor (14) in einer CMOS-Anordnung vorgesehen sind." J. on the semiconductor body (1) columns of different conductivity types for at least one n-channel MOS field effect transistor (13) and a p-channel MOS field effect transistor (14) are provided in a CMOS arrangement.
5. MOS-Feldeffekttransistoranordnung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß5. MOS field effect transistor arrangement according to one of claims 1 to 4, characterized in that
30 rieι- Füllisolator (3) aus einem Material mit niedriger Dielektrizitätskonstanten besteht.30 ri eι - filling insulator (3) consists of a material with low dielectric constant.
6. MOS-Feldeffekttransistoranordnung nach Anspruch 5, dadurch gekennzeichnet, daß6. MOS field effect transistor arrangement according to claim 5, characterized in that
35 der Füllisolator (3) aus Siliziumdioxid und/oder nichtdotiertem polykristallinem Silizium und/oder einem Stoff mit niedriger Dielektrizitätskonstanten besteht. 35 the filling insulator (3) consists of silicon dioxide and / or undoped polycrystalline silicon and / or a substance with low dielectric constants.
7. MOS-Feldeffekttransistoranordnung nach einem der Ansprüche 3 bis 6, dadurch gekennzeichnet, daß die Kanalweite (W) durch die Tiefe der Trenches (5, 4, 6) für Source, Drain und Gate bestimmt ist.7. MOS field effect transistor arrangement according to one of claims 3 to 6, characterized in that the channel width (W) is determined by the depth of the trenches (5, 4, 6) for source, drain and gate.
8. MOS-Feldeffekttransistoranordnung nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, daß der Halbleiterkorper (1) und die Halbleitersäule (2) den gleichen Leitungstyp haben und beide n- oder p-dotiert sind.8. MOS field effect transistor arrangement according to one of claims 1 to 7, characterized in that the semiconductor body (1) and the semiconductor column (2) have the same conductivity type and both are n- or p-doped.
1010
9. MOS-Feldeffekttransistoranordnung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, daß der Halbleiterkorper (1) und die Halbleitersäule (2) aus Silizium, einem AjuBy-Halbleiter oder SiC bestehen.9. MOS field effect transistor arrangement according to one of claims 1 to 8, characterized in that the semiconductor body (1) and the semiconductor column (2) consist of silicon, an A j uB y semiconductor or SiC.
1515
10. MOS-Feldeffekttransistoranordnung nach Anspruch 3, dadurch gekennzeichnet, daß der Trench (6) für Gate die Trenche (4, 5) für Source und Drain wenigstens berührt.10. MOS field effect transistor arrangement according to claim 3, characterized in that the trench (6) for gate at least touches the trenches (4, 5) for source and drain.
20 ιι. MOS-Feldeffekttransistoranordnung nach Anspruch 3, dadurch gekennzeichnet, daß ein Gateisolator (8) aus Siliziumdioxid und /oder Siliziumnitrid besteht.20 ιι. MOS field effect transistor arrangement according to claim 3, characterized in that a gate insulator (8) consists of silicon dioxide and / or silicon nitride.
12. Verfahren zum Herstellen der MOS-Feldeffekttransistoranordnung nach ei-12. Method for producing the MOS field effect transistor arrangement according to
~c nem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß nach Herstellung einer Ausgangs-Halbleitersäule (2) auf dem Halbleiterkorper (1) durch Ätzen die Ausgangs-Halbleitersäule (2) mit dem Füllisolator (3) umgeben wird, daß sodann in den Grenzbereich zwischen der Ausgangs- Halbleitersäule (2) und dem Füllisolator (3) die Trenches (5, 4, 6) für Sour-~ c nem of claims 1 to 11, characterized in that after the production of an output semiconductor column (2) on the semiconductor body (1) by etching the output semiconductor column (2) with the filling insulator (3) is surrounded, that then in the Border area between the output semiconductor column (2) and the filling insulator (3) the trenches (5, 4, 6) for sources
30 ce) Drain und Gate eingebracht werden, so daß von der Ausgangs-Halbleitersäule (2) nur die den Bodybereich bildende Halbleitersäule (7) zurückbleibt, daß sodann aus den Trenches (5, 4) für Source und Drain Dotierstoff des zum Dotierstoff der Halbleitersäule (7) entgegengesetzten Leitungstyps in die diese Trenches (5, 4) angrenzenden Gebiete der Halbleitersäule (7)30 ce) drain and gate are introduced, so that only the semiconductor column (7) forming the body region remains of the output semiconductor column (2), that then from the trenches (5, 4) for source and drain dopant for the dopant of the semiconductor column (7) of opposite conductivity type into the regions of the semiconductor column (7) adjoining these trenches (5, 4)
35 eingebracht wird und daß der Trench (6) für Gate mit einer Isolierschicht35 is introduced and that the trench (6) for gate with an insulating layer
(8) und auf dieser mit leitendem Material (9) gefüllt wird. (8) and on this is filled with conductive material (9).
3. Verfahren nach Anspruch 12, dadurch gekennzeichnet, daß die Ausgangs-Halbleitersäule (2) rechteckig oder oval oder T-förmig oder trapezförmig gestaltet wird. 3. The method according to claim 12, characterized in that the output semiconductor column (2) is rectangular or oval or T-shaped or trapezoidal.
EP01913571A 2000-02-04 2001-02-02 Mos field effect transistor arrangement Withdrawn EP1252657A1 (en)

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DE10004872 2000-02-04
DE10004872A DE10004872C1 (en) 2000-02-04 2000-02-04 Metal oxide semiconductor field effect transistor arrangement has source, drain and gates embedded between a column protruding from semiconductor body and insulator surrounding the column and arranged on body
PCT/DE2001/000441 WO2001057926A1 (en) 2000-02-04 2001-02-02 Mos field effect transistor arrangement

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US7515391B2 (en) * 2005-10-19 2009-04-07 Littlefuse, Inc. Linear low capacitance overvoltage protection circuit
US7489488B2 (en) * 2005-10-19 2009-02-10 Littelfuse, Inc. Integrated circuit providing overvoltage protection for low voltage lines
US10636902B2 (en) * 2018-09-13 2020-04-28 Ptek Technology Co., Ltd. Multiple gated power MOSFET device

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US4910564A (en) * 1987-07-01 1990-03-20 Mitsubishi Denki Kabushiki Kaisha Highly integrated field effect transistor and method for manufacturing the same
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US5281547A (en) * 1989-05-12 1994-01-25 Oki Electric Industry Co., Ltd. Method for manufacturing a field effect transistor
DE69213539T2 (en) * 1991-04-26 1997-02-20 Canon Kk Semiconductor device with improved insulated gate transistor
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