EP1196981A2 - Regelung von gleichspannungswandlern mit synchrongleichrichtern - Google Patents

Regelung von gleichspannungswandlern mit synchrongleichrichtern

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Publication number
EP1196981A2
EP1196981A2 EP00945283A EP00945283A EP1196981A2 EP 1196981 A2 EP1196981 A2 EP 1196981A2 EP 00945283 A EP00945283 A EP 00945283A EP 00945283 A EP00945283 A EP 00945283A EP 1196981 A2 EP1196981 A2 EP 1196981A2
Authority
EP
European Patent Office
Prior art keywords
power converter
controlled rectifier
waveform
circuitry
hold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00945283A
Other languages
English (en)
French (fr)
Inventor
Joshua Bretz
Abram Dancy
Leif Lawhite
Martin F. Schlecht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synqor Inc
Original Assignee
Synqor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synqor Inc filed Critical Synqor Inc
Publication of EP1196981A2 publication Critical patent/EP1196981A2/de
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/32Means for protecting converters other than automatic disconnection
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10Parallel operation of dc sources
    • H02J1/102Parallel operation of dc sources being switching converters

Definitions

  • Switching dc/dc converters whether isolated or non-isolated, have long used a combination of transistors and diodes to implement their switching function. More recently, the diodes have been replaced with transistors called "synchronous rectifiers" for the purpose of reducing the power dissipated by the converter. Typically, MOSFETs are used for the synchronous rectifiers, although other types of transistors such as BJTs and JFETs could also be used. While these transistors can provide a lower on-state voltage than a diode, they do need to be turned on and off at the appropriate times in the switching cycle by the application of a voltage waveform on their "control terminal" (e.g. the gate terminal for a MOSFET).
  • control terminal e.g. the gate terminal for a MOSFET
  • transistors can carry current in either direction when they are turned on.
  • Some transistors, such as the MOSFET also have an anti-parallel body diode inherent in their structure that can carry current when the transistor is turned off.
  • a Schottky diode is placed in anti-parallel with the transistor to carry this latter current because it has a lower on-state voltage and a faster turn-off recovery time than the transistor's own body diode.
  • this anti-parallel diode will be referred to herein as an "uncontrolled rectifier" to distinguish it from the active part of the transistor (i.e., the channel of a MOSFET), which will be referred to herein as a "controlled rectifier.”
  • An ORing transistor includes at least a controlled rectifier and may also include an uncontrolled rectifier. Since the controlled rectifier can carry current in both directions when it is turned on, the ORing transistor no longer solves the negative current problem.
  • a chain of three or four clamp diodes in series may be placed between the 5V output and the 3.3V output to ensure the former never gets too high compared to the latter.
  • one solution presented herein is to ensure the synchronous rectifiers and/or the ORing transistors are "disabled” (i.e., kept from turning on) under the conditions that create the problems. Once this is done, output currents can still flow, but only through the uncontrolled rectifiers.
  • This disabling of the controlled rectifiers can be done in anticipation of the negative current problem or as a result of a sensed condition that indicates the problem exists.
  • the controlled rectifiers can once again be “enabled” (i.e., allowed to turn on) so that they function as intended. Since the voltage drop across a controlled rectifier is smaller than that across an uncontrolled rectifier, the output voltage will undergo a transient if the controlled rectifier is suddenly enabled. To avoid this transient, the controlled rectifiers should be turned on in a manner that causes the average on-state voltage of the combined device to change slowly (relative to the bandwidth of the converter) from that of the uncontrolled rectifier to that of the controlled rectifier.
  • average on-state voltage it is meant the average value of the voltage drop across the parallel combination of the controlled and uncontrolled rectifiers during the time that they are conducting current. For the synchronous rectifier, this time is only a portion of the overall switching cycle.
  • mimmum current limit compares the output current to some threshold, and raises the output voltage when the output current falls below this threshold so as to limit the further decrease of the current.
  • the threshold current level might be slightly negative, zero, or slightly positive.
  • the minimum current limit can be implemented with either a fold-forward, a constant current source, or a fold-back characteristic.
  • a DC to DC power converter includes a control circuit which controls the output voltage of the converter.
  • the converter further includes an override control to the control circuit, responsive to a condition of the power converter or connected circuitry, to effect a minimum current limit.
  • the power converter includes a synchronous rectifier, and the override control substantially eliminates negative current flow through the controlled rectifier of the synchronous rectifier.
  • the override control may increase the voltage output of the power converter.
  • the minimum current limit may be a small negative or positive current, and may take the form of a current source, fold-back or fold-forward.
  • the override control may respond directly to sensed output current or to some other signal indicative of output current.
  • the signal indicative of output current may be a sensed current within the power converter such as current through an ORing transistor coupled to the output of the power converter or other controlled rectifier in the power converter.
  • the system may further disable at least one controlled rectifier in the power converter circuit in response to decision logic. For example, an ORing transistor at the output of the power converter may be disabled.
  • One power converter to which the invention is applied comprises first and second primary transformer windings connected to a power source.
  • a secondary transformer winding circuit has at least one secondary winding coupled to at least one of the first and second primary windings.
  • Each of plural controlled rectifiers has a parallel uncontrolled rectifier and is connected to a secondary winding. Each controlled rectifier is turned on and off in synchronization with the voltage waveform across a primary winding to provide the output.
  • Each primary winding has a voltage waveform with a fixed duty cycle and transition times which are short relative to the on-state and off-state times of the controlled rectifiers.
  • a regulator regulates the output while the fixed duty cycle is maintained.
  • a DC to DC power converter comprises a controlled rectifier and an uncontrolled rectifier in a power circuit.
  • a connection impedance is provided between a power circuit waveform and a controlled terminal of the controlled rectifier.
  • Hold-off circuitry is activated to disable the controlled rectifier.
  • the controlled rectifier may, for example, be a synchronous rectifier in the power circuit or an ORing transistor at the output of the power converter.
  • the connection impedance may be a completely passive circuit between the power circuit waveform and the control terminal of the controlled rectifier.
  • the power circuit waveform may be a voltage waveform, and the controlled rectifier may be implemented with a MOSFET.
  • the connection impedance comprises a capacitor and may include a resistor in parallel with the capacitor.
  • a parallel impedance may be connected in parallel with the hold-off circuitry to further attenuate the power circuit waveform when the hold-off circuitry is deactivated.
  • the hold-off circuitry may comprise a transistor between the control terminal and another terminal of the controlled rectifier to hold the controlled rectifier off when the switch is closed, and a diode may be connected in series with the transistor.
  • a waveform having a negative average may be produced at the control terminal of the controlled rectifier when the hold-off circuitry is activated.
  • the hold-off circuitry is deactivated, the waveform average applied to the control terminal increases slowly.
  • the hold-off circuitry may be activated by an enable/disable input signal from decision logic.
  • the decision logic may activate the hold-off circuitry when the power convert is shut down, in response to an indication of low output voltage from the power converter, in response to an indication of low output current from the power converter, during startup of the power converter, during a turn-off transient of the power converter, or in response to an external signal.
  • the hold-off circuitry may be inactivated in response to an indication that the waveform at the control terminal of the controlled rectifier will not result in correct drive.
  • the hold-off circuitry may be activated in response to a low voltage from a regulation stage of the power converter.
  • the hold-off circuitry may be activated in response to the power rail of the converter being too low or in response to a waveform controlling the controlled rectifier being too low.
  • a DC to DC power converter comprises a controlled rectifier responsive to a control waveform applied to a control terminal.
  • Decision logic generates an enable/disable signal to disable the controlled rectifier.
  • a circuit is responsive to the enable/disable signal to gradually change the degree to which the controlled rectifier is turned on or off such that a substantial momentary deviation in the output voltage is avoided when the controlled rectifier is enabled or disabled.
  • the control waveform may be provided passively from a power circuit of the power converter. The time over which the average of the control waveform changes may be determined by a resistive/capacitive circuit between the control terminal and the power circuit.
  • Figure 1 illustrates a non-isolated down-converter using synchronous rectification and an active drive scheme.
  • Figure 2 illustrates an isolated forward converter using synchronous rectification and an active drive scheme.
  • Figure 3 illustrates an isolated forward converter using synchronous rectification and a passive drive scheme.
  • Figure 4 illustrates an isolated forward converter with the synchronous rectifiers driven by auxiliary transformer windings.
  • Figure 5 illustrates another isolated dc/dc converter using synchronous rectifiers driven through passive circuitry.
  • Figure 6 illustrates an insertion of a logic gate in an active drive circuit to enable/disable a synchronous rectifier.
  • Figure 7 illustrates an insertion of a connection switch and a hold-off circuitry in a passive gate drive circuit to enable/disable a synchronous rectifier.
  • Figure 8 illustrates an insertion of a connection impedance and a hold-off circuitry in a passive gate drive circuit to enable/disable a synchronous rectifier.
  • Figure 9 illustrates a specific implementation of the concepts depicted in Figure 8.
  • Figure 10 illustrates the implementation of Figure 9 modified such that only one transistor is used in the hold-off circuitry for two synchronous rectifiers.
  • Figure 11 illustrates a non-isolated down-converter using synchronous rectification and a passive drive.
  • Figure 12 illustrates an ORing transistor driven by an active control circuit with a logic gate to provide the enabling/disabling function.
  • Figure 13 illustrates an ORing transistor driven by waveforms in the power circuit shown in Figure 5.
  • Figure 14 illustrates deriving the enable/disable signal from the control circuit's shutdown signal.
  • Figure 15 illustrates a specific implementation of the concept depicted in
  • FIG. 9 in which an opto-isolator is used to convey the enable/disable input signal from the input-side control circuit.
  • Figure 16 illustrates using a switching waveform in the power circuit to indicate that the converter has been shutdown to provide a "shutdown decision logic signal.”
  • Figure 17 illustrates using a comparator circuit to detect that the output voltage is too low and to disable the synchronous rectifier.
  • Figure 18 illustrates a sensing output current direction indirectly through the voltage drop across the synchronous rectifiers.
  • Figure 19 illustrates a dc/dc converter using synchronous rectifiers in which the decision to enable/disable the rectifiers is provided by an externally supplied signal.
  • Figure 20 illustrates slowly enabling a synchronous rectifier by gradually increasing its on-state duration during its normal conduction interval.
  • Figure 21 illustrates a converter implementing a minimum current limit.
  • Figure 22 illustrates that voltage/current characteristics of a converter having both minimum and maximum current limits.
  • Figure 23 illustrates a circuit to implement both maximum and minimum current limits.
  • MOSFETs will be used to implement the synchronous rectifiers and the ORing transistors since the MOSFET is the preferred device at this time.
  • One skilled in the art would know how to incorporate the concepts presented here for other types of transistors that might instead be used.
  • active-drive is to provide the control signal with electronic circuitry that may get its timing information from other electronic circuitry or from voltage or current waveforms within the power circuit.
  • the second approach is to provide the control signal either directly or through passive circuitry (such as resistors, capacitors, and/or inductors) from a waveform in the power circuit.
  • the active-drive approach is most often used in non-isolated dc/dc converters.
  • Figure 1 depicts a down-converter having a switching transistor 101 and a synchronous rectifier 102, two filter capacitors, 103 and 104, and a filter inductor 105.
  • the same control circuit 106 that turns on and off transistor 101 of a down-converter can be easily designed to turn on and off the synchronous rectifier 102 of this converter.
  • Such integrated circuits are available from companies such as LTC, Maxim, and Unitrode.
  • FIG. 2 depicts an isolated forward converter having a transformer 201, a switching transistor 101 and two synchronous rectifiers 202 and 203, and filter elements 103,104, and 105.
  • Output-side control circuitry 205 might create its own timing signals for driving transistors 202 and 203, it might derive them from waveforms in the power circuit, or it might derive them from signals passed to it (through an isolation link such as a transformer or a opto-coupler) from control circuit 204 on the input side of the power circuit. Examples of these schemes are well known in the art.
  • Figure 3 shows an example of how to control synchronous rectifiers 202 and 203 by connecting their control terminals directly to nodes in the power circuit.
  • control circuit 204 turns on transistor 101
  • the resultant positive voltage across the transformer 201 will cause the voltage at node A to be high, which will turn on synchronous rectifier 202.
  • the voltage at node B will then be low, which will turn off synchronous rectifier 203.
  • power will flow from the input source, through the transformer, and out to the load.
  • the voltage across the transformer will be negative.
  • the voltages at nodes A and B will then be such that synchronous rectifier 202 will be turned off and synchronous rectifier 203 will be turned on to maintain the current flow in inductor 105.
  • Figure 4 shows a variation of the approach depicted in Figure 3 where auxiliary windings 403 and 404 have been added to the isolation transformer's primary winding 401 and secondary winding 402 to drive the control terminals of the synchronous rectifiers 202 and 203.
  • the polarity of these auxiliary windings are arranged to make sure the correct synchronous rectifier is turned on during each portion of the switching cycle, and the turns-ratios are chosen to provide the correct level of drive voltage.
  • Other examples of using auxiliary transformer windings are well known in the art.
  • Figure 5 shows another transformer-based dc/dc converter which incorporates a down converter stage, composed of transistors 101 and 102 and filter elements 105, 500 and 515, to provide regulation and an isolation stage with two transformers having primary windings 501 and 503 and secondary windings 502 and 504.
  • Transistors 516 and 517 alternately connect primary windings 501 and 503 to the output of the regulation stage, and synchronous rectifiers 505 and 506 alternately connect the secondary windings to the output capacitor 104.
  • Capacitor/resistor dividers Capacitor/resistor dividers
  • a logic gate 604 could be added to the signal path between the control circuit 602 and the synchronous rectifier's gate driver 603, as shown in Figure 6.
  • This logic gate could take many forms, it might be composed of an integrated circuit or discrete parts, and its location in the signal path has some flexibility beyond the placement shown here, all of which would be immediately apparent to one skilled in the art.
  • the logic gate requires an input signal 605 to tell it when to enable/disable the synchronous rectifier. The manner in which this signal might be generated will be discussed later.
  • connection switch could be placed in series with the control terminal to connect or disconnect the control terminal from the waveform in the power circuit.
  • the circuit might also require “hold-off circuitry” to ensure the synchronous rectifier is held off when the connection switch is turned off.
  • FIG. 7 shows one embodiment of this approach where MOSFET 701 is used for a synchronous rectifier in a power circuit.
  • Connection switch 703 connects the waveform in the power circuit 702 to the gate of the MOSFET. This connection switch is turned on and off with a signal applied to its control terminal 704.
  • Hold-off circuitry 706 might be a passive impedance such as a resistor, or it might be another switch that is turned on when the connection switch 703 is turned off, or it might a more complex electronic circuit. If a resistor is used, it should be low enough in resistance to discharge the parasitic capacitance of the MOSFET's gate in the time required, yet high enough in resistance to keep its power dissipation small when the synchronous rectifier is enabled.
  • connection impedance 803 is placed between the power circuit waveform 702 and the control terminal of the MOSFET 701 used for a synchronous rectifier.
  • This connection impedance works in conjunction with the hold-off circuitry 706 to enable/disable the MOSFET in the following manner.
  • the hold-off circuitry is activated so that it pulls the MOSFET's gate-source voltage below its threshold level.
  • the connection impedance permits the waveform at the control terminal of the MOSFET to be different than the power circuit waveform 702.
  • the hold-off circuitry is deactivated and the control terminal waveform is representative of the power circuit waveforms with, perhaps, some attenuation. Note that in this scheme, the hold-off circuitry requires active components.
  • connection impedance should be chosen such that the level of current flowing through the hold-off circuitry when it is activated is acceptably low while still maintaining a proper waveform on the control terminal when the hold-off circuitry is deactivated.
  • Figure 9 shows a more specific example of the concepts depicted in Figure 8 as they are applied to the capacitor/resistor divider concept depicted in Figure 5.
  • the parallel combination of capacitor 903 and resistor 904 form the connection impedance
  • transistor 905 in series with diode 906 form the hold-off circuitry.
  • a switch 905 and a diode 906 are placed in parallel with each of the RC circuits 508,510 and 512,514.
  • the isolation stage of Figure 5 is switching, the voltage waveforms at the nodes marked A and B are square waves.
  • the voltage of the square- wave is near zero, and during the other half of the cycle (herein referred to as the "drive half of the cycle") the voltage is near twice the output voltage.
  • the two square- wave waveforms at nodes A and B are 180 degrees out of phase with respect to one another. See PCT Application No. WO98/33267 published 30 July 1998 for a complete description of how this power circuit works.
  • the voltage waveforms on the gates of the synchronous rectifiers have the same shape as the waveforms of nodes A and B.
  • the ac components are attenuated by the divider effect of the capacitors (C 507 /(C 507 +C 512 ) or C 511 /(C 5I I +C 50g )) and the dc components are attenuated by the divider effect of the resistors (R 514 /(R 509 +R 514 ) or R 510 /(R 513 +R 5 i 0 )).
  • connection impedance serves two purposes in this case: a voltage divider and a means by which the synchronous rectifier can be disabled.
  • the voltages at nodes A and B will be square-waves going between near zero volts and near 30 volts. Thirty volts is usually too high a voltage to apply to the gate of a MOSFET. But if we make the capacitance of capacitor 507 half that of capacitor 512 and the resistance of resistor 509 twice that of resistor 514, then the voltage waveform at the gate terminal of MOSFET 506 will be an attenuated square- wave that goes between near 0 volts and near 10 volts. Many MOSFETs can tolerate this range.
  • connection impedance shown in Figure 9 can still be added to the circuit to permit the hold-off circuitry to disable the synchronous rectifiers. It is simply necessary to make C 904 large compared to any parasitic capacitance of the MOSFET's gate terminal (and R ⁇ small compared to the effective resistance of the deactivated hold- off circuitry) so that the attenuation of the waveform will be minimal.
  • the hold-off circuitry When the transistors of the hold-off circuitry are turned on, the hold-off circuitry holds, or clamps, the gate waveforms near zero during the drive half of the cycle. These gate waveforms then go negative during the reset half of the cycle since capacitors 507 and 511 appear as a low impedance for the AC components of the waveforms at nodes A and B.
  • the gate waveforms therefore have the same square-wave shape they used to have, but the dc components of these square- waves are lowered such that the highest voltage the gate waveforms achieve does not reach the gate-source threshold level required to turn on the MOSFETs they drive.
  • the connection impedance approach requires a smaller transistor than does the connection switch approach depicted in Figure 7.
  • the gate waveforms are able to go slightly positive due to the voltage drop across the series connection of the diode and transistor of the hold-off circuitry. This positive value must be kept smaller than the threshold voltage of the MOSFETs.
  • Techniques that can be used to ensure this condition include using Schottky diodes, making the on-state voltage of the hold-off transistor as small as possible, and connecting the hold-off circuitry to a negative voltage potential instead of ground. Other techniques will be apparent to one skilled in the art given the ideas presented here.
  • the hold-off circuitry can use only one transistor instead of the two to disable two synchronous rectifiers.
  • a single transistor 1011 is connected to the two gate terminals of synchronous rectifiers 1001 and 1002 through diodes 1007 and 1008.
  • transistor 1011 works with diode 1007 to clamp the gate voltage of MOSFET 1001 during its drive half cycle, and it then works with diode 1008 to clamp the gate voltage of MOSFET 1002 on the next half cycle.
  • Figures 9 and 10 show the transistor (905 or 1011) of the hold-off circuitry as a bipolar transistor. Other transistors, such as a MOSFET could also be used.
  • the discussion above points out that the active-drive approach is most often used in a non-isolated converter, it is also possible to use the passive-drive approach.
  • a second winding 1101 with an appropriate turns-ratio could be added to inductor 105 and connected to the gate terminal of synchronous rectifier 102, as shown in Figure 11.
  • the concepts outlined above for using a connection switch or a connection impedance in conjunction with hold-off circuitry could therefore be applied in this situation, as well.
  • an ORing transistor When an ORing transistor is used to connect a dc/dc converter's output to the output bus the negative current problem can also be solved by turning off the controlled rectifier of this device. Doing so leaves the converter connected to the output bus only through the uncontrolled rectifier that does not permit negative current flow.
  • an active electronic circuit 1203 and gate driver 1205 might be used to control the ORing transistor 1202, in which case a logic gate 1204 could provide the enabling/disabling function.
  • FIG. 13 shows one way this might be accomplished for the converter of Figure 5.
  • the voltage waveforms at nodes A and B of the power circuit 1301 of Figure 5 are connected through diodes 1303 and 1304 to the gate terminal of the ORing MOSFET 1302.
  • Diodes 1303 and 1304 peak-detect these waveforms to give a gate-source voltage of approximately the output voltage.
  • resistor 1305 will discharge the gate of the ORing transistor 1302 to turn it off.
  • the enabling/disabling schemes that use connection switches, connection impedances, and hold-off circuitry mentioned above for synchronous rectifiers could be used here for the ORing transistor, as well.
  • shutdown decision logic ensures that the converter will not draw a negative current when the converter is not operating. It might be implemented by deriving the enable/disable input signals directly from the shutdown signal.
  • Figure 14 shows how this might be done for a non-isolated converter.
  • electronic control circuit 106 has a section 1407 that responds to either an externally applied on off signal 1408 or internal protection circuitry that senses an abnormal condition to generate a shutdown signal 1406.
  • Logic gate 1404 uses this shutdown signal as one of its inputs to enable or disable the normal gate drive signal 1407 on its path to the gate drive 1405 leading to the gate terminal of synchronous rectifier 102.
  • opto-isolator 1510 has an output transistor that drives an inverting buffer composed of transistor 1506 and resistor 1507. The output of this buffer then drives hold-off transistor 1505 that pulls down the gates of synchronous rectifiers 1501 and 1502 through diodes 1503 and 1504.
  • An alternate method for generating the enable/disable input signals for the shutdown decision logic approach is to indirectly discern when the converter is shutdown by observing waveforms in the power circuit that change their shape depending on whether or not the converter is operating. For instance, the voltage at node X of Figure 1, the voltage across LI of Figure 1, or the voltage across the secondary winding of the circuits in Figs. 2-5 could be used.
  • Figure 16 shows one example of how this indirect method might be implemented for any of these circuits.
  • the voltage at a node that has a switching waveform is peak detected by diode 1601, capacitor 1602, and resistor 1603. If the converter is switching, the voltage across capacitor 1602 should be high; if it is not switching the voltage should be low.
  • a comparator senses a divided version of this voltage and compares it to a reference voltage 1607. If the voltage across the capacitor is too low, indicating that the converter has stopped switching, the comparator output goes low 1608. This low signal can then be used to disable the synchronous rectifier in the power circuit 1610. More than one switching node in the power circuit can be sensed. For instance, in the power circuit of Figure 5, both nodes A and B could be sensed by using two diodes in the peak detect circuit.
  • a second decision logic approach that could be used is to disable the controlled rectifiers of synchronous rectifiers and/or ORing transistors whenever the output voltage is too low.
  • This "output under-voltage decision logic" ensures that the converter will not draw a negative current when conditions such as start-up, an excessive load current, a short-circuit, or some other abnormal event causes the output voltage to be pulled lower than it would be under normal operating conditions.
  • This decision logic approach might be implemented by directly sensing the output voltage with a comparator to see if it is below some minimum threshold (e.g., 90% of its nominal value). The appropriate enable/disable input signals can then be derived with circuitry such as is shown in Figure 17.
  • This circuitry contains a comparator 1605 that compares a representation of output voltage (generated by the resistor divider network 1603 and 1604) with a voltage generated by reference 102. Hysteresis might be added to the comparator according to well understood principles of design. This decision logic approach might also be implemented by sensing some other voltage or current in the power circuit that is indicative of the output voltage.
  • a third decision logic approach that could be used is to disable the controlled rectifiers of synchronous rectifiers and/or ORing transistors whenever the output current falls below some threshold level.
  • the threshold level in this "low output current decision logic approach" might ideally be set at zero so that whenever the converter starts to draw a negative current the controlled rectifiers are disabled, thereby preventing the negative current from flowing. However, it is not necessary to choose zero amps for the threshold level.
  • a slightly negative value say 1%-10% of the rated current
  • a slightly positive threshold level could be used to make sure the converter never draws a negative current. This would cause a small, but still positive load current to flow through the uncontrolled rectifiers rather than the more efficient controlled rectifiers, but this would not cause significant power dissipation due to the low level of current.
  • the threshold level it is not necessary for the threshold level to be precise (it could range between a small negative value and a small positive value). In addition, hysteresis could be incorporated into the comparison being made.
  • FIG. 18 shows one example of this latter method being used when the connection impedance scheme of Figure 10 is used in the power circuit of Figure 5.
  • the converter is delivering a positive output current
  • one or the other or both of the voltages at nodes A and B are negative with respect to node C at all times, depending on which one (or both) of the synchronous rectifiers 1001 and 1002 are conducting.
  • diodes 1801 and 1802 will keep the base of hold-off transistor 1011 at a low enough voltage that this transistor is turned off and the synchronous rectifiers are enabled.
  • a fourth decision logic approach that could be used is to disable the controlled rectifiers and/or ORing transistors during the start-up phase of the converter's operation.
  • This "start-up decision logic approach” ensures that the converter will not draw a negative current during a turn-on transient.
  • This approach could be implemented with the methods discussed above for the "shutdown decision logic approach,” but modified by adding a time delay such that the controlled rectifiers would be kept disabled for some time after the converter is no longer shutdown. Typical start-up transients for dc/dc converters are in the range of 5 ms to 30 ms.
  • Another way to implement this decision logic approach would be to combine the "shutdown decision logic approach” with the "output under-voltage decision logic approach.” The converter would have to be operating and the output voltage would have to rise to its nominal value before the controlled rectifiers would be enabled.
  • a fifth decision logic approach that could be used is to disable the controlled rectifiers of synchronous rectifiers and/or ORing transistors during a "turn-off transient" in which a converter's output voltage is slowly reduced to zero before it is shut down.
  • This "turn-off transient approach” ensures that the converter will not draw a negative current during this turn-off transient period.
  • this decision logic approach could be implemented with the methods discussed above for the "shutdown decision logic approach,” but modified by disabling the controlled rectifiers during the turn-off transient prior to the shutting down the converter.
  • the "output under-voltage decision logic approach” could be combined with the "shut-down decision logic approach” to achieve the desired result.
  • a sixth decision logic approach that could be used is to disable the controlled rectifiers of the synchronous rectifiers and/or ORing transistors when an external signal is applied to the converter.
  • Such a signal might be provided by circuitry that senses that a negative current exists or that a negative current problem might arise. This signal might come from another dc/dc converter, or it might come from auxiliary circuitry on the load board.
  • Figure 19 shows such an "external signal decision logic approach.”
  • a seventh decision logic approach that could be used is to disable the controlled rectifiers of the synchronous rectifiers and/or ORing transistors whenever a condition exists in which the waveforms presented to the control terminals of the controlled rectifiers will not result in their correct drive.
  • the controlled rectifiers could be disabled whenever the control circuitry's power rail is too low to guarantee its proper operation. If the active-drive circuitry gets its timing information from a waveform within the power circuit, the controlled rectifiers could be disabled whenever this waveform is too low to be properly interpreted by the drive circuitry.
  • the controlled rectifiers could be disabled whenever the waveform used to drive the control terminals of the controlled rectifiers is too low to guarantee proper control of the controlled rectifiers.
  • the voltage applied to the gates of the synchronous rectifiers 505 and 506 when they are to be turned on is proportional to the voltage across the mid-bus capacitor 500. If this mid-bus capacitor's voltage is too low, the rectifiers will not be driven with a high enough voltage to completely turn them on, and this condition could result in improper operation. Therefore, the mid-bus voltage could be sensed and the controlled rectifiers disabled whenever this voltage is below some threshold value. This threshold could be chosen to be relatively high (e.g. 50% of the mid-bus voltage's nominal value) since the mid-bus voltage should not be below this level during normal operation of the converter.
  • the average on-state voltage across a conducting synchronous rectifier or ORing MOSFET should gradually change from the larger voltage of the uncontrolled rectifier to the smaller voltage of the controlled rectifier over a time period that is comparable to or longer than the converter's bandwidth.
  • the converter's feedback loop will have time to adjust the duty ratio (or some other control variable) so that the deviation in the output voltage remains acceptably small. For example, in a converter with a 10 kHz bandwidth to its feedback loop, the slow enabling might occur over about 0.1 ms or longer.
  • the first approach is to control the degree to which the controlled rectifier is turned on. For instance, assuming a MOSFET device, the gate voltage (during the time when the MOSFET is to be conducting) can be controlled to be anywhere between the threshold level and several volts above threshold. In the former case, the MOSFET's channel resistance is very high, and in the latter case it is at its mimmum value.
  • the average on-state voltage of a MOSFET can therefore be gradually reduced from that of its uncontrolled rectifier to that of its controlled rectifier by allowing the gate voltage (during the MOSFET's conduction time) to slowly increase from the threshold level to several volts above threshold.
  • Figure 10 shows one way to achieve this slow increase of the MOSFETs' gate voltages.
  • the gate voltage waveforms are square waves that range from nearly zero during the reset half of the cycle to a voltage well above threshold during the drive half of the cycle.
  • the dc value of this waveform is positive.
  • the gate voltage waveform ranges from slightly above zero during the drive half of the cycle to a negative value during the reset half of the cycle.
  • the dc value of this waveform is negative.
  • the dc value of the gate's voltage waveform will increase from its initial negative value to its final positive value. This increase is of the form (1-e ⁇ t ), where ⁇ is the characteristic time constant C 1005 xR 1003 (or C 1006 xR 1004 ). As the dc voltage of the gate waveform increases, so too does the value of the gate voltage during the drive half cycle of the waveform. By making the characteristic time constant long enough (say several milliseconds), the average on-state voltage of the MOSFET will be slowly reduced.
  • connection impedance again serves multiple roles, including those mentioned before plus providing a means to slowly increase the MOSFETs gate voltage when it is enabled.
  • the second approach to control the average on-state voltage of a synchronous rectifier or an ORing transistor is to control the percentage of time (during the overall time that the combined device is to be conducting) that the controlled rectifier is turned on.
  • the controlled rectifier may be turned on very briefly during the conduction time, or it may be turned on for the entire interval.
  • the average on-state voltage of the combined device is nearly that of the uncontrolled rectifier (since it carries the current for the vast majority of the time), and in the latter case, the average on-state voltage of the combined device is that of the controlled rectifier.
  • the average on-state voltage of a synchronous rectifier or an ORing transistor can therefore be gradually reduced from that of its uncontrolled rectifier to that of its controlled rectifier by allowing the percentage of time that the control rectifier is turned on to slowly increase.
  • Figure 20 shows one way this might be accomplished when an electronic circuit is used to provide the control signal for a synchronous rectifier.
  • the logic gate that is used to enable/disable the controlled rectifier is preceded (on its gating input) by a circuit composed of a ramp generator circuit 2012 (inverter 2002, base resistor 2003, transistor 2004, current source 2005, and capacitor 2006), a comparator 2001, and an RC network 2007, 2009 with a diode 2008.
  • the ramp generator circuit creates a ramp that begins at zero volts whenever the drive signal 2010 from the electronic control circuit 602 indicates that the synchronous rectifier 601 should be on.
  • This ramp which continues to rise throughout the proposed conduction time, is shifted up by 1 volt due to voltage source 2010 and used as the negative input to the comparator, 2001.
  • the output of this comparator will only be high, and therefore allow the drive signal 2010 to get through logic gate 604, if the voltage on the positive input of the comparator is higher than the ramp voltage.
  • the enable/disable input signal 605 is low, so too is the positive input to the comparator, and the output of the comparator remains low at all times, disabling the drive signal from reaching the controlled rectifier of 601.
  • the circuit shown in Figure 20 could also be used to gradually turn on a connection switch in the scheme depicted in Figure 7, or to gradually turn-off a hold-off circuitry working against a connection impedance in the scheme depicted in Figure 8. It is also possible, using the general concepts discussed above, to control the rate at which the dc/dc converter is transitioned from an enabled state to a disabled state.
  • dc/dc converters incorporate a maximum current limit in their control circuitry to protect the converter from the affects of a too large output current.
  • Various schemes are used, including ones that shut the converter off and ones that continue to operate with a reduced output voltage that is a function of the load current.
  • some converters allow the output current to increase slightly above the threshold limit as the output voltage is reduced, some maintain a constant output current, and others cause the output current to decrease.
  • These approaches are sometimes referred to as "fold-forward,” “constant current source,” and “fold-back” current limits, and various methods to achieve each approach are well known in the field. For example, as illustrated in Figure 22, the converter normally operates at a constant output voltage V ou ⁇ with the current rising as needed to serve a particular load.
  • a novel minimum current limit 1, ⁇ can be incorporated into a control circuit to avoid the problems associated with negative current flow in a dc/dc converter, particularly one that uses synchronous rectifiers and/or ORing transistors, but is not limited to such converters.
  • a current limit would increase the output voltage once the load current falls below some threshold level. The increasing output voltage would then counteract the desire for the output current to decrease further.
  • the threshold level for the minimum current limit could be slightly negative as illustrated, zero, or slightly positive. The desire is to avoid a negative current that is large enough to cause a problem. For instance, a slightly negative threshold level (say 1%-10% of the rated current) could be used to make sure the converter works as intended all the way down to zero load current. This would allow some negative current to flow in an abnormal situation, but not enough to detrimentally affect the system's performance. Or a slightly positive threshold level could be used to make sure the converter never draws a negative current. This would cause a small, but still positive load current to flow through the uncontrolled rectifiers rather than the more efficient controlled rectifiers, but this would not cause significant power dissipation due to the low level of current.
  • the mimmum current limit control circuitry can be designed to display the characteristics of a fold- forward, a constant current source, or a fold-back current limit.
  • a fold-forward characteristic 2204 would allow the output current to continue to decrease slightly as the output voltage is increased.
  • the constant current source characteristic 2205 would hold the output current roughly constant as the output voltage increased.
  • the fold-back characteristic 2206 would make the output current increase above the threshold level once the output voltage increased.
  • This dc/dc converter could be a non-isolated or an isolated converter of any topology.
  • the sensing of the output current could be accomplished with several different types of sensors, such as a resistor, a current transformer, or a Hall effect sensor.
  • the sensed current could be at the output terminals, or at some other location within the power circuit where the current sensed is indicative of the output current. In some cases, other variables besides current (but that are indicative of the output current) could be sensed. In general, sensing techniques like those used in the third, low output current decision logic approach discussed above with respect to disabling the synchronous rectifiers and ORing transistors may be used here.
  • control circuit would typically adjust the dc/dc converter's duty cycle. For instance, in the down-converters of Figures 1-5, the duty cycle of transistor 101 would be increased.
  • An advantage of increasing the voltage output rather than turning off the synchronous rectifiers is that, with the synchronous rectifiers left on, they continue to operate in an efficient mode when large currents are flowing. On the other hand, when the rectifiers are turned off, the uncontrolled rectifier continues to operate alone, and in this inefficient condition, the circuit may heat up.
  • the output voltage could be increased when the mimmum current threshold is reached, and the synchronous rectifiers and ORing transistor could subsequently be disabled when a voltage threshold or other current threshold were reached.
  • Figure 23 shows one method to implement both a maximum and a minimum current limit.
  • Ul 2301 and U2 2302 are op-amps and V ref is a reference voltage.
  • the current, I, to be sensed flows through resistor 2303 and creates a voltage, V bland relative to ground.
  • the op-amps are configured as differential amplifiers with the addition of resistors 2304 through 2311.
  • Capacitors 2313 and 2314 reduce the gains of these amplifiers at high frequencies to stabilize the current limit feedback loops.
  • Capacitor 2312 filters any high frequency components of the sensed signal, V l5 due to noise in the power circuit.
  • Op-amp 2301 is responsible for the maximum current limit and op-amp 2302 is responsible for the mimmum current limit.
  • Resistors 2305 and 2304 provide a level shift, V LS , for V render the amount of the shift dependent on V ref and the relative values of the two resistors. Both op-amps amplify the difference between this level- shifted value of V, and a threshold voltage, but they each have different thresholds values, V T1 and V T2 , set by V ref and either resistors 2306 and 2307 or resistors 2309 and 2310, respectively.
  • V T1 is set higher than V LS by an amount that corresponds to the maximum current limit desired.
  • V T1 is set relative to V LS by an amount that corresponds to the minimum current limit.
  • the two op-amps can only affect the output voltage, V 0 , in one direction.
  • Op-amp 2301 will pull V CL up when the sensed current exceeds the maximum current limit
  • op-amp 2302 will pull V CL down when the sensed current falls below the minimum current limit. The more the sensed current exceeds (or falls below) these two limits, the more the op-amps pull up (or down) V CL .
  • node V CL is essentially in a high impedance state (limited by the relatively high impedances of resistors 2308 and 2311 and capacitors 2313 and 2314.
  • V CL is used as an additional input to the error amplifier 2317 of the normal feedback loop that determines the power converter's duty cycle. It will affect the error amplifier, and therefore the duty cycle, only when the sensed current goes out of range. Its connection to the amplifier is such that when the sensed current exceeds the maximum current limit, the power converter's output voltage is reduced. Conversely, when the sensed current falls below the minimum current limit, V CL causes the converter's output voltage to rise.
EP00945283A 1999-07-07 2000-07-07 Regelung von gleichspannungswandlern mit synchrongleichrichtern Withdrawn EP1196981A2 (de)

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US14258099P 1999-07-07 1999-07-07
US142580P 1999-07-07
US14398099P 1999-07-15 1999-07-15
US143980P 1999-07-15
US14625299P 1999-07-29 1999-07-29
US146252P 1999-07-29
US17288499P 1999-12-20 1999-12-20
US172884P 1999-12-20
PCT/US2000/018748 WO2001003277A2 (en) 1999-07-07 2000-07-07 Control of dc/dc converters having synchronous rectifiers

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JP2003504997A (ja) 2003-02-04
CA2378666A1 (en) 2001-07-11

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