Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/38—Calibration
  • H03M3/386—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
  • H03M3/388—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M3/00—Conversion of analogue values to or from differential modulation
  • H03M3/30—Delta-sigma modulation
  • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
  • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
  • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
  • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Definitions

• the subject of the present invention is a method and a system for compensating for the non-linearity of a sigma-delta analog-digital converter.
• a sigma-delta analog-digital converter mainly comprises a summator 1, a noise shaping filter 4, a quantizer 5, a digital filter 6 and a feedback loop 8 connecting the output from the quantizer 5 to the negative input 3 of the summator 1.
• This feedback loop 8 comprises a digital analog converter 7.
• a block-sampler-blocker (not shown), generally placed upstream of the adder 1, has the task of oversampling the signal at a given frequency, then keeping the level of output 2 constant to allow information processing by the sigma-delta analog-digital converter.
• the noise shaping filter 4 performs a shaping of the noise spectrum so as to attenuate the noise power in the frequency range of the useful signal.
• the quantizer block 5 has a set of discrete levels.
• the quantizer 5 associates it with the closest discrete level. This level quantization introduces an error called "quantization noise".
• Quantization noise The performance of a converter is conditioned by the power of this quantization noise.
• the oversampling carried out at the level of the sample-and-hold block (not shown) and the feedback loop 8 make it possible to "repel" the maximum of the power of the quantization noise outside of the bandwidth of the signal. (operating frequency band of the system).
• the digital filter 6, also called the decimation filter, placed at the output of the sigma-delta analog-digital converter makes it possible to eliminate the quantization noise that has been shaped as well as to sub-sample the output signal.
• the digital-analog converter 7 has a transfer function which makes it possible to link the digital (quantization) input levels delivered by the quantizer 5 to analog output values which are then delivered to the negative input 3 of the summator 1. For each quantization level present at the input, the digital-analog converter 7 associates it with an analog value corresponding to the output.
• the fundamental principle of the sigma-delta analog-digital converter consists first of all in oversampling the signal using the analog sampler-blocker, in pushing the maximum of the power of the quantization noise outside of the signal bandwidth by integrating the quantizer in a feedback loop, then filtering the signal obtained using a digital filter 6. These combined actions allow in a first time to "dilute" the quantization noise in a wide band thanks to oversampling, to carry out a shaping of the noise spectrum and then to filter the quantization noise to keep only the useful band of the signal.
• the multi-bit sigma-delta analog-digital converter is transformed into a one-bit sigma-delta analog-digital converter (only the most significant bit at the output of the quantizer is considered).
• the calibration phase essentially involves the elements described in Figure 2.
• the digital-analog converter 7 is then placed at the positive input 2 of the adder 1.
• a counter Eb controls the digital-analog converter 7 by delivering a digital signal (corresponding to one of the different possible levels of the quantizer 5) so that the latter generates an analog signal at the input of said converter one-bit sigma-delta analog-digital.
• An adder Ec receiving the signal from the output of the counter Eb and the signal from the output of the decimation filter 6 makes it possible to calculate a correction value which is stored in a memory module Ed.
• the counter Eb also controls the addresses of the memory module Ed.
• Each correction value represents a digital conversion difference due to the digital-analog converter 7 between a digital value and its conversion to analog.
• the sigma-delta analog-digital converter is equivalent to that of FIG.
• the digital correction module placed in front of the decimation filter 6 and containing the correction values. Any digital value leaving the quantizer 5 is corrected by the digital correction module before entering the decimation filter 6. Thus, the digital value, after correction, entering the decimation filter 6 is substantially equal to the arriving analog value by the negative input 3 of the summator 1.
• the switches 9, 10 and 12, 13 allow respectively to switch a capacitance C j and a capacitance C 2 which are connected to ground 14.
• the summator has two inputs El and E2 linked respectively to the capacitances C 1 and C 2 -
• An amplifier operational 11 performs the summing operation using a capacitor C connected in feedback.
• Capacities C l and C 2 are theoretically of the same value. But in reality, because of the dispersions, these values are different and the gain between the two inputs is therefore different.
• the digital-analog converter is therefore placed at the input El and the values injected are precisely measured.
• the digital-analog converter included in the feedback loop is placed at the input E2 of the adder.
• the values measured during the calibration phase are therefore not really the values injected during the normal operating phase.
• the accuracy of the measurement is influenced by possible offset voltages that may intrinsically exist in the sigma-delta analog-digital converter. These offset voltages may not be annoying during the normal operating phase, but they can become a drawback during the calibration phase since DC voltages are measured.
• the invention aims to provide a solution to this problem by preserving the structure of the sigma-delta analog-digital converter during the calibration phase and by using only digital signals.
• the invention proposes a method for compensating for the non-linearity of a sigma-delta analog-digital converter with quantization at N levels integrating a digital-analog converter in a feedback loop.
• N is an integer strictly greater than two.
• the method comprises a normal operating phase in which a plurality of numerical values corresponding to a plurality of quantization levels is modified by correction values Ci, i positive integer between 1 and N, calculated during a phase d 'calibration.
• the correction values Ci are calculated from the values of the output of the sigma-delta analog-digital converter processed digitally, while keeping the digital-analog converter in the feedback loop of the converter.
• the sigma-delta analog-digital converter and by transforming the multi-bit sigma-delta analog-digital converter into sigma-delta analog to digital converter with quantization at three levels, for example modifiable.
• the number N is a positive integer strictly greater than two.
• the correction values C ⁇ make it possible to correct the errors of the digital-analog converter.
• the corrections are made instantaneously during the normal operating phase.
• the method of compensating for non-linearity comprises a calibration phase in which the multi-bit sigma-delta analog-digital converter is transformed into a sigma-delta analog to digital converter with quantization at three levels, X m , X M and X j , i ranging from 1 to N-2; for a period Pl j , a predetermined value is delivered to the input of the sigma-delta analog-digital converter and the values of the output of the sigma-delta analog-digital converter are processed digitally; this N-2 calibration phase is carried out by keeping the levels X m and X jj , and successively taking for the level X j the N-2 levels other than the levels X m and X j y j .
• the correction values C j of the N-2 levels other than X m and Xp ⁇ are advantageously calculated using the processed values, the N-2 correction values C j being able to modify the N-2 levels other than X m and X dd during the normal operating phase.
• the levels X ⁇ X M and X j are digital values which will be transformed into analog values according to a transfer function of the digital-analog converter.
• the method can further comprise, during the calibration phase and before the calculation of the correction values Ci, at least one step F in which the analog-digital sigma-delta multi-bit converter is converted into an analog-to-analog converter.
• sigma-delta numeric with quantization at two levels which are X m and XJ ⁇ J.
• said predetermined value is delivered to the input of the sigma-delta analog-digital converter and the successive values of the output of the sigma-delta analog-digital converter are digitally processed.
• step F makes it possible to advantageously eliminate any offset voltages that may exist in the sigma-delta analog-digital converter.
• the durations Pl j can for example be all equal to each other and equal to the duration P2 when step F is carried out only once.
• the analog-digital sigma-delta converter with quantization at N levels is transformed into an analog-digital converter sigma-delta with a quantization number less than N by modifying quantization threshold values and a digital processing of implementation of internal comparators.
• the sigma-delta analog-digital converter with quantization at N levels is transformed into sigma-delta analog-digital converter with quantization at three levels, and in the optional case of carrying out step F (correction offset voltages), it is also transformed into a sigma-delta analog-digital converter with quantization at two levels.
• the levels X ⁇ and X M are respectively the minimum value and the maximum value of the N quantization levels.
• the value digital after correction is substantially equal to the analog value at the output of the digital-analog converter.
• said value predetermined is equal to zero and during the calibration phase, during the duration Pl j for each level X j , the number N j of values equal to is counted at the output of the sigma-delta analog-digital converter (A2) X j , the total number NT j of all the output values and a sum Sl j of the NT is made ; values.
• step F of the calibration phase can be performed N-2 times by taking a duration P2 for each embodiment; equal to each duration Pl ; and we add up in S2 j all the values coming out of the sigma-delta analog-digital converter
• the duration Pl j for each level X j , is equal to the duration necessary for the counting at the output of the analog-digital converter sigma-delta of the number N j of values equal to X j , until the number N j is equal to a given number N Q.
• the invention also proposes a system for compensating for the non-linearity of an analog-digital sigma-delta converter with quantization at N levels comprising in particular a digital converter analog and a digital filter.
• the system comprises means of implementation for carrying out the different phases described previously.
• the means of implementation include:
• a correction module interposed between the quantizer and the digital filter and communicating with the processing means, - comparators and a digital processing module internal to the quantizer at N levels and capable of transforming the quantifier into a quantifier at levels lower than N .
• FIG. 4 is a diagram of the general structure of the sigma-delta analog-digital converter according to the invention.
• FIG. 5 is a schematic view of a three-level quantizer according to the invention.
• FIG. 6a and 6b illustrate the result of the transformation of a five-level quantifier into a three-level quantifier.
• the diagram in Figure 4 consists of three parts. A first part A1 relating to input signals, a second part A2 relating to the sigma-delta analog-digital converter itself, and a third part A3 relating to a signaling system piloting.
• the first part A1 has an input 15 of value equal to zero and used during a calibration phase and an input 16 receiving the analog signal to be digitized by the sigma-delta analog-digital converter.
• a switch 17 makes it possible to connect either to input 15 or to input 16.
• a signal coming from the inputs 15 or 16 passes through the positive input 18a of an adder 19.
• a noise shaping filter 20 recovers the output signal from the adder 19.
• the signal 21 leaving the noise shaping filter 20 is a signal which is delivered to the input of a quantizer 22 comprising three quantization levels: -1; 0 and 1.
• This quantizer 22 generates a digital signal 23 which, during a normal operating phase, is delivered to the input of a corrector module 27 by means of a switch 26.
• the output signal of the module- corrector 27 then passes through a digital filter 28 in order to be sub-sampled. The subsampling allows to bring back around the frequency of Nyquist.
• the digital signal 23 also passes through a feedback loop 25 comprising a digital-analog converter 24, the output signal of which is sent to the negative input 18b of the adder 19.
• the third part A3 is a control device comprising an accumulator 29, a counter 30 and a second counter 31, all of which are connected to a random access memory module 32 connected to a digital processing module 33.
• This digital processing module 33 makes it possible to perform calculations and generate data signals 35 to the corrector module 27 of the sigma-delta analog-digital converter and control signals 34 to the quantizer 22 and the switches 17 and 26.
• the digital-analog converter 24 receives three different digital values (for example in the form of two bits coding 01, 00 and 10 representing the values -1, 0 and 1) and converts them into three analog values which should ideally take the values -1; 0 and 1. Generally the three analog points obtained do not do not ideally correspond to the values -1, 0 and 1.
• the correction of point 0 is independent of the zero value at input 15. Indeed, it is possible to correct points +1 or -1 by always having the value zero at input 15.
• the switch 17 is switched to the input 15 of zero value, and the switch 26 is switched to an input 36 common to the accumulator 29, to the counter 30 and to the second counter 31.
• the quantizer 22 operates in a three-level quantization mode. Using the counter 31, the number N Q of 0 (point to be corrected) contained in the digital signal 23 passing through the input 36 to the counter 31 is counted. The counting is carried out until the number N Q reaches a predetermined number. This predetermined number is chosen as a power of two in order to facilitate subsequent calculations. We take it equal to 2 18 for example, or 262,144.
• the sum SI of the values of the output signal of the quantizer 22 is calculated.
• This sum SI is stored in the RAM 32 as well as the number of points N j which have been generated by the quantizer 22 and counted using the second counter 30.
• the value 2 1S is chosen large enough so as to have good precision on the stored values.
• the division is done simply in the digital processing module 33 because we took care to choose a power of two for
• the value C is then saved in memory 32 which in fact comprises three sub-compartments in which the number N 1 has been saved ? the sum SI and the value C.
• the switch 17 is toggled on the input 16
• the switch 26 is toggled on the corrector module 27 and the quantizer 22 operates with three quantization levels -1, 0 and +1.
• the analog signal to be digitized therefore arrives via input 16, then leaves the quantizer 22 in digital form into a signal 23 which is modified by the corrector module 27, then digitally filtered by the module 28.
• the corrector module 27 operates according to a algorithm which can be summarized in the table below:
• FIG. 5 shows the three-level quantizer 22 composed of two comparators 37 and 38 and a digital processing module 39.
• the comparator 37 has two inputs, the first of which receives the signal 21 coming from the noise shaping filter 20 , and the second input is maintained at a fixed voltage V equal to a positive quantization threshold voltage.
• Comparator 38 also has two inputs, the first of which also receives signal 21, and the second input of comparator 38 is maintained at a voltage equal to -V.
• the output of comparator 37 and that of comparator 38 enter the digital processing module 39 generating the digital output signal 23.
• the digital signal 23 takes the value of +1 .
• the signal 23 takes the value of -1.
• the signal 23 is equivalent to 0.
• the digital processing module 39 is governed by the following algorithm:
• the sigma-delta analog-digital converter thus described makes it possible to compensate for the non-linearity of the digital-analog converter by performing a calibration phase without modifying the structure of the sigma-delta analog-digital converter.
• Figures 6a and 6b show the transformation of the five-level quantifier into a three-level quantifier.
• the abscissa axis E represents the input signal 7 and the ordinate axis S represents the output signal 9.
• FIG. 6a represents the transfer function of a five-level quantifier (-1; -0.5; 0; 0.5; 1). Any input signal having for example a value between two positive values vl and v2 delimiting a range of values on the abscissa axis E will be converted into a digital signal with a value equal to 0.5 on the ordinate axis S Desiring to correct the zero level by transforming the quantifier into three levels, the intermediate levels (-0.5 and 0.5) are deleted in accordance with FIG. 6b. The three remaining levels are therefore (-1; 0; 1).
• a sigma-delta analog-digital converter with quantization at three levels sampled at a frequency of 2048 kHz has in simulation, for a signal to be converted of maximum amplitude and without correction according to the invention, a signal ratio / noise of 46 dB.
• the method thus described makes it possible to carry out a calibration phase using a quantizer at three levels then at two levels while retaining the general structure of the analog-digital converter sigma-delta.
• the calibration phase is carried out simply by controlling the various switches.

Landscapes

• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=9547448

Family Applications (1)

Country Status (4)

Families Citing this family (7)

Family Cites Families (5)

• 1999
  • 1999-06-29 FR FR9908323A patent/FR2795889B1/fr not_active Expired - Fee Related
• 2000
  • 2000-06-23 US US10/019,170 patent/US6653958B1/en not_active Ceased
  • 2000-06-23 EP EP00945993A patent/EP1192718A1/de not_active Withdrawn
  • 2000-06-23 US US11/487,666 patent/USRE42387E1/en not_active Expired - Fee Related
  • 2000-06-23 WO PCT/FR2000/001754 patent/WO2001001578A1/fr not_active Application Discontinuation

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events