EP1186129A1 - Procede et dispositif pour convertir des flux de donnees virtuellement enchaines en flux de donnees continuellement enchaines - Google Patents

Procede et dispositif pour convertir des flux de donnees virtuellement enchaines en flux de donnees continuellement enchaines

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Publication number
EP1186129A1
EP1186129A1 EP00926525A EP00926525A EP1186129A1 EP 1186129 A1 EP1186129 A1 EP 1186129A1 EP 00926525 A EP00926525 A EP 00926525A EP 00926525 A EP00926525 A EP 00926525A EP 1186129 A1 EP1186129 A1 EP 1186129A1
Authority
EP
European Patent Office
Prior art keywords
containers
channel
data streams
pointer
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00926525A
Other languages
German (de)
English (en)
Inventor
Andreas Stadler
Jürgen HEILES
Michael Zapke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Solutions and Networks GmbH and Co KG
Original Assignee
Siemens AG Oesterreich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG Oesterreich filed Critical Siemens AG Oesterreich
Publication of EP1186129A1 publication Critical patent/EP1186129A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0094—Virtual Concatenation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0096—Serial Concatenation

Definitions

  • the invention relates to a method for converting virtually linked data streams into successive (continuously) linked data streams, the data being transmitted in containers inserted in pulse frames, a sequence of N containers being combined to form a multiframe, each container having a multiframe -Indicator is provided regarding its temporal position within the multiframe, and the virtually linked data streams consist of X sub-streams / channels.
  • the invention also relates to an apparatus for performing this method.
  • signals are divided into several containers that are chained together. These linked containers can be transmitted in a common transmission frame of appropriate capacity.
  • Two methods are used for chaining containers, namely sequential (contiguous) and virtual chaining. Both methods provide a consecutive chained bandwidth that is proportional to the number X of chained containers and the container size. The difference lies in the transportation between the ends of the transportation path.
  • sequential chaining the temporal coupling of the containers is retained over the entire transport route, whereas in the case of virtual chaining, the overall signal is divided into individual virtual containers, these individual containers are transported independently and recombined to form the overall signal at the end point of the transmission.
  • virtual concatenation concatenation-specific devices are only required at the ends of the transmission path, whereas with consecutive concatenation, corresponding devices must generally be present for each network element.
  • the initial bytes of the containers are specified by so-called “pointers” which are located at predetermined positions in the pulse frame.
  • the pointers thus also have a fixed position with respect to the frame password contained in the transmission pulse frame and give the number with a number, for example between 0 and 782 Distance from the beginning of the container to the pointer.
  • the respective pointer value is used for each container on the transmission side, but different transit times of the (sub) containers, which are caused, for example, by network elements in the transmission path, can occur during the transmission. At the end of the virtually chained transmission, such runtime differences are compensated for. This is described in the concatenation of subsystem units for bit rates of an intermediate hierarchy level in EP 0 429 888 B1.
  • the invention is based on the object of specifying a possibility for converting virtually chained to successive (contigous) chained containers which takes into account the runtime differences mentioned.
  • This object is achieved according to the invention with a method of the type mentioned at the outset in that containers assigned to the same location in the multiframe are identified by evaluating the multiframe indicator, and the temporal displacement of these identified individual containers of the partial data streams is measured relative to one another when there is a displacement only leading containers are each delayed by times, which ensure that all containers are aligned in time, as well as filling levels of buffer stores are compared with threshold values in each channel and, depending on this, channel-specific stop indicators are generated and tamping operations are carried out taking into account the stop indicators of all channels.
  • the invention offers the advantage that an automatic adaptation to different transit time differences can be carried out with minimal delay.
  • the invention also allows the corresponding device to be easily configured for different link widths or for non-linked signals, whereby a modular structure can be used in which the information exchange between the modules or channels can be kept low.
  • the communication between the channels is decoupled in time from the data streams, which allows the communication signals to be used for additional concatenated signals and for other tasks which are not the focus here.
  • a device for carrying out the method according to the invention in which according to the invention a pointer interpreter is assigned to each channel, followed by an elastic memory and a pointer generator, the pointer generators are synchronized with one another, and each pointer generator is set up to control the readout of the elastic memory associated with its channel, an overhead inserter is provided in a channel selected as the master channel, to which the output data from the elastic memories is arranged - Extractors are supplied, and the elastic storage devices are set up to delay or align all containers.
  • FIG. 3 is a schematic block diagram of a device according to the
  • FIG. 5 shows a representation according to FIG. 4 for a second variant of the invention.
  • Step Findications and the generated pointer for negative stoppers for the second variant of the invention.
  • the structure of the data or data flows used in the synchronous digital hierarchy, SDH for short is first to be discussed, although the invention is not intended to be restricted to a specific system or a specific standard.
  • FIG. 1 The structure of such a container is shown in FIG. 1 and the virtual concatenation of X (sub) containers of type VC-4 in connection with a VC-4-Xc container is shown in FIG.
  • a VC-4-Xc container has a payload area of X Containers-4, as shown in FIG. 1.
  • a common set of payload overheads is arranged in the first column and used for the entire VC-4-Xc container.
  • the parity formation used here BIP-8 (Bit Interleaved Parity") records all 261 * X columns of the VC-4-Xc container. Columns 2 to X are fixed fill bits or bytes and can consist of nothing but "0".
  • the VC-4-Xc container is transported in X contingent AU-4, so-called "Administrative Units", in an STM-N signal (STM is used as an abbreviation for Synchronous Transport Module).
  • STM is used as an abbreviation for Synchronous Transport Module.
  • the first column of the VC-4-Xc- Containers are always in the first AU-4.
  • the pointer of this first AU-4 indicates the position of the start byte of the VC-4-Xc container.
  • the pointers of AU-4 No. 2 to X are set to a chaining indication to display the contingently linked payload.
  • the pointer operations are carried out for all X-linked AU-4s and X * 3 stuffing bytes are used.
  • a VC-4-Xv offers a payload range of X Containers-4, as shown in FIG. 2.
  • the contingently linked container is mapped to X individual VC-4 containers, which form the VC-4-Xv.
  • Each VC-4 has its "own” path overhead.
  • the overhead byte H4 is used as a specific sequence and multiframe indicator of virtual concatenation.
  • multiframe introduced in the art is used here for "superunit”.
  • Each VC-4 of the VC-4-Xv is transported individually through the network. Due to the individual transport, the sequence and the timing of the VC-4 containers may change. At the end of the path, the individual VC-4 containers have to be rearranged and aligned in order to restore the contingently linked container.
  • the sequence indicator in the H4 byte is used to monitor the correct sequence.
  • the sequence indicator numbers the individual VC-4 containers of the VC-4-Xv from 0 to (X - 1).
  • the multiframe indicator in the H4 byte and the pointer values of the individual VC-4 containers are used for realignment.
  • a 4-bit multiframe indicator creates a 16-frame multiframe. Reference is now made to FIG.
  • Each of these channels corresponds to a time slot of the output signal - a column of the output pulse frame - and is used to transport a VC-4 container.
  • the conversion is described for a VC-4 chaining, but can also be used in the same way for other containers.
  • the data streams first arrive in each channel in a pointer interpreter PH, PI2, whereby they arrive, for example, from another network element of the transmission system, and if necessary a switching network KOP can be connected upstream.
  • Each pointer interpreter PH, PI2 can also contain a multiframe counter MFZ, which will be referred to later.
  • a total of X independent channels are used, whereby for the sake of simplicity only two channels are drawn and a third channel is indicated. What is essential is the arrangement of an elastic memory ESI, ES2 for each channel and also a pointer generator PG1, PG2 in each channel, these local pointer generators being synchronized with one another. Each pointer generator controls the reading out of the elastic memory assigned to it.
  • One of the channels here the channel KAI, is selected as the master channel, and in this channel the output data of the elastic memory are fed to a pointer generator PG1 and an overhead inserter OI 1 for the payload.
  • the output data of the respective elastic memories are fed to an overhead extractor OE1, OE2 for the payload, and there is a data exchange between the overhead inserter Oll and the overhead extractor OE2 or the other extractors intended.
  • the master channel KAI inserts the pointer into the outgoing STM signal, whereas the other channels, which can also be referred to as "slaves", use the concatenation indication (concatenation indication).
  • the path overhead POH of the VC-4-Xc - Container is generated from the POH of the VC-4-Xv container after synchronization of the payload.
  • the pointer buffer ESI, ES2 used here is a FIFO memory for the VC-4 payload and / or the path overhead, the writing into the memory and the reading from the memory taking place with an independent SDH frame position.
  • unlinked VC-4 containers can also be transported, for which the synchronization only has to be interrupted.
  • the elastic stores ESI, ES2 ... are controlled in such a way that the payload of the VC-4 containers or these as a whole is delayed by a maximum of the maximum runtime difference between individual VC-4 containers.
  • the synchronization mechanism used for this and the stuffing strategy in operation are explained in detail below.
  • the data streams of the “slave” channels at the output of the device are passed through filler byte inserts FSI.
  • the subcontainers VC-4 can be allocated to the channels KAI, KA2 ... of the pointer buffer by means of the switching matrix KOP mentioned, whose connection matrix is automatically / manually corrected with regard to the channel allocation in the event of errors which were recognized by the sequence indicator in H4 can be.
  • the outputs of the individual channels are fed to a corresponding device to form STM frames.
  • the synchronized reading of the buffer memory which is divided over several channels, i. H. the elastic memory ESI, ES2 first requires a synchronization process when the device is switched on, as well as after alignment errors have occurred and after error states of the respective pointer interpreters PIl, PI2 of a channel, and subsequently the operations of the pointer generator PGl, PG2 can be performed synchronized.
  • the temporal position of the data stream read from the buffer memory must be determined relative to the outgoing pulse frame.
  • an H4 identifier is transmitted in each channel of the buffer memory ESI, ES2 in parallel to the payload.
  • the identifier contains an indicator bit for the position in time, ie a bit which identifies a specific position of the container.
  • the temporal position of the container can be measured relative to the position of the outgoing transmission pulse frame.
  • a pointer value P is formed, which describes the temporal position of the container relative to the transmission frame.
  • H4 identifier enables the synchronization process to be accelerated, but an identifier for each can also be used in the same way any VC-4 byte can be used.
  • a JI identifier simplifies the determination of the outgoing pointers (Hl, H2) in the master channel KAI.
  • the pointer value P of each of the X channels is distributed to the other channels of the VC-4-X container. Errors such as B. an AU-AIS of a channel (an alarm indication signal of the administrative unit), further errors in the multiframe indicator, in the sequence indicator or a buffer memory overflow or underflow from the recognizing channel to all other channels.
  • the 10-bit portion of the pointer value formed by measuring the H4 identifier in the pointer generator is protected against bit errors by filtering the pointer interpreter PI1, PI2 as provided in the standards.
  • the multiframe indicator in the H4 byte must also be filtered as part of the pointer in the pointer interpreter PI1, PI2.
  • the sequence of multiframe indicators for the pointer generator PG1, PG2 is generated with the aid of the multiframe counters MFZ in the pointer interpreters.
  • Error displays such as B. Trail signal fail, AIS or LOP are transmitted from each pointer interpreter via a signal fail signal SF to the respective pointer generator PG1, PG2.
  • the signal SF is also set in the event of an overflow or underflow of the buffer memory ESI, ES2 etc. As soon as one of the local pointer generators PG1, PG2 detects an error, this is signaled to the other local pointer generators and the entirety of the Pomter generators generates an AlS signal for the VC-4-Xc.
  • the local pointer generators PG1, PG2 After switching on the converter, the local pointer generators PG1, PG2 generate an AlS signal.
  • the read and write pointers of the buffer memory are set to values that correspond to a minimal delay.
  • the write side of the buffer memory ESI, ES2 starts writing, the read side starts reading.
  • a local pointer generator PG1, PG2 receives an H4 identifier, it makes its local pointer value P (see above) available to all other pointer generators available. With each new H4 identifier, the pointer value P is overwritten and the new value is distributed. As long as the total pointer generator of the VC-4-Xc container is in the Einsynchronisie- stage this means sets each local buffer memory ES I, ES2 with obtaining a pointer value P m i n, which is smaller than its own pointer value P, its read pointer RP to the Difference between his own and the received pointer value. Of course, the cyclicality of the pointer values must be taken into account.
  • This synchronization process is ended within an STM frame after receipt of the first H4 identifier.
  • the buffer memory of the channel that received its H4 byte last has the minimum delay set by setting the write and read pointers with the SF signal, all others have an additional delay that corresponds to the advance of the VC-4 at its input.
  • a channel KAI, KA2 detects an overflow of its buffer memory ESI, ES2 (the write address has caught up or overtaken the read address).
  • the channel reports "loss of alignment" LOA to all other channels, the entirety of the pointer generators PG1, PG2 generates an AlS signal and begins a new synchronization process.
  • the sequence indicators of the individual channels are filtered against bit errors. Votes z. For example, if several sequence indicators in a row do not match the sequence indicator determined from the channel number, the channel sends an SQM message to all other channels, and all channels together generate an AlS signal.
  • so-called "path traces” can also be read and evaluated in order to control an upstream switching matrix. Path traces are used to identify the connection path, are transmitted by a sequence of Jl bytes, and are in the ITU recommendation G.707 defined.
  • Each local buffer store ESI, ES2 calculates its current level value, e.g. B. by averaging over an STM line and monitors whether the threshold is exceeded and the Falling below the thresholds 1 / and (see Fig. 4).
  • the lower threshold is /; equal to the sum of the minimum delay d E s, min , duration of the SOH.
  • Gap tsoH, duration of the positive stuffing bytes - H3 + and maximum skew between the buffer memory input clock tO and its output clock tOs t s : d E s, m m + 3 + 1 + t s . (The information is given here in triple bytes as they are addressed by pointer.) If the frame start matches on both sides of the pointer buffer, the SOH gap duration need not be taken into account.
  • a minimum delay dEs.mm> 0 is advantageous in order to compensate for any delay in the POH compared to the payload, which may be caused by an inter-ASIC communication required to exchange the POH between the VC-4 channels of a chained VC-4 .
  • the upper stuffing threshold I 3 is determined dynamically. Every time you synchronize, it will open
  • the difference P max - Pmm is formed independently by each channel KAI, KA2 using the available pointer values of all channels.
  • the pointer generator PG1, PG2 of each channel KAI, KA2 communicates one of four possible states to all other channels. These states are:
  • the tamping is positive in all channels after compliance with the minimum tamping distance of three frames.
  • negative tamping is maintained in all channels after the minimum tamping distance of three frames.
  • the threshold references and the signaled states are evaluated simultaneously in all local pointer generators PG1, PG2, for example using the Hl byte.
  • the buffer memory delay exceeds the threshold I 3 (message NST) at least for the fastest VC-4; all other delays are h (report LDEC). The delay must be reduced for all channels. All channels in a next frame are negative tamped as soon as the minimum tamping distance is maintained.
  • Each local buffer store ESI, ES2 computes - e.g. B. by averaging over an STM line - its current level value and monitors whether the threshold is exceeded / undershot the threshold / ;.
  • Method 1 the lower threshold / _ ⁇ equal to the sum of the minimum buffer memory delay d ⁇ s.mm, SOH gap duration, duration of the SOH stuff bytes and maximum skew t s between the buffer memory input clock tO and its output clock t0 s :
  • the pointer generator PG1, PG2 of each channel KAI, KA2 communicates one of four possible states to all other channels. These states are
  • PST is taken after two frames with normal pointers, if the own channel falls below the threshold / / ,
  • NOP no operation
  • the threshold references and the signaled states are evaluated in all local locations
  • Pointer generators simultaneously, for example with the Hl byte.
  • Buffer memory delay for the slowest VC-4 seen at the buffer memory input falls below the threshold / / .
  • the delay must be increased for all channels. All channels are positively plugged as soon as the minimum plug spacing is maintained. At least one channel then reports PST, the other NOP or HIGH.
  • FIG. 6a shows the chronological sequence of the transmission pulse frames with generated pointer indications
  • FIG. 6b shows the chronological sequence of the stuff indications (SI), ie the stop indicators, of a channel.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne un procédé et un dispositif pour convertir des flux de données, de virtuellement enchaînés à continuellement enchaînés. Les données sont transmises dans des conteneurs. N conteneurs forment une multitrame. Les flux de données virtuellement enchaînés sont constitués de X flux partiels/canaux. Les conteneurs affectés à la même place dans la multitrame sont identifiés par exploitation d'un indicateur de multitrame du conteneur. Le décalage temporel de ces conteneurs identifiés de flux de données partiels est mesuré les uns contre les autres. En présence d'un décalage, des conteneurs exclusivement en avance sont retardés, de façon à assurer un alignement temporel de l'ensemble des conteneurs. Un pointeur-interpréteur (PI1, PI2), suivi d'une mémoire élastique (ES1, ES2) et d'un pointeur-générateur (PG1, PG2), sont associés à chaque canal (KA1, KA2, ...). Les pointeurs-générateurs sont synchronisés entre eux. Chaque pointeur-générateur est réglé pour commander l'extraction de la mémoire élastique appartenant à son canal. Un gestionnaire de surdébit (OI1) est prévu dans un canal choisi comme canal maître (KA1).
EP00926525A 1999-06-10 2000-05-15 Procede et dispositif pour convertir des flux de donnees virtuellement enchaines en flux de donnees continuellement enchaines Withdrawn EP1186129A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
AT0103499A AT407319B (de) 1999-06-10 1999-06-10 Verfahren und vorrichtung zum umwandeln virtuell verketteter datenströme in kontingent verkettete
AT103499 1999-06-10
PCT/AT2000/000132 WO2000077960A1 (fr) 1999-06-10 2000-05-15 Procede et dispositif pour convertir des flux de donnees virtuellement enchaines en flux de donnees continuellement enchaines

Publications (1)

Publication Number Publication Date
EP1186129A1 true EP1186129A1 (fr) 2002-03-13

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US (1) US6842787B2 (fr)
EP (1) EP1186129A1 (fr)
CN (1) CN1354927A (fr)
AT (1) AT407319B (fr)
AU (1) AU772296B2 (fr)
BR (1) BR0012114A (fr)
WO (1) WO2000077960A1 (fr)

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US6842787B2 (en) 2005-01-11
US20020080812A1 (en) 2002-06-27
CN1354927A (zh) 2002-06-19
AU4522900A (en) 2001-01-02
ATA103499A (de) 2000-06-15
BR0012114A (pt) 2002-05-21
AU772296B2 (en) 2004-04-22
WO2000077960A1 (fr) 2000-12-21
AT407319B (de) 2001-02-26

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