EP1172790A1 - Commande de niveaux de gris sur un écran d'affichage du type matriciel - Google Patents

Commande de niveaux de gris sur un écran d'affichage du type matriciel Download PDF

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Publication number
EP1172790A1
EP1172790A1 EP01114898A EP01114898A EP1172790A1 EP 1172790 A1 EP1172790 A1 EP 1172790A1 EP 01114898 A EP01114898 A EP 01114898A EP 01114898 A EP01114898 A EP 01114898A EP 1172790 A1 EP1172790 A1 EP 1172790A1
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EP
European Patent Office
Prior art keywords
sub
addressing
field
period
panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01114898A
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German (de)
English (en)
Inventor
Sebastien Weitbruch
Carlos Correa
Rainer Zwing
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Deutsche Thomson Brandt GmbH
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Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP00250231A external-priority patent/EP1172787A1/fr
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Priority to EP01114898A priority Critical patent/EP1172790A1/fr
Publication of EP1172790A1 publication Critical patent/EP1172790A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge

Definitions

  • the invention relates to a method for controlling light emission of a matrix display in a display period and an apparatus for carrying out the method. More specifically the invention is closely related to a new addressing concept for matrix displays in which different grey levels for pixels are generated by controlling light emission/reflection/transmission with small pulses in a pulse width modulation form. Such a concept is e.g. used in plasma display panels (PDP) or other display devices where the pixel values control the generation of a corresponding number of small lighting pulses on the display.
  • PDP plasma display panels
  • the Plasma technology now makes it possible to achieve flat colour panels of large size (out of the CRT limitations) and with very limited depth without any viewing angle constraints.
  • a Plasma Display Panel utilizes a matrix array of discharge cells which could only be “ON” or “OFF”. Also unlike a CRT or LCD in which grey levels are expressed by analogue control of the light emission, a PDP controls the grey level by modulating the number of light pulses per frame (sustain pulses). This time-modulation will be integrated by the eye over a period corresponding to the eye time response.
  • an electrical discharge will appear in a gas filled cell, called plasma and the produced UV radiation will excite a colored phosphor which emits the light.
  • a first selective operation called addressing will create a charge in the cell to be lighted.
  • Each plasma cell can be considered as a capacitor which keeps the charge for a long time.
  • a general operation called "sustain" applied during the lighting period will add charges in the cell.
  • the two charges together will build up between two electrodes of the cell a firing voltage. UV radiation is generated which excites the phosphor for light emission.
  • the discharge of the cell is made in a very short period and there remains some charge in the cell. With the next sustain pulse, this charge is increased again up to the firing voltage so that the next discharge will happen and the next light pulse will produced.
  • the cell will be lighted in small pulses.
  • an erase operation will remove all the charges to prepare a new cycle.
  • FIG. 1 The principle structure of a plasma cell in matrix plasma display technologie is shown in Fig. 1.
  • Reference number 10 denotes the face plate made of glass. With reference number 11 a transparent line electrode is denoted.
  • the back plate of the panel is referenced with reference number 12.
  • In the back plate are integrated column electrodes 14 being perpendicular to the line electrodes 11.
  • the inner part of the cells consists of the luminous substance 15 (phosphor) and separators 16 for separating the different coloured phosphors (green 15a), (blue 15b), (red 15c).
  • the UV radiation caused by the discharge is denoted with reference number 17.
  • the light emitted from the green phosphor 15a is indicated with arrows having the reference number 18. From this structure of a PDP it is. clear, that there are three plasma cells necessary, corresponding to the three colour components R,G,B, to produce the colour of a picture element of the displayed picture
  • the gray level of each R,G,B component of a pixel is controlled in a PDP by modulating the number of light pulses per frame period. This time modulation will be integrated by the eye over a period corresponding to the human eye time-response.
  • the frame period will be divided in 8 lighting periods (called sub-fields), each one corresponding to a bit.
  • the number of light pulses for the bit "2" is the double as for the bit "1", and so forth.
  • sub-fields 8 lighting periods
  • the standard principle used to generate this gray modulation is based on the ADS (Address/Display Separated) principle, in which all operations are performed at different time on the whole panel. This principle is illustrated in Fig. 2.
  • Figure 2 represents an example of ADS addressing scheme based on an 8-bit encoding with only one priming period at the beginning of the frame.
  • This is only an example and there are very different sub-field organisations known from the literature with e.g. more sub-fields and different sub-field weights. Often, more sub-fields are used to reduce moving artifacts and priming could be used on more sub-fields to increase the response fidelity.
  • Priming is a separate optional period, where the cells are charged. This charge can lead to a small discharge, i.e. can create background light, which is in principle unwanted. After the priming period an erase period follows for immediately quenching the charge. This is required for the following sub-field periods, where the cells need to be addressed again. So priming is a period which facilitates the following addressing periods, i.e. it improves the efficiency of the writing stage by regularly exciting all cells, simultaneously.
  • each sub-field consists of addressing period, sustain period and erase period.
  • the addressing period length is equal for all sub-fields, also the erase period length.
  • the cells are addressed linewise from line 1 to line N of the display.
  • the erasing period all the cells will be discharged in parallel in one shot, which does not take as much time as for addressing.
  • the example in Fig. 2 shows that all operations addressing, sustaining and erasing are completely separated in time. At one point in time there is one of these operations active for the whole panel. And this reduces the efficiency of these operations. There is a long time between operations which should interact. In addition, there is a strong concentration of energy during the sustain periods which will stress the power supply of the PDP.
  • Tad stands for the addressing time for the complete panel.
  • Ter stands for the erasing time of the complete panel.
  • these are the long time distances which cause a problem.
  • the charge of a written cell can diminish and the cell characteristics may change in general, e.g. resitance, capacity, etc. as explained above.
  • one first idea could be to simply reduce the addressing time by a faster addressing but this would have a negative impact on the response fidelity of the panel.
  • a reduction of the erase time can generate false erasure which appears as flashing pixels in dark areas.
  • a priming and erase period or a sustain period is likewise performed.
  • a spreading of the sustaining period is achieved and the energy output is stretched in the sub-field periods.
  • a constant sustain period after the addressing period as can be seen in Fig. 27 and the corresponding description.
  • ADM address display multiplexing
  • the further improvement to the disclosure of this document consists in the measure that the time distance between the successive addressing periods for the respective sub-panels is set to be constant within a given sub-field but varies from one sub-field to the other.
  • the variation of the time distance between sub-field addressing periods in different sub-fields improves the efficiency of each basic operation to achieve a low-voltage addressing as well as a better response fidelity and a better panel homogeneity.
  • panel homogeneity will permit to increase the speed of some operation (addressing, sustaining) to win more time, which can be used for generating more light.
  • the use of low-power addressing will further reduce the price of the electronics.
  • the energy will be spread during the whole frame and the peak current will be reduced, as well as the stress on all the power components. For these reasons, it will be possible to reduce the cost as well as the power supply complexity, in terms of component count.
  • a plasma cell can only be switched on or off. Therefore, the light generation is being done in small pulses where a plasma cell is switched on.
  • the different colours are produced by modulating the number of small pulses per frame period.
  • a frame period is subdivided in so called sub-fields SF.
  • Each sub-field SF has assigned a specific weight which determines how many light pulses are produced in this sub-field SF.
  • Light generation is controlled by sub-field code words.
  • a sub-field code word is a binary number which controls sub-field activation and inactivation. Each bit being set to 1 activates the corresponding sub-field SF. Each bit being set to 0 inactivates the corresponding sub-field SF. In an activated sub-field SF the assigned number of light pulses will be generated. In an inactivated sub-field there will be no light generation.
  • a sub-field is a period of time in which successively the following is being done with a cell:
  • Fig. 4 the principle of the ADM addressing scheme is shown compared to the ADS addressing scheme.
  • the plasma panel is partitioned in 4 sub-panels corresponding to the numbers 1 to 4.
  • the partition is made in horizontal direction.
  • the first sub-panel comprises the first 120 lines of the display
  • the second sub-panel comprises lines 121 to 240
  • the fourth sub-panel comprises lines 361 to 480.
  • One very good possibility is to make a driver-wise partition, which means that each sub-panel will correspond to a scanning driver. This will enable to work with really optimized scanning drivers (low-voltage driver for addressing... at lower cost) which will reduce the global power consumption of the panel.
  • An example of a driver-wise partition is shown in
  • the PDP has 8 scan drivers for the horizontal addressing lines. This means that in case of 480 lines on the display to each driver 60 lines are assigned.
  • the partition of the panel in sub-panels is correspondingly made, i.e. each sub-panel consists of 60 lines of the panel which can be driven with one scan driver.
  • the data drivers are shown in Fig. 5.
  • the conventional ADS addressing scheme is depicted in the lower part of Fig.4.
  • the subfield organisation shown in Fig. 2 can be used, where the sub-field weights are 1 - 2 - 4 - 8 -16 - 32 - 64 - 128.
  • This is the simplest sub-field organisation and it is pointed out that often some other types of sub-field organisations are used, e.g. with 12 sub-fields where the sub-field weights have a refined gradation.
  • Fig. 4 only the first 6 of the 8 sub-fields are depicted for simplification. All sub-panels are summarized so that the whole panel can be regarded as one part.
  • Each sub-field comprises addressing, sustaining and erasing period.
  • the whole panel will be addressed linewise, i.e. addressing is performed for lines 1 to line 480 continuously. As mentioned above, this takes a relatively long time.
  • the sustaining pulses are fed simultaneously.
  • the sub-fields of a frame period have different weights, different amounts of sustain pulses are produced for the different sub-fields. The amount of sustain pulses increases from the left to the right of the picture.
  • an erase period follows, where all plasma cells of the panel are discharged with a corresponding voltage pulse of different polarity.
  • Fig. 4 it is assumed that no priming period ahead of the first sub-field is present. But this is not mandatory and in another embodiment, one or more priming periods can be part of the sub-field organisation.
  • Fig. 4 shows the addressing scheme related to the first five sub-fields.
  • the sixth sub-field is only partly displayed.
  • a weight unity will correspond to a packet of sustain pulses.
  • the basic concept of this scheme is that, for each sub-field, first, the sub-panel 1 will be addressed, then a group of sustain pulses corresponding to one weight unity will be produced for sub-panel 1, then in the same sub-field, the cells of the second sub-panel 2 will be addressed and the number of sustain pulses for the first weight unity will be produced on this sub-panel, and so on.
  • This weight unity will happen at the same time on sub-panel N+1 as the second weight unity of the same sub-field on sub-panel N and so forth.
  • the sustain period In the first sub-field SF1, the sustain period has only a weight of 1. Therefore, it directly follows the erase period for the respective sub-panel. In the second sub-field SF2, the sustain period has a weight of 2. Therefore, the erase period for the first sub-panel follows after the second shot of sustain periods. The second shot of sustain periods happen in the same time as the first shot for the second sub-panel. In the fourth sub-field SF4 with weight 8, there is a period where the remaining sustain pulses for the weight unities 5 to 8 are produced summarized one after the other on all sub-panels in common. This structure is true also for the sub-fields SF5 to SF8. For all sub-fields there is a small time distance between the addressing periods corresponding to one weight unity except for the first sub-field, where the distance is slightly longer because of the erase period.
  • the most important difference to the ADS addressing scheme is, that the addressing time, for each sub-panel, has been reduced since the number of lines to be addressed per sub-panel has been reduced. This increases a lot the response fidelity and the homogeneity of the panel, reducing the need of priming (better contrast) and enabling a faster addressing in terms of addressing speed. The global gain in time obtained with a higher addressing speed will enable to make more light.
  • Fig. 4 focusses merely on the comparison between ADM and ADS in terms of time delay between scanning and sustaining and the repartition of energy.
  • the use of only 4 sub-panels is not optimized. Nevertheless, it is obvious that there will be less delay between operations in case of ADM and the energy will be better spread over the frame period. This will introduce a gain in terms of response fidelity, as well as in terms of power consumption and power supply optimization.
  • the gain obtained in terms of response fidelity will enable a faster addressing, sparing time that can be used to produce more light (sustain pulses) for contrast improvement.
  • Fig. 6 an improved embodiment of the ADM addressing scheme is shown.
  • the time distance between addressing periods varies. It is not always one weight unity for all sub-fields as in the example of Fig. 4.
  • the time distance of one weight unity is valid only for the first three sub-fields SF1 to SF3.
  • the time distance is two weight unities, for the fifth sub-field SF5 four weight unities, for the sixth sub-field SF6 eight weight unities, for the seventh sub-field SF7 sixteen weight unities and for the eights sub-field SF8 thirtytwo weight unities.
  • the time distance between successive addressing periods remains constant.
  • Fig. 6 shows that, in case of the second ADM scheme, the energy input and output will be better spread over the frame period, especially for the sub-fields with higher weights. This allows for a better optimization of the power supply in terms of component count and component costs.
  • the above picture describes a possible implementation.
  • the control block selects the appropriate sub-panel that should be primed / addressed / erased. When a given sub-panel is selected, the required frame memory address is evaluated, in order to allow a direct memory access to the corresponding video contents. At the same time the control block generates all prime, erase, scan and sustain pulses in the order required by either of the proposed ADM sequences.
  • FIG. 7 a circuit implementation of the invention is illustrated.
  • Input R,G,B video data is forwarded to a sub-field coding unit 20.
  • the sub-field code words are forwarded to a memory 21 separately for the different colour components R,G,B.
  • This memory preferably has a capacity of two frame memories. This is recommendable due to the plasma driving process.
  • the plasma display panel is driven in sub-fields as explained above and therefore for every pixel only one bit (in fact three bits because of the three colour components) needs to be read out of this memory per sub-field.
  • data needs to be written in the memory.
  • the read bits of the sub-field code words are collected in a serial parallel conversion unit 22 for a whole line of the PDP. As there are e.g. 854 pixel in one line, this means 2962 sub-field coding bits needs to be read for each line per sub-field period. These bits are input in the shift registers of the serial parallel conversion unit 22.
  • the sub-field code words are stored in memory unit 21. Reading and writing from and to this memory unit is also controlled by the external control unit 24.
  • the control unit 24 controls writing and reading from and to the memory 21. Also it controls the sub-field coding process and the serial parallel conversion. Further it generates all scan, sustain and erase pulses for PDP control. It receives horizontal and vertical synchronising signals for reference timing.
  • the invention can be used in particular in PDPs.
  • Plasma displays are currently used in consumer electronics, e.g. for TV sets, and also as a monitor for computers.
  • use of the invention is also appropriate for matrix displays where the light emission is also controlled with small pulse in sub-fields, i.e. where the PWM principle is used for controlling light emission.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP01114898A 2000-07-13 2001-07-02 Commande de niveaux de gris sur un écran d'affichage du type matriciel Withdrawn EP1172790A1 (fr)

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EP01114898A EP1172790A1 (fr) 2000-07-13 2001-07-02 Commande de niveaux de gris sur un écran d'affichage du type matriciel

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP00250231 2000-07-13
EP00250231A EP1172787A1 (fr) 2000-07-13 2000-07-13 Commande de niveaux de gris sur un écran d'affichage du type matriciel
EP01114898A EP1172790A1 (fr) 2000-07-13 2001-07-02 Commande de niveaux de gris sur un écran d'affichage du type matriciel

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1650734A1 (fr) 2004-10-19 2006-04-26 Samsung SDI Co., Ltd. Dispositf d'affichage et son procédé de commande
EP1684325A2 (fr) * 2005-01-19 2006-07-26 Pioneer Corporation Dispositif d'affichage à plasma

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903245A (en) * 1993-11-29 1999-05-11 Nec Corporation Method of driving plasma display panel having improved operational margin
DE19850633A1 (de) * 1998-03-13 1999-09-16 Lg Semicon Co Ltd Steuerverfahren für Wechselstrom-Plasmabildschirm
US6057815A (en) * 1996-11-19 2000-05-02 Nec Corporation Driver circuit for AC-memory plasma display panel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903245A (en) * 1993-11-29 1999-05-11 Nec Corporation Method of driving plasma display panel having improved operational margin
US6057815A (en) * 1996-11-19 2000-05-02 Nec Corporation Driver circuit for AC-memory plasma display panel
DE19850633A1 (de) * 1998-03-13 1999-09-16 Lg Semicon Co Ltd Steuerverfahren für Wechselstrom-Plasmabildschirm

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1650734A1 (fr) 2004-10-19 2006-04-26 Samsung SDI Co., Ltd. Dispositf d'affichage et son procédé de commande
CN100463024C (zh) * 2004-10-19 2009-02-18 三星Sdi株式会社 显示装置及其驱动方法
EP1684325A2 (fr) * 2005-01-19 2006-07-26 Pioneer Corporation Dispositif d'affichage à plasma

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