Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
  • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
  • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Definitions

• the present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for etching a semiconductor chip.
• One common method for processing semiconductor wafers includes forming and modifying structure on the wafer using an etch process.
• One particular etching application involves the formation of structure having a side wall profile, such as a gate electrode. Obtaining profiles near 90° is important for achieving desired performance levels from the chip. However, obtaining such a profile is difficult in many applications, such as in the formation of deep sub-micron gate structures having a thin gate oxide. When etching a deep sub-micron gate structure in a process such as an amorphous Si or poly-Si gate etch process, it is important to avoid etching down to the thin gate oxide.
• One such method for etching a deep sub-micron gate structure involves the application of a selective high Si/SiO 2 etch process that does not etch down to the thin gate oxide.
• the high Si/SiO 2 etch is deficient, however, in that the resulting profile from the etch is often tapered, which can result in a loss in performance of the structure.
• Another method used in conjunction with the high Si/SiO 2 etch is the application of a high Cl 2 flow for improving the tapering profiles.
• the addition of the high Cl 2 flow can improve the profile, it has drawbacks including the degradation of the Si/SiO 2 etch selectivity. For instance, the addition of the high Cl 2 flow can cause micro- trenching problems as well as severe etch side wall roughness.
• the present invention is directed to a method for manufacturing a semiconductor device involving the formation of structure, such as a gate electrode, having an about vertical profile without degrading material below the structure.
• structure such as a gate electrode
• the present invention is exemplified in a number of implementations and applications, some of which are summarized below.
• a semiconductor chip having a substrate formed over a thin oxide is processed.
• a plasma is generated from an etch gas and an inert gas and is supplied to the chip, wherein the etch gas chemistry, the plasma power, and the pressure at which the plasma is applied are sufficient to maintain a high selectivity to the thin oxide.
• the inert gas is supplied at a rate that is sufficient to achieve an about vertical side wall profile of the structure while maintaining the high etch selectivity.
• the semiconductor chip is etched and a structure is formed using the substrate.
• a semiconductor chip includes a structure having at least one side wall that is about vertical and an underlying thin oxide.
• the structure is formed by patterning a mask over the structure and etching the chip with a highly selective etch gas an in the presence of an inert gas.
• the inert gas facilitates the formation of about vertical side walls while not degrading the selectivity of the etch gas, thereby inhibiting the etching of the thin oxide.
• FIG. 1 is a semiconductor chip having a substrate formed over a thin oxide, for use in connection with an example embodiment of the present invention
• FIG. 2 shows the semiconductor chip of FIG. 1 having an etch gas and inert gas supplied to the substrate, according to an example embodiment of the present invention
• FIG. 3 shows the semiconductor chip of FIG. 2, having undergone an etch process, according to another example embodiment of the present invention.
• FIG. 4 is a flow diagram for processing a semiconductor chip, according to another example embodiment of the present invention.
• the present invention is believed to be applicable for a variety of different types of semiconductor devices, and the invention has been found to be particularly suited for devices requiring or benefiting from the formation of structure having about vertical side walls. While the present invention is not necessarily limited to such devices, various aspects of the invention may be appreciated through a discussion of various examples using this context.
• an inert gas such as helium
• a conventional etch gas as it is supplied for etching a semiconductor chip substrate
• the inert gas improves the profile while maintaining good etch selectivity to material such as oxide located in the chip.
• FIG. 1 shows such a chip 100 having a substrate 120 formed over a thin gate oxide layer 110, and a mask 130 formed over a portion 140 of the substrate 120.
• the substrate may, for example, include gate material such as poly-silicon or amorphous silicon.
• the substrate includes an anti-reflective coating over the substrate 120.
• FIG. 2 shows the chip 100 of FIG. 1 being etched.
• a plasma 230 is generated from an etch gas 210 and an inert gas 220, and is then supplied to the substrate 120.
• the etch gas 220 may, for example, include a plurality of gases.
• the etch and inert gas supplies, the plasma power, and the etch pressure at which the plasma is supplied are sufficient to achieve about vertical side wall profiles 250 of the masked portion
• an etch pressure of between about 5 - 100 mTorr, a plasma source power (for controlling the plasma density) of between about 50-400 W, and a plasma bias power (for controlling the energy supplied to the ions) of between about 10-200 W provide conditions adequate for achieving the about vertical side walls.
• the mask 130 masks the portion 140 of the substrate, and the remaining substrate is etched, as shown in FIG. 3.
• the resulting structure 340 formed from the masked portion 140 of the substrate has about vertical side walls 350.
• the selectivity of the etch gas to the thin oxide layer 110, while in the presence of the inert gas is about infinite. The infinite selectivity permits the formation of the structure 340 without etching the thin oxide layer 110, thereby reducing the harmful effects of problems, such as microtrenching, associated with etch processes that are not as highly selective.
• the inert gas can also improve the resulting structure by removing depositions on the side walls.
• the etch and inert gas supply to the chip can be accomplished in various manners.
• the chip 100 is placed in an etch chamber, and the gases are supplied to the chip via a supply to the etch chamber.
• the etch gas 210 may include, for example, a typical etch gas chemistry used in highly selective Si/SiO 2 etch processes.
• Helium can be supplied as the inert gas and used with the highly selective Si/Si0 2 etch chemistry for etching the chip.
• the helium is supplied at a volumetric flow rate of between about 25- 500 seem.
• the helium is supplied at a flow rate of at least about 500 seem.
• the inert gas and the etch gas are mixed prior to their introduction to the chip.
• the side walls 350 of the resulting structure 340 are shown to be close to vertical.
• the resulting side walls have an included angle ⁇ of at least about 85°, and in another the included angle ⁇ is about 90°.
• This resulting structure 340 is useful because vertical side walls exhibit improved performance over side walls having a tapered profile.
• FIGs. 1-3 show one structure 340, it should be noted that a plurality of such structures may be formed on the chip.
• the chip may be part of a semiconductor wafer having a plurality of chips, some or all of which having a structure formed in a similar manner.
• the structure 340 in FIG. 3 may include a gate used in connection with a transistor.
• the thin oxide 110 is a gate oxide
• the chip 100 includes structure such as source and drain regions near the gate.
• the present invention is particularly advantageous for the formation of deep sub-micron gate structure. For example, in one implementation a gate having a width of less than about 0.20 microns is formed. In another implementation a gate having a width of about 0.15 microns is formed. In still another implementation, a gate having a width of less than about 0.15 microns is formed.
• FIG. 4 is a flow diagram of an example process for manufacturing a semiconductor chip, according to another example embodiment of the present invention.
• a thin oxide layer is formed over a semiconductor chip at block 410.
• a substrate such as gate material including poly- silicon or amorphous silicon, is formed over the oxide at block 420.
• a mask material is patterned over the substrate at block 430, and the chip is then placed in an etch chamber at block 440.
• the mask may be patterned, for example, for forming one or more gate structures on the chip.
• a vacuum is drawn on the chamber at block 450, and an etch gas and an inert gas are supplied to the etch chamber and a plasma is generated at block 460.
• the etch pressure is held about constant during the addition of the inert gas.
• the plasma anisotropically etches the unmasked substrate in a manner that forms about vertical side wall profiles on the masked structures that are not etched.
• the unmasked substrate is etched while etching little or none of the thin oxide layer.
• the mask material is removed from the chip at block 470.
• the chip may then be annealed or further processed in other manners.
• a semiconductor chip is manufactured.
• the chip includes a gate structure having at least one side wall that is about vertical and an underlying thin oxide.
• the gate structure is formed by patterning a mask over the structure and etching the structure with a highly selective etch gas while in the presence of an inert gas.
• the inert gas facilitates the formation of about vertical side walls while not degrading the selectivity of the etch gas.
• the resulting gate profile has side walls that are about vertical, and the thin oxide layer is not etched due to the use and maintenance of the highly selective etch process.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Plasma & Fusion (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• General Chemical & Material Sciences (AREA)
• Drying Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2000
  • 2000-12-22 KR KR1020017011029A patent/KR20010112294A/ko not_active Application Discontinuation
  • 2000-12-22 WO PCT/US2000/035131 patent/WO2001050511A1/en not_active Application Discontinuation
  • 2000-12-22 EP EP00986720A patent/EP1166346A1/de not_active Withdrawn
  • 2000-12-22 JP JP2001550791A patent/JP2003519914A/ja active Pending

Non-Patent Citations (1)

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