EP1166341A1 - A reactive ion etching process - Google Patents
A reactive ion etching processInfo
- Publication number
- EP1166341A1 EP1166341A1 EP00914290A EP00914290A EP1166341A1 EP 1166341 A1 EP1166341 A1 EP 1166341A1 EP 00914290 A EP00914290 A EP 00914290A EP 00914290 A EP00914290 A EP 00914290A EP 1166341 A1 EP1166341 A1 EP 1166341A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- waveguide
- rie
- seem
- fabricating
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
Abstract
A reactive ion etching process controls the flow rate of at least one etchant gas used in said reactive ion etching process, the pressure of said at least one etchant gas; and the r.f. power used in said reactive ion etching process. The parameters of flow rate, pressure and r.f. power are selected to obtain a desired etch rate and/or a desired level of material re-deposition in the reactive ion etching process.
Description
A REACTIVE ION ETCHING PROCESS
FIELD OF THE INVENTION
The invention relates to a reactive ion etching (RIE) process, in particular to a RIE process which can be used in the fabrication of an optical waveguide with low surface and sidewall roughness and which has low levels of material re-deposition.
BACKGROUND OF THE INVENTION
There is an increasing demand in industries such as telecommunications and bioelectronics for planar lightwave circuit components. Such components include large scale silica glass film waveguides whose planar dimensions are normally in the range 4μm to 8 μm but which can exceed lOμm. This differs from devices which are fabricated for the semiconductor industry, where etch depths are small (<2μm) and where the amount of etched material is typically less than 5%, such that the "loading effect", or amount of material redeposition, is reduced. The deep etching of the silica glass films during the fabrication of such
waveguides by dry etch mask techniques has several known disadvantages .
Large scale silica waveguides can alternatively be fabricated using a combination of flame hydrolysis deposition (FHD) and RIE processes. It is desirable for the RIE process to have a high FHD glass etch rate, high mask selectivity and to cause minimal damage to the waveguide core side walls during the etching process.
RIE processes have several disadvantages known in the prior art. RIE generally depends on ion assisted chemical reactions forming volatile species which are subsequently removed during the waveguide fabrication process. However, it is desirable in certain applications for the waveguides to be doped with rare earth or heavy metal species which form involatile products during the RIE process. These involatile products enable surface imperfections or "grass" to develop on the etched surfaces surrounding the waveguide.
By combining the RIE and FHD processes, it is possible to fabricate rare earth channel waveguides with relatively smooth etched surfaces. In particular, the RIE process can be controlled so that certain parameters directly or indirectly affect the etchant speed and the amount of ion re-deposition which occurs during the RIE processing stage of fabricating an optical waveguide.
In particular, in the deep etching of flame hydrolysis deposited silica glass, for example when 4 μm or more of material is to be removed, it is highly desirable to achieve a fast etch speed. A problem arises in that
such fast etch speeds are known in the prior art to affect the integrity of the mask used to define the waveguide core area. Moreover, fast etch speeds often result in damage to the etched side walls of the waveguide .
The invention seeks to provide an RIE process which achieves a fast etch speed which preserves the integrity of the mask used to define the waveguide core area and which also provides high quality waveguide core side walls. It is known that the choice of etchant gas, which may be a mixture of actively etching gas(es) with dilutant or process gas(es), can accelerate the rate at which material is etched but may at the same time exacerbate the amount the etchant gas undercuts the mask.
Suitable ranges of values for the RIE process parameters are provided according to the invention to enable the RIE process to produce heavy metal or rare earth doped channel waveguides. The waveguide cores are formed with a desirably low level of surface roughness and are etched at a desirable speed with minimal damage to the waveguide side walls. A range of values for the pressure of an etchant gas, the rate at which the etchant gas is supplied, and the radio frequency (r.f) power density used in the RIE process are given.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a reactive ion etching process comprising the steps of: controlling the flow rate of at least one etchant gas used in said reactive ion etching process; controlling the pressure of said at least one
etchant gas ; and controlling the r.f. power density used in said reactive ion etching process, wherein the parameters of flow rate, pressure and r.f. power are selected to obtain a desired etch rate and/or to reduce the level of ion dopant material redeposited in the reactive ion etching process .
DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which :-
Figs. 1A to IC show scanned electron micrographs of a erbium doped phosphosilicate waveguide with varying levels of surface roughness.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to the drawings, Figs .1A to IC illustrate scanned electron microscope images of erbium doped phosphosilicate waveguides formed by a method of fabricating an optical waveguide which incorporates the method of optimising the reactive ion etching (RIE) process to achieve a desired etch rate and/or level of etched surface roughness.
Referring now to Fig. 1A, an optical waveguide 1 is shown which displays a moderate number of surface defects 2. The RIE process in the fabrication of the optical waveguide has been controlled to ensure a rapid etch rate to the detriment of the smoothness of the waveguide surface.
Referring now to Fig. IB, an optical waveguide 3 is shown which displays a fewer surface defects 4, than shown in Fig. 1A. The RIE process in the fabrication of the optical waveguide has been controlled to slightly compromise the rapidity of the etch rate to give a lower degree of roughness of the waveguide surface .
Referring now to Fig. IC, an optical waveguide 5 is shown which displays a minimal number of surface defects 6. The RIE process in the fabrication of the optical waveguide has been controlled to ensure the roughness of the waveguide surface is been reduced to a minimum to the detriment of the etch rate.
In a preferred embodiment of the invention, a method of fabricating an optical waveguide includes the following stages : -
(1) Forming at least one intermediate layer on an underlying substrate and optionally doping said layer;
(2) Forming at least one core layer on the underlying intermediate layer and optionally doping said core layer;
(3) Forming a waveguide core from the core layer (s) by masking the uppermost said core layer and by using a reactive ion etching (RIE) process to remove the unwanted portions of said core layer (s) .
(4) Forming at least one cladding layer to embed the waveguide core and optionally doping said cladding layer.
In the preferred embodiment, any suitably appropriate process can be used to perform each of stages one, two and four. The masking step of stage three can be performed conventionally but the reactive ion etching process step of stage three is performed according to the invention.
The preferred embodiment will now be described in more detail. An intermediate layer, for example a buffer layer and an upper intermediate layer deposited thereon, is deposited on a substrate, for example a silicon substrate using, for example, a flame hydrolysis deposition (FHD) process.
The buffer layer comprises silica, but can be any thermally oxidised layer of the substrate. The upper intermediate layer comprises silica, and is doped with selected dopant ions which induce certain desired properties in the upper intermediate layer. The upper intermediate layer is then consolidated, for example, in an electrical furnace or by an FHD burner, before any subsequent layers are deposited.
In the method of fabricating the optical waveguide, after the upper intermediate layer is consolidated, a core layer is subsequently deposited using an FHD process. The core layer comprises silica, and is doped with dopant ions which induce certain desired properties in the core layer. The core layer is then consolidated, for example in an electrical furnace or by an FHD burner, at least partially before any subsequent layers are deposited.
The normal FHD apparatus is modified so that the core layer can be aerosol doped. An additional feed is provided on the FHD apparatus supplies aerosol droplets
of the dopant ions. High concentrations of core layer dopant ions, for example concentrations exceeding 0.5wt%, but more typically in the range 0.2wt% to 2 wt%, of rare earth ions or heavy metal ions can be introduced during the deposition of the core layers by using such an aerosol doping technique .
The waveguide core is then formed from the core layer by masking the core layer and etching away the unwanted portion of the core layer. Subsequently, another cladding layer is deposited and consolidated similarly to the first cladding layer.
Many variations in the stages of fabricating an optical waveguide are possible which differ from those described in the preferred embodiment. For example, more than one intermediate, core and/or cladding layers can be deposited at each stage. The intermediate, core and cladding layers may be only partially consolidated after they are deposited and full consolidation can be achieved by subsequent thermal treatment, for example, when a subsequently deposited layer is being consolidated. Obviously, the choice of fabrication process depends to an extent on the deposition and consolidation temperatures of each layer.
The waveguide core is formed from the core layers by performing a suitable masking process on the uppermost core layer so that a mask portion covers the waveguide area to be retained during the RIE process. The RIE process parameters are selected to enable the desired etch rate to be achieved with a minimal amount of erosion of the mask portion and with a minimal amount of undercut under the mask portion. The RIE etchant gas is thus selected to exhibit a high degree of selectivity between the mask layer and the waveguide
layers to be etched.
The mask used is preferably metal, for example, nichrome (NiCr) or alternatively is Ni , Ti-Ni, or Ti:NiCr. Other suitable masks include amorphous silicon and polysilicon. The mask is formed by depositing a mask layer, i.e. a layer of masking material, on the uppermost core layer. The metal masks may be deposited, for example, by thermal evaporation, electron beam evaporation or sputtering. Amorphous silicon masks may be deposited, for example, by plasma enhanced chemical vapour deposition (PECVD) , and silicon masks may be deposited, for example, by low pressure chemical vapour deposition (LPCVD) .
A layer of resist, for example, photo-resist, is then formed on top of the mask layer and is patterned using standard photo- lithographic techniques which remove the resist. The exposed unwanted mask areas are then etched away and the wanted mask portion defining the waveguide is finally left covered by the mask and resist layers.
Preferably, the metal mask is deposited by using an evaporator. To prevent mask erosion during the etchant process, a mask thickness of 100 nm was used which lies in a suitable range of lOnm to 800nm. A suitable photoresist is SHIPLEY™ S1818 which was postbaked at 120°C. Alternatively, a 1.8μm thick photoresist can be alone as a dry etch mask.
To achieve the desired etch rates and waveguide wall surface roughness, the method of controlling the RIE process selectively controls certain selected parameters, for example, the pressures of the etchant gases used, the flow rate of the etchant gas, and the
r.f. power density used. It is desirable for the etchant gas to offer a high etch rate yet be highly selective between the mask and core material. If the selectivity is low, the side wall quality is reduced.
The etchant gas is a ideally a fluorine based etch gas and/or at least one other gas, for example, a dilutant or a process gas, e.g. 02. Fluorine based gases can be used, for example, to etch both metal and silicon based masks or alternatively, chlorine bases gases can be used to etch silicon based masks. The process gas is selected, for example, so that the amount of polymer formation during the RIE process stage of fabricating a waveguide is increased, which increases the anisotropy of the etching process and so improves the vertical orientation of the side-walls of the waveguide channel which are etched.
These selected RIE parameters affect the etch rate of the RIE process and the amount of material which is redeposited during the RIE processing stage. The amount of re-deposition which occurs during the RIE processing stage directly and/or indirectly determines the level of surface roughness of the etched surfaces formed.
In the preferred embodiment, the etchant gas includes a process gas, for example 02, and a fluorine based chemical, for example, CHF3. Selecting suitable values for the RIE parameters with this etchant gas enables the RIE process to form waveguide cores which possess a desirably low level of surface roughness and/or which are formed at a desirable etch rate. The parameters varied are the fluorine based etchant gas flow rate, the process gas flow rate, the etchant gas pressure and the r.f. power density. Selected values of these RIE
parameters and the RIE etchant speeds and levels of waveguide core surface roughness obtained by the RIE process using these parameters are detailed in Table 1A shown overleaf .
A level setting for the RIE process combines selected values of the RIE parameters. Three level settings are given in Table IB shown below: -
Table IB The values set for each of the RIE parameters for each level setting of the RIE process.
The etch rate average for an CHF3 flow of 5 seem (runs 1,2, and 3) is given by the average of El (1.85μm/hr), E2 (5.42μm/hr) and E3 (13. llμm/hr) . This is denoted as EC1, and is 6.79 μm/hr. Similarly, the etch rate average for CHF3 flow setting 2, 25 seem, is given by the
Table 1 The CHF3 gas flow rate, the 02 gas flow rate, etchant gas pressure and r.f. power density and the resulting etch rate of the RIE process and the roughness
of the waveguide surface etched by the RIE process.
average of the etch rates of experiments 4, 5 and 6 and is 4.16 μm/hr. The etch rate average for CHF3 flow level setting 3 is EC3 = 4.57 μm/hr.
The average etch rates obtained by the RIE process for each level setting of the RIE process are shown overleaf in Table 2A, and the average surface roughness of the waveguides formed by each level setting are shown in Table 2B .
Each of the first three rows in Table 2A corresponds to a different level setting, i.e., to a different set of parameters selected to control the RIE process . The final row gives the difference between the maximum and minimum etch rates in each column.
In table 2A, the etch rate difference for the CHF3 flow parameter values selected, ΔEC, is EC1-EC2, or 2.63 μm/hr. Similarly, the etch rate difference for the pressure parameter values selected is given by EPr3 - EPrl, or 2.91 μm/hr.
The maximum etch rate for each of the RIE parameter values selected occurs at the smallest CHF3 flow value, greatest 02 flow value, highest pressure value and highest power value, i.e., by the values Ecl, E03, EPr3, EPo3. The RIE process is optimized for maximum etch rate by setting the RIE parameters to these values.
Table 2B shows the average surface roughness of the optical waveguide formed by the RIE process. Each of the first three rows corresponds to a different level setting: i.e., to a different set of parameters selected to control the RIE process. The final row gives the difference between the maximum and minimum surface roughness obtained in each column.
Table 2A
Ta e B
Table 2B shows that RIE process produces minimal roughness for the greatest CHF3 flow, medium 02 flow, smallest pressure and smallest power (EC3, E02 , EPrl, EPol) .
The following settings for the RIE parameters: a CHF3 flow rate of 25 seem, an 02 flow rate of 5 seem, a pressure of 20 mTorr, and a r.f. power density of 0.6W/cm2 give an etch rate of 5.2 μm/hr. These settings give a desirably low level of re-deposition and a desirably low level of surface roughness. Fig. IC displays a scanned electron microscope image of an erbium doped phosphosilicate waveguide 5 fabricated using these RIE parameter values.
To achieve a desirably smooth waveguide surface the following ranges of RIE parameter values are suitable: a CHF3 flow rate of 5 to 75 seem; an 02 flow rate of 0 to 15 seem, a pressure of 5 to 30 mTorr, and a r.f. power density of 0.06 to 0.64 Wcm"2. The selection of parameter values in these ranges gives RIE etch rates of between 1.8 and 1.3 μm/hr and surface roughness levels of between 5 and 100 nm.
In another embodiment, the RIE process is controlled to give an optimum etch rate which depends strongly on the pressure and power by selecting the following parameter values: a CHF3 carrier gas flow rate of 45 seem, an 02 flow rate of 5 seem, a pressure of 20 mTorr, and a r.f. power density of 0.6 Wcm"2. Fig. IB illustrates a scanned electron microscope image of an erbium doped phosphosilicate waveguide 5 formed according to this embodiment.
To achieve a desirably high etch rate the following ranges of parameter values are suitable: a CHF3 flow
rate of 5 to 45 seem; an 02 flow rate of 5 to 15 seem, a pressure of 80 to 120 mTorr, and a r.f. power density of 0.54 to 0.95 W/cm2. The selection of parameter values in these ranges gives RIE etch rates of between 8μm and 13μm/hr and surface roughness levels of between 100 and 200 nm.
Although 02 and CHF3 form the etchant gas used in the RIE process in the preferred embodiment of the invention, other fluoride based etchant gases can be used for etching silica type material such as CF4 , C2F6/ SF6, etc. Process gases such as Ar, CH4 , etc can also be incorporated into the etchant . The RIE processing stage can be generally tailored for each etchant gas mix to produce optimal etch rates by using high flow rate, low pressure and high power parameters.
Alternatively, the RIE processing stage can be tailored to reduce the amount of ion deposition and thus the level of surface roughness of the optical waveguide formed by the method. Desirably low levels of surface roughness of silicon based waveguides of between 5 nm to 100 nm can be achieved.
Waveguides which are fabricated using the invention display further desired properties, for example substantially vertical (90°) sidewalls.
By the selection of appropriate values for the pressure and flow rates of the etchant gases, the RIE rate can exceed 115 nm/ in. An etch rate in excess of 115 nm/min was achieved using an etchant gas flow rate of ~45sccm, a low etchant gas pressure of -20 mTorr and by using a high r.f. power density of 0.6 Wcm"2. The resulting waveguide has a side wall anisotropy of >89° and a relatively low surface roughness of 19nm.
While several embodiments of the present invention have been described and illustrated, it will be apparent to those skilled in the art once given this disclosure that various modifications, changes, improvements and variations may be made without departing from the spirit or scope of this invention.
The text of the accompanying claims and abstract are hereby declared to be incorporated into the text of the description.
Claims
1. A reactive ion etching (RIE) process comprising the steps of : controlling the flow rate of at least one etchant gas used in said reactive ion etching process; controlling the pressure of said at least one etchant gas; and controlling the r.f. power density used in said reactive ion etching process, wherein the parameters of flow rate, pressure and r.f. power density are selected to obtain a desired etch rate and/or a desired level of material re-deposition in the reactive ion etching process.
2. A RIE process as claimed in Claim 1, wherein the etchant gas comprises a first etchant gas and at least one other etchant gas and/or process gas.
3. A RIE process as claimed in either Claim 1 or Claim 2, wherein the flow rate of the first etchant gas is controlled such that its parameter ranges from 5 seem to 45 seem.
4. A RIE process as claimed in any either Claim 2 or Claim 3, wherein the etchant gas further includes a process gas whose flow rate is controlled such that its parameter ranges from 0 seem to 10 seem.
5. A RIE process as claimed in any preceding claim, wherein the pressure of the etchant gas is controlled such that its parameter ranges from 20 mTorr to 100 mTorr.
6. A RIE process as claimed in any preceding claim, wherein the r.f. power density is controlled such that its parameter ranges from 0.16 Wcm"2 to 0.6 Wcm"2.
7. A RIE process as claimed in any preceding claim, wherein the etchant gas is a fluorine based gas.
8. A RIE process as claimed in Claim 7, wherein the fluorine based gas is CHF3 and/or C2F6 and/or SF6 and/or CF. and/or CBrF5.
9. A RIE process as claimed in any of claims 2 to 8, wherein the said process gas is 02, and/or Ar, and/or CH3, and/or CH4 , and/or C2H4.
10. A RIE process as claimed in any one of claims 2 to 9, wherein the first etchant gas flow rate ranges from 5 seem to 75 seem; the process gas flow rate ranges from 0 seem to 15 seem; the etchant gas pressure ranges from 5 mTorr to 30 mTorr; and the r.f. power density ranges from 0.06 Wcm"2 to 0.64 Wcm"2.
11. A RIE process as claimed in any preceding claim, wherein the etchant rate of the RIE process is greater than 115 nm/min.
12. A RIE process as claimed in any one of claims 2 to 9, wherein the first etchant gas flow rate ranges from 5 seem to 45 seem; the second process gas flow rate ranges from 5 seem to 15 seem; the etchant gas pressure ranges from 80 mTorr to 120 mTorr; and the r.f. power density ranges from 0.54 Wcm"2 to 0.95 Wcm"2.
13. A method of fabricating a waveguide comprising the steps of: forming an intermediate layer upon a substrate; forming a core layer on the intermediate layer; forming a waveguide core from the core layer; and forming a cladding layer to embed the waveguide core ; wherein the step of forming the waveguide core comprises the steps of: forming a mask on the core layer; and removing an unwanted portion of the core layer leaving the waveguide core using a reactive ion etching process as claimed in any preceding claim.
14. A method of fabricating a waveguide as claimed in claim 13, wherein the RIE process etches material to a depth greater than 4 μm.
15. A method of fabricating a waveguide as claimed in either Claim 13 or Claim 14, wherein the RIE process fabricates a waveguide core with a planar dimension greater than 20μm.
16. A method of fabricating a waveguide as claimed in any of Claims 13 to 15, wherein the etched surfaces of the waveguide core have a surface roughness of 5 nm to lOOn .
17. A method of fabricating a waveguide as claimed in any of claims 13 to 16, wherein the RIE etchant and/or process gas is selected to optimise the selectivity between the mask and the core layer, and the range of values for the RIE parameters are selected accordingly.
18. A method of fabricating a waveguide as claimed in claim 14, wherein the RIE process etches material to a depth greater than 10 μm.
19. A method of fabricating a waveguide as claimed in any of Claims 13 to 18 wherein the mask used is formed by depositing a layer of Ni , Ti:Ni, Ti:NiCr, amorphous silicon and/or polysilicon.
20. A method of fabricating a waveguide as claimed in claim 19, wherein the mask layer is formed by either thermal evaporation, or electron beam evaporation, or sputtering, or plasma enhanced chemical vapour deposition, or low pressure chemical vapour deposition.
21. A method of fabricating a waveguide as claimed in any of Claims 13 to 20, wherein at least one layer of the waveguide is doped with rare earth ions.
22. A method of fabricating a waveguide as claimed in claim 21, wherein the dopant concentration of the rare earth ions is substantially greater than or equal to 0.5 wt%.
23. A method of fabricating a waveguide as claimed in any of Claims 13 to 22, wherein the amount of polymer formation undergone by the etchant gas during the reactive ion etching process increases the anisotropy of the etching process such that substantially vertical waveguide side-walls are etched by the etching process.
24. A reactive ion etching process substantially as described herein and with reference to the accompanying drawings.
25. A method of fabricating a waveguide substantially as described herein and with reference to the accompanying drawings.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9907302A GB2348399A (en) | 1999-03-31 | 1999-03-31 | Reactive ion etching with control of etch gas flow rate, pressure and rf power |
GB9907302 | 1999-03-31 | ||
PCT/GB2000/001231 WO2000059020A1 (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
Publications (1)
Publication Number | Publication Date |
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EP1166341A1 true EP1166341A1 (en) | 2002-01-02 |
Family
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Family Applications (1)
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EP00914290A Withdrawn EP1166341A1 (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
Country Status (4)
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EP (1) | EP1166341A1 (en) |
AU (1) | AU3568500A (en) |
GB (2) | GB2348399A (en) |
WO (1) | WO2000059020A1 (en) |
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US20020158047A1 (en) * | 2001-04-27 | 2002-10-31 | Yiqiong Wang | Formation of an optical component having smooth sidewalls |
CN1244828C (en) * | 2002-02-06 | 2006-03-08 | 松下电器产业株式会社 | Optical waveguide manufacturing method |
US8735797B2 (en) | 2009-12-08 | 2014-05-27 | Zena Technologies, Inc. | Nanowire photo-detector grown on a back-side illuminated image sensor |
US9000353B2 (en) | 2010-06-22 | 2015-04-07 | President And Fellows Of Harvard College | Light absorption and filtering properties of vertically oriented semiconductor nano wires |
US8890271B2 (en) | 2010-06-30 | 2014-11-18 | Zena Technologies, Inc. | Silicon nitride light pipes for image sensors |
US8299472B2 (en) | 2009-12-08 | 2012-10-30 | Young-June Yu | Active pixel sensor with nanowire structured photodetectors |
US9515218B2 (en) | 2008-09-04 | 2016-12-06 | Zena Technologies, Inc. | Vertical pillar structured photovoltaic devices with mirrors and optical claddings |
US9299866B2 (en) | 2010-12-30 | 2016-03-29 | Zena Technologies, Inc. | Nanowire array based solar energy harvesting device |
US9406709B2 (en) | 2010-06-22 | 2016-08-02 | President And Fellows Of Harvard College | Methods for fabricating and using nanowires |
US9082673B2 (en) | 2009-10-05 | 2015-07-14 | Zena Technologies, Inc. | Passivated upstanding nanostructures and methods of making the same |
US8866065B2 (en) | 2010-12-13 | 2014-10-21 | Zena Technologies, Inc. | Nanowire arrays comprising fluorescent nanowires |
US9478685B2 (en) | 2014-06-23 | 2016-10-25 | Zena Technologies, Inc. | Vertical pillar structured infrared detector and fabrication method for the same |
US8229255B2 (en) | 2008-09-04 | 2012-07-24 | Zena Technologies, Inc. | Optical waveguides in image sensors |
US8835831B2 (en) | 2010-06-22 | 2014-09-16 | Zena Technologies, Inc. | Polarized light detecting device and fabrication methods of the same |
US8546742B2 (en) | 2009-06-04 | 2013-10-01 | Zena Technologies, Inc. | Array of nanowires in a single cavity with anti-reflective coating on substrate |
US8791470B2 (en) | 2009-10-05 | 2014-07-29 | Zena Technologies, Inc. | Nano structured LEDs |
US8269985B2 (en) | 2009-05-26 | 2012-09-18 | Zena Technologies, Inc. | Determination of optimal diameters for nanowires |
US9343490B2 (en) | 2013-08-09 | 2016-05-17 | Zena Technologies, Inc. | Nanowire structured color filter arrays and fabrication method of the same |
US8889455B2 (en) | 2009-12-08 | 2014-11-18 | Zena Technologies, Inc. | Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor |
US8519379B2 (en) | 2009-12-08 | 2013-08-27 | Zena Technologies, Inc. | Nanowire structured photodiode with a surrounding epitaxially grown P or N layer |
US8748799B2 (en) | 2010-12-14 | 2014-06-10 | Zena Technologies, Inc. | Full color single pixel including doublet or quadruplet si nanowires for image sensors |
US8274039B2 (en) | 2008-11-13 | 2012-09-25 | Zena Technologies, Inc. | Vertical waveguides with various functionality on integrated circuits |
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US5221425A (en) * | 1991-08-21 | 1993-06-22 | International Business Machines Corporation | Method for reducing foreign matter on a wafer etched in a reactive ion etching process |
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JP2884970B2 (en) * | 1992-11-18 | 1999-04-19 | 株式会社デンソー | Dry etching method for semiconductor |
US5935877A (en) * | 1995-09-01 | 1999-08-10 | Applied Materials, Inc. | Etch process for forming contacts over titanium silicide |
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AUPO281896A0 (en) * | 1996-10-04 | 1996-10-31 | Unisearch Limited | Reactive ion etching of silica structures for integrated optics applications |
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1999
- 1999-03-31 GB GB9907302A patent/GB2348399A/en not_active Withdrawn
-
2000
- 2000-03-30 EP EP00914290A patent/EP1166341A1/en not_active Withdrawn
- 2000-03-30 WO PCT/GB2000/001231 patent/WO2000059020A1/en not_active Application Discontinuation
- 2000-03-30 AU AU35685/00A patent/AU3568500A/en not_active Abandoned
- 2000-03-30 GB GB0118719A patent/GB2363361B/en not_active Expired - Fee Related
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Title |
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Also Published As
Publication number | Publication date |
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AU3568500A (en) | 2000-10-16 |
WO2000059020A1 (en) | 2000-10-05 |
GB2363361B (en) | 2003-04-02 |
GB0118719D0 (en) | 2001-09-26 |
GB2363361A (en) | 2001-12-19 |
GB2348399A (en) | 2000-10-04 |
GB9907302D0 (en) | 1999-05-26 |
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