KR100518520B1 - Etching method of silicon film in semiconductor devices - Google Patents
Etching method of silicon film in semiconductor devices Download PDFInfo
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- KR100518520B1 KR100518520B1 KR10-1998-0032507A KR19980032507A KR100518520B1 KR 100518520 B1 KR100518520 B1 KR 100518520B1 KR 19980032507 A KR19980032507 A KR 19980032507A KR 100518520 B1 KR100518520 B1 KR 100518520B1
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Abstract
본 발명은 반도체 장치의 기초 막질 재료로 널리 이용되는 실리콘막을 식각하는 방법에 관한 것이다. 본 발명의 실리콘막의 식각방법은, SF6를 포함하는 식각가스와 상기 식각가스에 의한 등방성 식각을 방지하기 위한 산소 가스에, CH2F2 또는 CH3F를 첨가하여 실리콘막을 식각하는 것을 특징으로 한다.The present invention relates to a method of etching a silicon film widely used as a base film material of a semiconductor device. The etching method of the silicon film of the present invention is characterized in that the silicon film is etched by adding CH 2 F 2 or CH 3 F to an etching gas containing SF 6 and an oxygen gas for preventing isotropic etching by the etching gas. do.
본 발명에 의하면, 식각가스와 산소 가스에 CH2F2 또는 CH3F를 첨가함으로써, 종횡비의 차이에 따른 식각속도의 변화, 식각물의 재증착에 의한 패턴불량 및 등방성 식각에 의한 측벽 결함없이 양호하고 수직인 프로파일의 실리콘막 패턴이 얻어진다.According to the present invention, by adding CH 2 F 2 or CH 3 F to the etching gas and oxygen gas, it is possible to change the etching rate according to the difference in aspect ratio, without pattern defects due to redeposition of the etchant and sidewall defects due to isotropic etching. And a vertical silicon film pattern is obtained.
Description
본 발명은 반도체 장치의 기초 막질 재료로 널리 이용되는 실리콘막을 식각하는 방법에 관한 것이다.The present invention relates to a method of etching a silicon film widely used as a base film material of a semiconductor device.
실리콘막을 종횡비(aspect ratio)가 10 이상되는 패턴으로 식각하는 여러 가지 방법이 시도되어 왔다. 이러한 종횡비가 큰 실리콘막 패턴은 주로 DRAM 소자에서 커패시터로 이용되고, 최근에는 미세패턴의 형성시에 마스크로 사용하기 위한 시도를 하고 있다. Various methods have been attempted to etch a silicon film in a pattern having an aspect ratio of 10 or more. Such a large aspect ratio silicon film pattern is mainly used as a capacitor in DRAM devices, and recently, an attempt has been made to use it as a mask in forming a fine pattern.
종래 이렇게 종횡비가 큰 실리콘막 패턴은 화학반응이 우수하고 빠른 식각속도를 얻을 수 있는 F, Cl, Br 등의 할로겐족 원소를 이용하는 건식식각방법을 많이 사용하여 왔다. 실제 이러한 할로겐족 원소를 포함하는 식각가스로는 HBr, Cl2, SF6, CHF3, CF4 등이 사용되었다.Conventionally, the silicon film pattern having a large aspect ratio has used a lot of dry etching methods using halogen group elements such as F, Cl, Br, etc., which have excellent chemical reactions and obtain fast etching rates. In fact, as an etching gas containing such a halogen group element, HBr, Cl 2 , SF 6 , CHF 3 , CF 4 and the like were used.
또한, 할로겐족 원소들의 등방성 식각을 막기 위해 산소 가스를 첨가하여 식각하는데, 이 산소 가스에 의한 산화성 폴리머가 식각되는 실리콘막의 측벽에 재증착함으로써 식각하는 패턴의 경사가 발생하여, 특히 식각되는 패턴이 좁을수록 식각되는 면적이 줄어들고 그에 따라 식각속도가 줄어드는 문제가 있었다. 또한, 식각되는 패턴이 넓은 곳에서는 식각된 패턴의 바닥면에 산화성 폴리머의 재증착이 일어남으로써 패턴불량(이른바 black silicon이라고도 함)이 발생하는 문제가 있었다. 이러한 종래기술의 문제점을 트렌치(trench) 식각을 예로 하여 도시한 것이 도1로서, 도시된 바와 같이, 트렌치가 좁을수록(20) 식각속도의 저하가 두드러져 넓은 트렌치(40)에 비해 식각되는 깊이가 얕고, 식각되는 패턴이 넓은 곳(50)에서는 식각물의 재증착에 의한 패턴불량(55)이 일어난다.In addition, in order to prevent isotropic etching of the halogen group elements, oxygen gas is added and etched, and the oxidized polymer by the oxygen gas is redeposited on the sidewall of the silicon film to be etched so that the inclination of the etching pattern occurs, and in particular, the etching pattern is narrow. As the area to be etched decreases, the etching speed decreases accordingly. In addition, where the pattern to be etched is large, there is a problem in that a pattern defect (also called black silicon) occurs due to redeposition of the oxidative polymer on the bottom surface of the etched pattern. As shown in FIG. 1, the problem of the related art is illustrated by using trench etching as shown in FIG. 1. As shown in FIG. 1, the narrower the trench 20, the lower the etching speed is, so that the depth of etching compared to the wide trench 40 is increased. In the shallow and wide portions 50 to be etched, the pattern defect 55 is caused by redeposition of the etchant.
한편, 식각가스로서 특히 CF4나 CHF3를 사용하는 경우에, F 라디칼이 다량 발생하여 산화성 폴리머의 제거속도가 빨라져 식각 프로파일의 조절이 힘들고, 특히 식각속도가 빠른 부위에서 폴리머의 증착속도보다 제거속도가 빨라 국부적인 측면 결함(attack)이 발생한다.On the other hand, especially when CF 4 or CHF 3 is used as an etching gas, a large amount of F radicals are generated, which speeds up the removal rate of the oxidizing polymer, which makes it difficult to control the etching profile, particularly in the region where the etching rate is faster than the deposition rate of the polymer. The speed is high and a local side attack occurs.
본 발명은 이러한 종래기술의 문제점을 극복하기 위한 것으로서, 종횡비가 다양한 실리콘막의 패턴에서 등방성 식각을 막으면서도 식각물의 재증착을 방지하여 식각속도와 깊이를 균일하게 하고, 패턴불량이 발생하지 않는 실리콘막의 식각방법을 제공하는 것을 목적으로 한다.The present invention is to overcome the problems of the prior art, while preventing the isotropic etching in the pattern of the silicon film of various aspect ratio to prevent the redeposition of the etchant to uniform etching speed and depth, the pattern of the silicon film does not occur An object of the present invention is to provide an etching method.
상기의 목적을 달성하기 위한 본 발명에 따른 실리콘막의 식각방법은, SF6를 포함하는 식각가스와 상기 식각가스에 의한 등방성 식각을 방지하기 위한 산소 가스에, CH2F2 또는 CH3F를 첨가하여 실리콘막을 식각하는 것을 특징으로 한다.In the etching method of the silicon film according to the present invention for achieving the above object, CH 2 F 2 or CH 3 F is added to an etching gas containing SF 6 and an oxygen gas for preventing isotropic etching by the etching gas. By etching the silicon film.
본 발명의 실시예에 따르면, SF6와 산소 가스의 비율은 1:0.7 내지 1:1.3인 것이 바람직하다.According to an embodiment of the present invention, the ratio of SF 6 and oxygen gas is preferably 1: 0.7 to 1: 1.3.
또한, SF6와 산소 가스의 비율이 위와 같을 때, 첨가되는 CH2F2 또는 CH3F와 산소 가스의 비율은 0.7:1 내지 1:1인 것이 바람직하다.In addition, when the ratio of SF 6 and oxygen gas is as described above, the ratio of CH 2 F 2 or CH 3 F and oxygen gas to be added is preferably 0.7: 1 to 1: 1.
그리고, 기판온도는 -15℃ 내지 60℃로 하고, 식각챔버의 압력은 5mT 내지 40mT인 것이 바람직하다.The substrate temperature is -15 ° C to 60 ° C, and the etching chamber pressure is preferably 5mT to 40mT.
이와 같이, 본 발명은 종래의 식각가스와 산소 가스에 CH2F2 또는 CH3F를 첨가함으로써, 실리콘막에 특히 종횡비가 다양한 트렌치들을 형성할 때 균일한 식각속도와 깊이를 얻을 수 있으면서도 식각물의 재증착에 의한 패턴불량을 없앨 수 있다.As described above, the present invention adds CH 2 F 2 or CH 3 F to conventional etching gas and oxygen gas, thereby achieving uniform etching speed and depth while forming trenches having various aspect ratios in the silicon film. Eliminate pattern defects caused by redeposition.
이하, 첨부도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2 내지 도4는 본 발명의 식각방법에 따라 실리콘 기판의 소정영역에 0.3∼0.8μm의 다양한 폭을 갖는 트렌치들을 형성하는 과정을 도시한 단면도들이다. 먼저 도2를 보면, 실리콘 기판(100) 위에 430nm 두께의 고온열산화막(110), 60nm 두께의 반사방지막(120)이 차례로 적층되고, 그 위에 식각하고자 하는 영역을 노출시킨 감광막 패턴(130)이 형성되어 있다. 이때 사용되는 식각설비는 ICP(Inductivel Coupled Plasma) 방식의 식각장치로서 종래의 플라즈마 식각에 사용되는 통상적인 장치이다. 2 to 4 are cross-sectional views illustrating a process of forming trenches having various widths of 0.3 to 0.8 μm in predetermined regions of a silicon substrate according to the etching method of the present invention. First, referring to FIG. 2, a 430 nm-thick high-temperature thermal oxide film 110 and a 60-nm-thick antireflection film 120 are sequentially stacked on the silicon substrate 100, and the photoresist pattern 130 exposing the region to be etched is exposed. Formed. At this time, the etching apparatus used is an inductive coupled plasma (ICP) etching apparatus, which is a conventional apparatus used in conventional plasma etching.
도2와 같이 형성된 상태에서 감광막 패턴(130)을 마스크로 하여 우선 반사방지막(120)과 고온열산화막(110)을 식각한다. 그러면 도3과 같이 실리콘 기판(100) 위에 고온열산화막 및 반사방지막 패턴(111 및 121)이 형성되는데, 이 고온열산화막 및 반사방지막 패턴(111 및 121)이 실제 실리콘 기판을 식각할 때 마스크로 된다.2, the anti-reflection film 120 and the high temperature thermal oxide film 110 are etched using the photoresist pattern 130 as a mask. Then, as shown in FIG. 3, the high temperature thermal oxide film and the antireflection film patterns 111 and 121 are formed on the silicon substrate 100, and the high temperature thermal oxide film and the antireflection film patterns 111 and 121 serve as a mask when etching the actual silicon substrate. do.
이어서, 이 고온열산화막 및 반사방지막 패턴(111 및 121)을 마스크로 하여 실리콘 기판(100)을 본 발명의 식각방법에 따라 식각하면 도4와 같이 원하는 다양한 폭의 트렌치들이 형성된다. 본 발명의 특징은 이 실리콘 기판(100)의 식각과정에 있으며, 이를 상세히 설명하면 다음과 같다. Subsequently, when the silicon substrate 100 is etched according to the etching method of the present invention using the high temperature thermal oxide film and the antireflection film patterns 111 and 121 as masks, trenches of various widths as shown in FIG. 4 are formed. A feature of the present invention is the etching process of the silicon substrate 100, which will be described in detail as follows.
먼저, 식각가스로는 SF6를 사용하였으며, 산소 가스의 첨가비율은 SF6:O2 = 1:1±0.3이 되도록 한다.First, SF 6 was used as an etching gas, and an oxygen gas addition ratio was set to SF 6 : O 2 = 1: 1 ± 0.3.
그리고, SF6와 O2의 비율이 이와 같을 때, 첨가되는 CH2F2 또는 CH3F의 양에 따라 식각 프로파일의 기울기가 변화하는데 즉, (CH2F2 또는 CH3F) : O2의 비율이 작을수록 도5a에 도시된 바와 같이 기울기는 감소하여 90°이하로 되고, 이 비율이 클수록 도5b에 도시된 바와 같이 기울기는 90°이상으로 커진다. 또한, 이 비율이 클수록 식각폭이 넓은 곳에서 일어나는 패턴불량(black silicon)이 적어지고, 이 비율이 작을수록 패턴불량이 많아진다. 이는 CH2F2 또는 CH3F가 많을수록 산화성 폴리머의 제거효과가 크고, O2가 많을수록 등방성 식각 방지효과가 크다는 것을 의미한다. 본 실시예의 실험에서는 (CH2F2 또는 CH3F) : O2의 비율을 0.7:1∼1:1의 범위에서 변화시켰으며, 패턴불량이 발생하지 않는 최적의 비율은 SF6:O2 = 1:1일 때, 0.83:1로 나타났다.When the ratio of SF 6 and O 2 is equal to this, the slope of the etching profile changes according to the amount of CH 2 F 2 or CH 3 F added, that is, (CH 2 F 2 or CH 3 F): O 2 The smaller the ratio of, the smaller the slope becomes, as shown in Fig. 5A, to 90 ° or less, and the larger the ratio, the larger the slope becomes, as shown in Fig. 5B, to 90 ° or more. In addition, the larger this ratio is, the smaller the pattern defects (black silicon) that occur in a large etching width, and the smaller the ratio, the larger the pattern defects. This means that more CH 2 F 2 or CH 3 F has a greater effect of removing the oxidative polymer, and more O 2 has a greater effect of preventing isotropic etching. In the experiment of this example, the ratio of (CH 2 F 2 or CH 3 F): O 2 was changed in the range of 0.7: 1 to 1: 1, and the optimal ratio at which no pattern defect occurred was SF 6 : O 2 = 1: 1, 0.83: 1.
또한, 실리콘 기판의 식각시 식각챔버의 압력은 5∼40mT의 범위에서 실험하였으며, 최적의 압력은 SF6:O2 = 1:1일 때 20mT로 나타났다.In addition, the pressure of the etching chamber during the etching of the silicon substrate was tested in the range of 5 ~ 40mT, the optimum pressure was 20mT when SF 6 : O 2 = 1: 1.
이밖에 식각특성에 영향을 미치는 요인으로는 기판온도가 있는데, -15∼60℃ 범위에서 온도가 낮을수록 측벽에 폴리머의 증착이 증가하였으나, 식각폭이 넓은 곳에서의 패턴불량은 발생하지 않았다. 최적의 온도는 15℃로 나타났다.Other factors affecting the etching characteristics include substrate temperature. As the temperature is lower in the range of -15 to 60 ° C, the deposition of polymers on the sidewalls increases, but no pattern defect occurs in the wide etching region. The optimum temperature was found to be 15 ° C.
이상과 같은 결과로부터 최적의 조건 즉, SF6:O2 = 1:1, (CH2F2 또는 CH3F):O2 = 0.83:1, 기판온도 15℃, 챔버압력 20mT의 조건에서, 0.4μm 폭의 트렌치를 4μm 깊이(종횡비 10)로 수직하게 형성할 수 있었다. 이때의 식각속도는 1.17μm/min였으며, 또한 같은 조건에서 7μm 깊이까지 식각했을 때 평균 식각속도는 1.15μm/min로 식각깊이에 따른 변화는 거의 없었다. 이는 식각됨에 따라 종횡비가 증가하여도 식각속도의 저하없이 균일한 식각속도가 얻어짐을 의미한다.From the above results, under optimal conditions, namely SF 6 : O 2 = 1: 1, (CH 2 F 2 or CH 3 F): O 2 = 0.83: 1, substrate temperature 15 ℃, chamber pressure 20mT, A 0.4 μm wide trench could be formed vertically at 4 μm depth (10 aspect ratio). At this time, the etching rate was 1.17μm / min, and the average etching rate was 1.15μm / min when the etching was performed to the depth of 7μm under the same conditions. This means that a uniform etching rate is obtained without decreasing the etching rate even though the aspect ratio increases as the etching is performed.
또한, 같은 조건에서 0.4μm 폭의 트렌치와 0.7μm 폭의 트렌치를 동시에 식각했을 때, 그 식각속도의 차이는 6%로 나타났다. 이같은 결과는 식각속도의 차이는 종횡비에 의해 영향을 받기 보다는 처음의 식각폭에 의존하는 것을 의미한다.Also, when the 0.4 μm wide trench and the 0.7 μm wide trench were simultaneously etched under the same conditions, the difference in etching speed was 6%. These results indicate that the difference in etching rate depends on the initial etching width rather than being affected by the aspect ratio.
이상 상술한 바와 같이 본 발명의 실리콘막 식각방법에 의하면, 식각가스와 산소 가스에 CH2F2 또는 CH3F를 첨가함으로써, 종횡비의 차이에 따른 식각속도의 변화없이 1μm/min 이상의 식각속도를 유지하면서, 식각물의 재증착에 의한 패턴불량이나 등방성 식각에 의한 측벽 결함없이 양호하고 수직인 프로파일의 실리콘막 패턴이 얻어진다.As described above, according to the silicon film etching method of the present invention, by adding CH 2 F 2 or CH 3 F to the etching gas and the oxygen gas, the etching rate of 1 μm / min or more is changed without changing the etching rate according to the difference in aspect ratio. While maintaining, a good and vertical profile silicon film pattern is obtained without pattern defects due to redeposition of the etchant or sidewall defects due to isotropic etching.
도1은 종래의 방법에 의해 실리콘막을 식각하여 형성된 트렌치들을 도시한 단면도이다.1 is a cross-sectional view showing trenches formed by etching a silicon film by a conventional method.
도2 내지 도4는 본 발명에 따라 실리콘막을 식각하는 과정을 도시한 단면도들이다.2 to 4 are cross-sectional views illustrating a process of etching a silicon film according to the present invention.
도5a 및 도5b는 각각 (CH2F2 또는 CH3F) : O2의 비율이 작을 때와 클 때 얻어지는 트렌치들의 프로파일을 도시한 단면도들이다.5A and 5B are cross-sectional views illustrating profiles of trenches obtained when the ratio of (CH 2 F 2 or CH 3 F): O 2 is small and large, respectively.
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