WO2000059020A1 - A reactive ion etching process - Google Patents
A reactive ion etching process Download PDFInfo
- Publication number
- WO2000059020A1 WO2000059020A1 PCT/GB2000/001231 GB0001231W WO0059020A1 WO 2000059020 A1 WO2000059020 A1 WO 2000059020A1 GB 0001231 W GB0001231 W GB 0001231W WO 0059020 A1 WO0059020 A1 WO 0059020A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- waveguide
- rie
- seem
- fabricating
- gas
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
Definitions
- the invention relates to a reactive ion etching (RIE) process, in particular to a RIE process which can be used in the fabrication of an optical waveguide with low surface and sidewall roughness and which has low levels of material re-deposition.
- RIE reactive ion etching
- Such components include large scale silica glass film waveguides whose planar dimensions are normally in the range 4 ⁇ m to 8 ⁇ m but which can exceed lO ⁇ m. This differs from devices which are fabricated for the semiconductor industry, where etch depths are small ( ⁇ 2 ⁇ m) and where the amount of etched material is typically less than 5%, such that the "loading effect", or amount of material redeposition, is reduced.
- the deep etching of the silica glass films during the fabrication of such waveguides by dry etch mask techniques has several known disadvantages .
- RIE processes have several disadvantages known in the prior art. RIE generally depends on ion assisted chemical reactions forming volatile species which are subsequently removed during the waveguide fabrication process. However, it is desirable in certain applications for the waveguides to be doped with rare earth or heavy metal species which form involatile products during the RIE process. These involatile products enable surface imperfections or "grass” to develop on the etched surfaces surrounding the waveguide.
- the RIE process can be controlled so that certain parameters directly or indirectly affect the etchant speed and the amount of ion re-deposition which occurs during the RIE processing stage of fabricating an optical waveguide.
- the invention seeks to provide an RIE process which achieves a fast etch speed which preserves the integrity of the mask used to define the waveguide core area and which also provides high quality waveguide core side walls.
- etchant gas which may be a mixture of actively etching gas(es) with dilutant or process gas(es)
- Suitable ranges of values for the RIE process parameters are provided according to the invention to enable the RIE process to produce heavy metal or rare earth doped channel waveguides.
- the waveguide cores are formed with a desirably low level of surface roughness and are etched at a desirable speed with minimal damage to the waveguide side walls.
- a range of values for the pressure of an etchant gas, the rate at which the etchant gas is supplied, and the radio frequency (r.f) power density used in the RIE process are given.
- a reactive ion etching process comprising the steps of: controlling the flow rate of at least one etchant gas used in said reactive ion etching process; controlling the pressure of said at least one etchant gas ; and controlling the r.f. power density used in said reactive ion etching process, wherein the parameters of flow rate, pressure and r.f. power are selected to obtain a desired etch rate and/or to reduce the level of ion dopant material redeposited in the reactive ion etching process .
- Figs. 1A to IC show scanned electron micrographs of a erbium doped phosphosilicate waveguide with varying levels of surface roughness.
- Figs .1A to IC illustrate scanned electron microscope images of erbium doped phosphosilicate waveguides formed by a method of fabricating an optical waveguide which incorporates the method of optimising the reactive ion etching (RIE) process to achieve a desired etch rate and/or level of etched surface roughness.
- RIE reactive ion etching
- an optical waveguide 1 which displays a moderate number of surface defects 2.
- the RIE process in the fabrication of the optical waveguide has been controlled to ensure a rapid etch rate to the detriment of the smoothness of the waveguide surface.
- Fig. IB an optical waveguide 3 is shown which displays a fewer surface defects 4, than shown in Fig. 1A.
- the RIE process in the fabrication of the optical waveguide has been controlled to slightly compromise the rapidity of the etch rate to give a lower degree of roughness of the waveguide surface .
- an optical waveguide 5 which displays a minimal number of surface defects 6.
- the RIE process in the fabrication of the optical waveguide has been controlled to ensure the roughness of the waveguide surface is been reduced to a minimum to the detriment of the etch rate.
- a method of fabricating an optical waveguide includes the following stages : -
- stage three Forming at least one cladding layer to embed the waveguide core and optionally doping said cladding layer.
- any suitably appropriate process can be used to perform each of stages one, two and four.
- the masking step of stage three can be performed conventionally but the reactive ion etching process step of stage three is performed according to the invention.
- An intermediate layer for example a buffer layer and an upper intermediate layer deposited thereon, is deposited on a substrate, for example a silicon substrate using, for example, a flame hydrolysis deposition (FHD) process.
- FHD flame hydrolysis deposition
- the buffer layer comprises silica, but can be any thermally oxidised layer of the substrate.
- the upper intermediate layer comprises silica, and is doped with selected dopant ions which induce certain desired properties in the upper intermediate layer.
- the upper intermediate layer is then consolidated, for example, in an electrical furnace or by an FHD burner, before any subsequent layers are deposited.
- a core layer is subsequently deposited using an FHD process.
- the core layer comprises silica, and is doped with dopant ions which induce certain desired properties in the core layer.
- the core layer is then consolidated, for example in an electrical furnace or by an FHD burner, at least partially before any subsequent layers are deposited.
- the normal FHD apparatus is modified so that the core layer can be aerosol doped.
- An additional feed is provided on the FHD apparatus supplies aerosol droplets of the dopant ions.
- High concentrations of core layer dopant ions for example concentrations exceeding 0.5wt%, but more typically in the range 0.2wt% to 2 wt%, of rare earth ions or heavy metal ions can be introduced during the deposition of the core layers by using such an aerosol doping technique .
- the waveguide core is then formed from the core layer by masking the core layer and etching away the unwanted portion of the core layer. Subsequently, another cladding layer is deposited and consolidated similarly to the first cladding layer.
- stages of fabricating an optical waveguide are possible which differ from those described in the preferred embodiment.
- more than one intermediate, core and/or cladding layers can be deposited at each stage.
- the intermediate, core and cladding layers may be only partially consolidated after they are deposited and full consolidation can be achieved by subsequent thermal treatment, for example, when a subsequently deposited layer is being consolidated.
- the choice of fabrication process depends to an extent on the deposition and consolidation temperatures of each layer.
- the waveguide core is formed from the core layers by performing a suitable masking process on the uppermost core layer so that a mask portion covers the waveguide area to be retained during the RIE process.
- the RIE process parameters are selected to enable the desired etch rate to be achieved with a minimal amount of erosion of the mask portion and with a minimal amount of undercut under the mask portion.
- the RIE etchant gas is thus selected to exhibit a high degree of selectivity between the mask layer and the waveguide layers to be etched.
- the mask used is preferably metal, for example, nichrome (NiCr) or alternatively is Ni , Ti-Ni, or Ti:NiCr.
- Other suitable masks include amorphous silicon and polysilicon.
- the mask is formed by depositing a mask layer, i.e. a layer of masking material, on the uppermost core layer.
- the metal masks may be deposited, for example, by thermal evaporation, electron beam evaporation or sputtering.
- Amorphous silicon masks may be deposited, for example, by plasma enhanced chemical vapour deposition (PECVD)
- silicon masks may be deposited, for example, by low pressure chemical vapour deposition (LPCVD) .
- PECVD plasma enhanced chemical vapour deposition
- LPCVD low pressure chemical vapour deposition
- a layer of resist for example, photo-resist, is then formed on top of the mask layer and is patterned using standard photo- lithographic techniques which remove the resist. The exposed unwanted mask areas are then etched away and the wanted mask portion defining the waveguide is finally left covered by the mask and resist layers.
- the metal mask is deposited by using an evaporator.
- a mask thickness of 100 nm was used which lies in a suitable range of lOnm to 800nm.
- a suitable photoresist is SHIPLEYTM S1818 which was postbaked at 120°C.
- a 1.8 ⁇ m thick photoresist can be alone as a dry etch mask.
- the method of controlling the RIE process selectively controls certain selected parameters, for example, the pressures of the etchant gases used, the flow rate of the etchant gas, and the r.f. power density used. It is desirable for the etchant gas to offer a high etch rate yet be highly selective between the mask and core material. If the selectivity is low, the side wall quality is reduced.
- the etchant gas is a ideally a fluorine based etch gas and/or at least one other gas, for example, a dilutant or a process gas, e.g. 0 2 .
- Fluorine based gases can be used, for example, to etch both metal and silicon based masks or alternatively, chlorine bases gases can be used to etch silicon based masks.
- the process gas is selected, for example, so that the amount of polymer formation during the RIE process stage of fabricating a waveguide is increased, which increases the anisotropy of the etching process and so improves the vertical orientation of the side-walls of the waveguide channel which are etched.
- RIE parameters affect the etch rate of the RIE process and the amount of material which is redeposited during the RIE processing stage.
- the amount of re-deposition which occurs during the RIE processing stage directly and/or indirectly determines the level of surface roughness of the etched surfaces formed.
- the etchant gas includes a process gas, for example 0 2 , and a fluorine based chemical, for example, CHF 3 .
- a process gas for example 0 2
- a fluorine based chemical for example, CHF 3
- Selecting suitable values for the RIE parameters with this etchant gas enables the RIE process to form waveguide cores which possess a desirably low level of surface roughness and/or which are formed at a desirable etch rate.
- the parameters varied are the fluorine based etchant gas flow rate, the process gas flow rate, the etchant gas pressure and the r.f. power density. Selected values of these RIE parameters and the RIE etchant speeds and levels of waveguide core surface roughness obtained by the RIE process using these parameters are detailed in Table 1A shown overleaf .
- a level setting for the RIE process combines selected values of the RIE parameters. Three level settings are given in Table IB shown below: -
- Table IB The values set for each of the RIE parameters for each level setting of the RIE process.
- the etch rate average for an CHF 3 flow of 5 seem (runs 1,2, and 3) is given by the average of El (1.85 ⁇ m/hr), E2 (5.42 ⁇ m/hr) and E3 (13. ll ⁇ m/hr) . This is denoted as E C1 , and is 6.79 ⁇ m/hr.
- the etch rate average for CHF 3 flow setting 2, 25 seem is given by the
- Table 1 The CHF 3 gas flow rate, the 0 2 gas flow rate, etchant gas pressure and r.f. power density and the resulting etch rate of the RIE process and the roughness of the waveguide surface etched by the RIE process.
- the average etch rates obtained by the RIE process for each level setting of the RIE process are shown overleaf in Table 2A, and the average surface roughness of the waveguides formed by each level setting are shown in Table 2B .
- Each of the first three rows in Table 2A corresponds to a different level setting, i.e., to a different set of parameters selected to control the RIE process .
- the final row gives the difference between the maximum and minimum etch rates in each column.
- the etch rate difference for the CHF 3 flow parameter values selected, ⁇ E C is E C1 -E C2 , or 2.63 ⁇ m/hr.
- the etch rate difference for the pressure parameter values selected is given by E Pr3 - E Prl , or 2.91 ⁇ m/hr.
- the maximum etch rate for each of the RIE parameter values selected occurs at the smallest CHF 3 flow value, greatest 0 2 flow value, highest pressure value and highest power value, i.e., by the values E cl , E 03 , E Pr3 , E Po3 .
- the RIE process is optimized for maximum etch rate by setting the RIE parameters to these values.
- Table 2B shows the average surface roughness of the optical waveguide formed by the RIE process.
- Each of the first three rows corresponds to a different level setting: i.e., to a different set of parameters selected to control the RIE process.
- the final row gives the difference between the maximum and minimum surface roughness obtained in each column.
- Table 2B shows that RIE process produces minimal roughness for the greatest CHF 3 flow, medium 0 2 flow, smallest pressure and smallest power (E C3 , E 02 , E Prl , E Pol ) .
- RIE parameters a CHF 3 flow rate of 25 seem, an 0 2 flow rate of 5 seem, a pressure of 20 mTorr, and a r.f. power density of 0.6W/cm 2 give an etch rate of 5.2 ⁇ m/hr. These settings give a desirably low level of re-deposition and a desirably low level of surface roughness.
- Fig. IC displays a scanned electron microscope image of an erbium doped phosphosilicate waveguide 5 fabricated using these RIE parameter values.
- RIE parameter values are suitable: a CHF 3 flow rate of 5 to 75 seem; an 0 2 flow rate of 0 to 15 seem, a pressure of 5 to 30 mTorr, and a r.f. power density of 0.06 to 0.64 Wcm "2 .
- the selection of parameter values in these ranges gives RIE etch rates of between 1.8 and 1.3 ⁇ m/hr and surface roughness levels of between 5 and 100 nm.
- the RIE process is controlled to give an optimum etch rate which depends strongly on the pressure and power by selecting the following parameter values: a CHF 3 carrier gas flow rate of 45 seem, an 0 2 flow rate of 5 seem, a pressure of 20 mTorr, and a r.f. power density of 0.6 Wcm "2 .
- Fig. IB illustrates a scanned electron microscope image of an erbium doped phosphosilicate waveguide 5 formed according to this embodiment.
- etch rate the following ranges of parameter values are suitable: a CHF 3 flow rate of 5 to 45 seem; an 0 2 flow rate of 5 to 15 seem, a pressure of 80 to 120 mTorr, and a r.f. power density of 0.54 to 0.95 W/cm 2 .
- the selection of parameter values in these ranges gives RIE etch rates of between 8 ⁇ m and 13 ⁇ m/hr and surface roughness levels of between 100 and 200 nm.
- etchant gas used in the RIE process in the preferred embodiment of the invention
- other fluoride based etchant gases can be used for etching silica type material such as CF 4 , C 2 F 6/ SF 6 , etc.
- Process gases such as Ar, CH4 , etc can also be incorporated into the etchant .
- the RIE processing stage can be generally tailored for each etchant gas mix to produce optimal etch rates by using high flow rate, low pressure and high power parameters.
- the RIE processing stage can be tailored to reduce the amount of ion deposition and thus the level of surface roughness of the optical waveguide formed by the method. Desirably low levels of surface roughness of silicon based waveguides of between 5 nm to 100 nm can be achieved.
- Waveguides which are fabricated using the invention display further desired properties, for example substantially vertical (90°) sidewalls.
- the RIE rate can exceed 115 nm/ in.
- An etch rate in excess of 115 nm/min was achieved using an etchant gas flow rate of ⁇ 45sccm, a low etchant gas pressure of -20 mTorr and by using a high r.f. power density of 0.6 Wcm "2 .
- the resulting waveguide has a side wall anisotropy of >89° and a relatively low surface roughness of 19nm.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0118719A GB2363361B (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
AU35685/00A AU3568500A (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
EP00914290A EP1166341A1 (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9907302A GB2348399A (en) | 1999-03-31 | 1999-03-31 | Reactive ion etching with control of etch gas flow rate, pressure and rf power |
GB9907302.5 | 1999-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000059020A1 true WO2000059020A1 (en) | 2000-10-05 |
Family
ID=10850638
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB2000/001231 WO2000059020A1 (en) | 1999-03-31 | 2000-03-30 | A reactive ion etching process |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1166341A1 (en) |
AU (1) | AU3568500A (en) |
GB (2) | GB2348399A (en) |
WO (1) | WO2000059020A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002088787A2 (en) * | 2001-04-27 | 2002-11-07 | Lightcross, Inc. | Formation of an optical component having smooth sidewalls |
EP1394581A1 (en) * | 2002-02-06 | 2004-03-03 | Matsushita Electric Industrial Co., Ltd. | Optical waveguide manufacturing method |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8835831B2 (en) | 2010-06-22 | 2014-09-16 | Zena Technologies, Inc. | Polarized light detecting device and fabrication methods of the same |
US8890271B2 (en) | 2010-06-30 | 2014-11-18 | Zena Technologies, Inc. | Silicon nitride light pipes for image sensors |
US8274039B2 (en) | 2008-11-13 | 2012-09-25 | Zena Technologies, Inc. | Vertical waveguides with various functionality on integrated circuits |
US8866065B2 (en) | 2010-12-13 | 2014-10-21 | Zena Technologies, Inc. | Nanowire arrays comprising fluorescent nanowires |
US8229255B2 (en) | 2008-09-04 | 2012-07-24 | Zena Technologies, Inc. | Optical waveguides in image sensors |
US9406709B2 (en) | 2010-06-22 | 2016-08-02 | President And Fellows Of Harvard College | Methods for fabricating and using nanowires |
US9000353B2 (en) | 2010-06-22 | 2015-04-07 | President And Fellows Of Harvard College | Light absorption and filtering properties of vertically oriented semiconductor nano wires |
US9343490B2 (en) | 2013-08-09 | 2016-05-17 | Zena Technologies, Inc. | Nanowire structured color filter arrays and fabrication method of the same |
US8735797B2 (en) | 2009-12-08 | 2014-05-27 | Zena Technologies, Inc. | Nanowire photo-detector grown on a back-side illuminated image sensor |
US8519379B2 (en) | 2009-12-08 | 2013-08-27 | Zena Technologies, Inc. | Nanowire structured photodiode with a surrounding epitaxially grown P or N layer |
US9515218B2 (en) | 2008-09-04 | 2016-12-06 | Zena Technologies, Inc. | Vertical pillar structured photovoltaic devices with mirrors and optical claddings |
US8269985B2 (en) | 2009-05-26 | 2012-09-18 | Zena Technologies, Inc. | Determination of optimal diameters for nanowires |
US8299472B2 (en) | 2009-12-08 | 2012-10-30 | Young-June Yu | Active pixel sensor with nanowire structured photodetectors |
US8791470B2 (en) | 2009-10-05 | 2014-07-29 | Zena Technologies, Inc. | Nano structured LEDs |
US9082673B2 (en) | 2009-10-05 | 2015-07-14 | Zena Technologies, Inc. | Passivated upstanding nanostructures and methods of making the same |
US8748799B2 (en) | 2010-12-14 | 2014-06-10 | Zena Technologies, Inc. | Full color single pixel including doublet or quadruplet si nanowires for image sensors |
US9299866B2 (en) | 2010-12-30 | 2016-03-29 | Zena Technologies, Inc. | Nanowire array based solar energy harvesting device |
US8889455B2 (en) | 2009-12-08 | 2014-11-18 | Zena Technologies, Inc. | Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor |
US8546742B2 (en) | 2009-06-04 | 2013-10-01 | Zena Technologies, Inc. | Array of nanowires in a single cavity with anti-reflective coating on substrate |
US9478685B2 (en) | 2014-06-23 | 2016-10-25 | Zena Technologies, Inc. | Vertical pillar structured infrared detector and fabrication method for the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5176790A (en) * | 1991-09-25 | 1993-01-05 | Applied Materials, Inc. | Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal |
US5431772A (en) * | 1991-05-09 | 1995-07-11 | International Business Machines Corporation | Selective silicon nitride plasma etching process |
EP0763850A1 (en) * | 1995-09-01 | 1997-03-19 | Applied Materials, Inc. | Etch process for forming contacts over a silicide layer |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4992134A (en) * | 1989-11-14 | 1991-02-12 | Advanced Micro Devices, Inc. | Dopant-independent polysilicon plasma etch |
JP2830978B2 (en) * | 1990-09-21 | 1998-12-02 | 忠弘 大見 | Reactive ion etching apparatus and plasma processing apparatus |
US5221425A (en) * | 1991-08-21 | 1993-06-22 | International Business Machines Corporation | Method for reducing foreign matter on a wafer etched in a reactive ion etching process |
JP2884970B2 (en) * | 1992-11-18 | 1999-04-19 | 株式会社デンソー | Dry etching method for semiconductor |
US5637190A (en) * | 1995-09-15 | 1997-06-10 | Vanguard International Semiconductor Corporation | Plasma purge method for plasma process particle control |
EP0822582B1 (en) * | 1996-08-01 | 2003-10-01 | Surface Technology Systems Plc | Method of etching substrates |
AUPO281896A0 (en) * | 1996-10-04 | 1996-10-31 | Unisearch Limited | Reactive ion etching of silica structures for integrated optics applications |
-
1999
- 1999-03-31 GB GB9907302A patent/GB2348399A/en not_active Withdrawn
-
2000
- 2000-03-30 GB GB0118719A patent/GB2363361B/en not_active Expired - Fee Related
- 2000-03-30 AU AU35685/00A patent/AU3568500A/en not_active Abandoned
- 2000-03-30 WO PCT/GB2000/001231 patent/WO2000059020A1/en not_active Application Discontinuation
- 2000-03-30 EP EP00914290A patent/EP1166341A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5431772A (en) * | 1991-05-09 | 1995-07-11 | International Business Machines Corporation | Selective silicon nitride plasma etching process |
US5176790A (en) * | 1991-09-25 | 1993-01-05 | Applied Materials, Inc. | Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal |
EP0763850A1 (en) * | 1995-09-01 | 1997-03-19 | Applied Materials, Inc. | Etch process for forming contacts over a silicide layer |
Non-Patent Citations (3)
Title |
---|
BONAR J ET AL: "AEROSOL DOPED ND PLANAR SILICA WAVEGUIDE LASER", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 31, no. 2, 19 January 1995 (1995-01-19), pages 99 - 100, XP000504787, ISSN: 0013-5194 * |
BONDUR J A ET AL: "GAS MIXING TO PREVENT POLYMER FORMATION DURING REACTIVE ION ETCHING", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 21, no. 10, 1 March 1979 (1979-03-01), pages 4016, XP002003416, ISSN: 0018-8689 * |
DATABASE INSPEC INSTITUTE OF ELECTRICAL ENGINEERS, STEVENAGE, GB; DUTTA: "Prospects of vertical and smooth etching of thick silicon oxide for opto-electronics integration", XP002145015 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002088787A2 (en) * | 2001-04-27 | 2002-11-07 | Lightcross, Inc. | Formation of an optical component having smooth sidewalls |
WO2002088787A3 (en) * | 2001-04-27 | 2003-09-25 | Lightcross Inc | Formation of an optical component having smooth sidewalls |
EP1394581A1 (en) * | 2002-02-06 | 2004-03-03 | Matsushita Electric Industrial Co., Ltd. | Optical waveguide manufacturing method |
EP1394581A4 (en) * | 2002-02-06 | 2006-12-13 | Matsushita Electric Ind Co Ltd | Optical waveguide manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
GB2363361A (en) | 2001-12-19 |
GB2363361B (en) | 2003-04-02 |
EP1166341A1 (en) | 2002-01-02 |
AU3568500A (en) | 2000-10-16 |
GB0118719D0 (en) | 2001-09-26 |
GB2348399A (en) | 2000-10-04 |
GB9907302D0 (en) | 1999-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2000059020A1 (en) | A reactive ion etching process | |
EP1576399B1 (en) | Process for fabrication of optical waveguides | |
US6356694B1 (en) | Process for producing planar waveguide structures as well as waveguide structure | |
US7469558B2 (en) | As-deposited planar optical waveguides with low scattering loss and methods for their manufacture | |
US5354417A (en) | Etching MoSi2 using SF6, HBr and O2 | |
EP1123522B1 (en) | Manufacture of a silicon waveguide structure | |
US20020104821A1 (en) | Reactive ion etching of silica structures | |
US7573085B2 (en) | Deep trench formation in semiconductor device fabrication | |
US6037268A (en) | Method for etching tantalum oxide | |
US6376272B1 (en) | InA1As etch stop layer for precise semiconductor waveguide fabrication | |
Hines et al. | Patterning of wave guides in LiNbO 3 using ion beam etching and reactive ion beam etching | |
KR20010013402A (en) | Method of forming a silicon layer on a surface | |
US20020158047A1 (en) | Formation of an optical component having smooth sidewalls | |
JP2606679B2 (en) | Manufacturing method of optical waveguide | |
KR100518520B1 (en) | Etching method of silicon film in semiconductor devices | |
JPH07333452A (en) | Production of optical waveguide | |
KR20030038651A (en) | Process for selectively etching doped silicon dioxide over undoped silicon dioxide and silicon nitride | |
AU724044B2 (en) | Reactive ion etching of silica structures | |
WO2002097874A1 (en) | Method for deep and vertical dry etching of dielectrics | |
Ting et al. | RIE lag in diffractive optical element etching | |
JPH0933741A (en) | Quartz optical waveguide and its production | |
JPWO2003067293A1 (en) | Manufacturing method of optical waveguide | |
Libing et al. | Optimization of Plasma Etching Parameters and Mask for Silica Optical Waveguides | |
Zhou et al. | Fabrication of silica-on-silicon planar lightwave circuits by PECVD and ECR | |
Ou | Engineering sidewall angles of silica-on-silicon waveguides |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2000914290 Country of ref document: EP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref country code: GB Ref document number: 200118719 Kind code of ref document: A Format of ref document f/p: F |
|
WWP | Wipo information: published in national office |
Ref document number: 2000914290 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 09937791 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: JP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2000914290 Country of ref document: EP |