EP1155447A2 - Structure a semi-conducteur dotee d'une piste conductrice - Google Patents

Structure a semi-conducteur dotee d'une piste conductrice

Info

Publication number
EP1155447A2
EP1155447A2 EP00908981A EP00908981A EP1155447A2 EP 1155447 A2 EP1155447 A2 EP 1155447A2 EP 00908981 A EP00908981 A EP 00908981A EP 00908981 A EP00908981 A EP 00908981A EP 1155447 A2 EP1155447 A2 EP 1155447A2
Authority
EP
European Patent Office
Prior art keywords
conductive layer
semiconductor structure
interconnect
cavity
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00908981A
Other languages
German (de)
English (en)
Inventor
Gerd Lichter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1155447A2 publication Critical patent/EP1155447A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate

Definitions

  • the invention relates to a semiconductor structure in an integrated circuit with an insulating layer on a carrier and with an interconnect which is arranged above the insulating layer, and to a method for producing the structure.
  • interconnects are required as wiring to control the individual components. These interconnects often also lead over an active area or other conductive structures, so that parasitic capacitances occur which impair the speed of the circuit.
  • interconnects in integrated circuits are used as word lines of transistors.
  • An interconnect forms the gate of a MOS transistor over an active region in the semiconductor substrate which has two regions which are spaced apart and doped in the opposite manner to the conductivity type of the substrate.
  • the transistor can be switched using the potential of the gate. In many cases it is it is desirable that a transistor in a circuit be always open (or always closed) regardless of the potential of the gate. In this way, a given integrated circuit can be programmed.
  • the object of the present invention is to provide a semiconductor structure with an interconnect, which on the one hand has a low parasitic capacitance, and a manufacturing method for such a semiconductor structure.
  • Another object is to specify a semiconductor structure with a conductor track, which allows simple programming of transistors, and a corresponding programming method.
  • the invention is based on the idea of arranging the interconnect on a cavity.
  • the lower surface of the cavity borders on an insulating layer on a carrier, with its upper surface on the interconnect and on two opposite sides on an insulating cover.
  • the insulating cover also covers the sidewalls of the interconnect.
  • under a section of the electrically conductive interconnect extends a cavity with essentially the same lateral dimensions as the interconnect.
  • the cavity is preferably filled with air or an essentially inert gas, in particular it is partially evacuated.
  • the cavity Transversely to the direction of the interconnect, the cavity has essentially the same width as the width of the interconnect. In the direction of the interconnect, the cavity can extend under the entire interconnect.
  • the track can also have a portion in which it is arranged on a lower conductive layer, in other words, the
  • Cavity is here filled quasi with the lower conductive layer, in particular with n-doped or p ⁇ doped polysilicon.
  • the interconnect can be used as
  • the interconnect preferably consists of a metal silicide.
  • the carrier over which the interconnect with the underlying cavity is arranged can contain an active region in the form of two spaced doped S / D regions of a MOS transistor.
  • the semiconductor structure here represents a MOS transistor in which the interconnect forms the gate and is separated from the gate oxide by a cavity. Such a transistor is always open or closed, regardless of the potential of the gate (normaly on or normaly off depending on the selected threshold voltage).
  • the production method for the semiconductor structure provides for an insulating layer to be applied to a carrier and then for a lower conductive layer and an upper conductive layer to be applied.
  • the upper conductive layer can also be a multilayer.
  • the two conductive layers are structured, preferably simultaneously, in the form of a web in accordance with the interconnect to be produced.
  • An insulating cover is formed on the exposed surfaces of the lower and upper conductive layers.
  • An opening is then created in the insulating cover that at least partially exposes a surface of the lower conductive layer. Through this opening, the lower conductive layer is selectively removed using an essentially isotropic etching process. The opening is closed with another insulating material.
  • the lower conductive layer preferably consists of n-doped or p ⁇ - Polysilicon, and the top conductive layer of one
  • Si-LLzid For the etching of the lower conductive layer, i.e. KOH can be used in particular to create the cavity.
  • the cavity is to be created over a longer section of the interconnect, it is advantageous to arrange a plurality of openings in the cover at a predetermined distance from one another along the interconnect.
  • a transistor formed in the semiconductor substrate can be programmed in a simple manner: depending on the arrangement of an opening in the insulating cover and on the etching time, either a cavity is formed over the channel region of the transistor, or the lower conductive layer remains and forms part of the gate. Only in the latter case is the transistor controlled via the potential of the gate.
  • the invention thus enables a mask-programmable circuit.
  • a major advantage is that customary process steps for producing a conductive path, in particular a word line in a memory circuit, can be used and only one etching (with photo technology) for opening the insulating cover and the subsequent one
  • Cavity etching must be performed. In some DRAM concepts, these etchings to form other structures - for example a conductive strap that connects the selection transistor to a storage capacitor - have already been implemented, so that only one
  • FIGS. 1 to 5 show a section through or a top view (FIG. 2) of a semiconductor substrate, on which the method steps and the semiconductor structure are illustrated.
  • a silicon oxide layer is applied as an insulating layer 2.
  • the silicon oxide layer can be used as gate oxide in certain sections of the circuit.
  • N-doped polysilicon is applied as the lower conductive layer 3 and a metal silicide, in particular Wsi x , is applied as the upper conductive layer 4 using known methods.
  • This double layer 3, 4 is structured in the form of a web (see FIG. 2) and provided with an insulating cover 5 on the free surfaces.
  • Covering can consist of a part lying on the upper conductive layer 4 and lateral spacers, the lying part being structured in a web shape together with the conductive layers 3, 4 and the spacers then being produced on the side walls. This procedure is known for encapsulation of interconnects, for example word lines, on all sides.
  • the insulating cover can in particular consist of silicon oxide and / or silicon nitride.
  • FIG 2 The top view schematically shows the position of the lower and upper conductive layers 3, 4 and the insulating cover 5. The area shown in broken lines indicates the position of an opening 6 in the opening to be made Photomask on. Outside the opening, the arrangement with
  • the opening must overlap the insulating cover, to the extent that with an etching
  • the opening 6 must extend up to this side wall, preferably the
  • Interconnect overlaps This requirement can be omitted in the case of etching with an isotropic component.
  • the upper interconnect 4 is not attacked when the opening is made.
  • FIG. 3 shows the arrangement obtained in cross section at a point remote from the opening 6 (see FIG. 2), FIG. 4 shows a cross section in the region of the opening. Under the upper conductive layer 4 is a
  • the openings 6 are provided at a number of points at a predetermined distance along the path.
  • the upper interconnect 4 is not attacked when the opening is made.
  • the hole formed in the insulating cover is closed again.
  • a layer 7 of the material of the insulating cover is preferably deposited over the entire surface.
  • a bar or phosphorus-doped glass is preferably used as layer 7, as is usually used as a so-called “under layer dielectric”.
  • Structures in the carrier are composed of the insulating layer 2 (preferably a gate oxide) of a few nm thickness and of the cavity, which is preferably filled with air and whose vertical extent is preferably in the range from 200 to 800 nm.
  • the insulating layer 2 preferably a gate oxide
  • FIG. 6 shows the application of the invention to a carrier with a MOS transistor.
  • the carrier there are doped regions 10, 12 which have the conductivity type opposite to that of the semiconductor substrate 1.
  • a channel region 11 is located between the doped regions 10, 12, which represent source and drain.
  • the interconnect 4 is guided as a gate over the channel region and is insulated from the substrate by the insulating layer 2.
  • the cavity (H), which was produced according to the invention, is located between the interconnect 4 and the insulating layer 2. The transistor shown is not switched by a potential applied to the interconnect 4.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

Structure à semi-conducteur qui comporte une piste conductrice séparée par un espace creux d'une couche isolante sous-jacente située sur un support. Selon le procédé de fabrication de ladite structure, la piste conductrice est d'abord structurée sur une double couche puis dotée d'une structure de recouvrement isolante. Une ouverture dans la structure de recouvrement isolante est ensuite ménagée par attaque chimique et la couche conductrice sous-jacente est sélectivement éliminée. Ledit procédé permet d'une part de fabriquer un câblage de faible capacité et d'autre part de programmer de manière simple les transistors MOS.
EP00908981A 1999-02-15 2000-02-01 Structure a semi-conducteur dotee d'une piste conductrice Withdrawn EP1155447A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19906291 1999-02-15
DE19906291A DE19906291A1 (de) 1999-02-15 1999-02-15 Halbleiterstruktur mit einer Leitbahn
PCT/DE2000/000298 WO2000049642A2 (fr) 1999-02-15 2000-02-01 Structure a semi-conducteur dotee d'une piste conductrice

Publications (1)

Publication Number Publication Date
EP1155447A2 true EP1155447A2 (fr) 2001-11-21

Family

ID=7897567

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00908981A Withdrawn EP1155447A2 (fr) 1999-02-15 2000-02-01 Structure a semi-conducteur dotee d'une piste conductrice

Country Status (5)

Country Link
US (1) US6724055B2 (fr)
EP (1) EP1155447A2 (fr)
JP (1) JP4027039B2 (fr)
DE (1) DE19906291A1 (fr)
WO (1) WO2000049642A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10126294C1 (de) * 2001-05-30 2002-11-28 Infineon Technologies Ag Herstellungsverfahren für eine integrierte Schaltung
US8022489B2 (en) * 2005-05-20 2011-09-20 Macronix International Co., Ltd. Air tunnel floating gate memory cell

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US5798559A (en) * 1996-03-29 1998-08-25 Vlsi Technology, Inc. Integrated circuit structure having an air dielectric and dielectric support pillars
US5828121A (en) * 1994-07-15 1998-10-27 United Microelectronics Corporation Multi-level conduction structure for VLSI circuits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3635462A1 (de) * 1985-10-21 1987-04-23 Sharp Kk Feldeffekt-drucksensor
US5185294A (en) * 1991-11-22 1993-02-09 International Business Machines Corporation Boron out-diffused surface strap process
DE4337355C2 (de) * 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5670404A (en) * 1996-06-21 1997-09-23 Industrial Technology Research Institute Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
TW363273B (en) * 1997-04-18 1999-07-01 United Microelectronics Corp Manufacturing method for multi-level ROM
US6204103B1 (en) * 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
US6441418B1 (en) * 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933743A (en) * 1989-03-11 1990-06-12 Fairchild Semiconductor Corporation High performance interconnect system for an integrated circuit
US5828121A (en) * 1994-07-15 1998-10-27 United Microelectronics Corporation Multi-level conduction structure for VLSI circuits
US5798559A (en) * 1996-03-29 1998-08-25 Vlsi Technology, Inc. Integrated circuit structure having an air dielectric and dielectric support pillars

Also Published As

Publication number Publication date
US20020066932A1 (en) 2002-06-06
US6724055B2 (en) 2004-04-20
WO2000049642A2 (fr) 2000-08-24
JP4027039B2 (ja) 2007-12-26
JP2002537649A (ja) 2002-11-05
WO2000049642A3 (fr) 2001-03-15
DE19906291A1 (de) 2000-08-24

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