EP1145315A1 - Ensemble semi-conducteur integre verticalement - Google Patents

Ensemble semi-conducteur integre verticalement

Info

Publication number
EP1145315A1
EP1145315A1 EP99964451A EP99964451A EP1145315A1 EP 1145315 A1 EP1145315 A1 EP 1145315A1 EP 99964451 A EP99964451 A EP 99964451A EP 99964451 A EP99964451 A EP 99964451A EP 1145315 A1 EP1145315 A1 EP 1145315A1
Authority
EP
European Patent Office
Prior art keywords
carrier
semiconductor
main side
semiconductor chip
another
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99964451A
Other languages
German (de)
English (en)
Inventor
Michael Smola
Andreas Kux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1145315A1 publication Critical patent/EP1145315A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the thin grinding of semiconductor chips is becoming interesting, e.g. To be able to assemble stacks of several semiconductor chips on top of one another.
  • the semiconductor chips are ground so thin that a plated-through hole for connecting two or more layers is made possible.
  • the through-contacting of thin-ground semiconductor chips of this type can also be used in order to use the rear side of the semiconductor chips for circuit structures. This is of particular interest in the area of security and chip card ICs, since active protective structures against physical attacks can be implemented in this way (e.g. security plate on the back).
  • the object of the present invention is therefore to propose a semiconductor arrangement with thin-ground semiconductor chips that can be produced inexpensively.
  • a semiconductor arrangement with at least one semiconductor chip with a first and a second main side is proposed, the semiconductor chip having active structures on the first and the second main side which are connected to one another by means of connections passing through the semiconductor chip, the at least one semiconductor chip also having one of the main pages is arranged on a first main page of a carrier.
  • the carrier remains in the semiconductor arrangement, so that good manageability is ensured during manufacture. It is possible to arrange several chips on the first main side of the carrier.
  • at least one further semiconductor chip with active structures on its first and second main side is provided on the second, opposite, main side of the carrier, one of its main sides facing the carrier and the semiconductor chip on the first main side facing the wearer.
  • the semiconductor arrangement is provided in the form of a “sandwich” structure on both sides of the carrier. This enables a semiconductor arrangement that requires little space.
  • the carrier of the first and / or the second main side has contact connections which are connected to contacts of the semiconductor chips of the active structure.
  • the carrier can thus be used to accommodate simple passive connection structures, which on the one hand can reduce the complexity of the active layers and on the other hand can ensure high security against the separation of active structures and the carrier. It is thus possible to connect contacts of a semiconductor chip via the passive connection structure in the carrier or to connect contacts of different semiconductor chips via the passive connection structure in the carrier.
  • the connection structures can be provided in one or more levels in the carrier.
  • either the contact connections on the first main side of the carrier are connected to one another and / or the contact connections on the second main side of the carrier are connected to one another and / or the contact connections on the first and the second main side of the carrier are connected to one another via vias.
  • the electrical connection between two semiconductor chips, which are located on the opposite main sides of the carrier can be realized via vias in the carrier.
  • the interconnected contacts of the semiconductor chips are then advantageously located on the sides of the semiconductor chips that face the carrier. If the contacts between one of the semiconductor chips and the carrier were separated, the circuits implemented on the semiconductor chips would no longer be functional. This enables an examination of the lines that arise
  • the carrier has vias and non-conductive areas running at regular intervals from the first to the second main side.
  • the carrier is advantageously designed as a semiconductor wafer.
  • a semiconductor wafer serving as a carrier can be produced inexpensively and also has the advantage that the layer thickness can be selected in accordance with the mechanical requirements without the technological boundary conditions of the active ones
  • Layer can be influenced. Of course, this also applies to any other carrier, for example made of a plastic or a ceramic.
  • a semiconductor wafer as a carrier also has the advantage that it is particularly easy to connect to the semiconductor chips. In addition, the coefficients of thermal expansion are matched to one another.
  • FIG. 1 shows a first exemplary embodiment of the semiconductor arrangement according to the invention with a semiconductor chip on a main side of a carrier
  • Figure 2 shows a second embodiment of the semiconductor device according to the invention with semiconductor chips on both main sides of a carrier and
  • FIG. 3 shows a third exemplary embodiment of a semiconductor arrangement according to the invention, with a special one
  • FIG. 1 shows the simplest embodiment of a semiconductor arrangement according to the invention.
  • a semiconductor chip 1 is applied to a first main side 8 of a carrier 7.
  • the semiconductor chip 1 has an active structure 4 on a first main side 2.
  • An active structure 5 is also applied to a second main side 3.
  • the second main side 3 of the semiconductor chip 1 is connected to the first main side 8 of the carrier 7.
  • the active structures 4, 5 of the semiconductor chip 1 are connected to one another via a plurality of connections which extend from the first to the second main side 2, 3.
  • the semiconductor chip 1 is a thin-ground semiconductor chip which has a thickness of 15 to 20 ⁇ m, for example.
  • the carrier has a thickness of 100 ⁇ m, for example.
  • the layer thickness of the carrier can be chosen according to the mechanical requirements. Since the carrier 7 is not conductive, the technological boundary conditions of the active layer 5 need not be taken into account.
  • the carrier 7 in FIG. 1 also has a connection structure 18, which in the present example connects contacts (not shown) of the semiconductor chip 1 to one another.
  • the carrier 7 can have one or even more additional wiring layers. As a result, the complexity of the wiring in the active structure of the semiconductor chip 1 can be reduced.
  • the connection between the carrier 7 and the semiconductor chip 1 can take place, for example, by means of gluing or laminating. The connection can of course also be made in any other suitable manner.
  • FIG. 2 shows a second exemplary embodiment of the semiconductor arrangement according to the invention.
  • a semiconductor chip 1 and a semiconductor chip 10 are now respectively applied to a carrier 7 both on a first main side 8 and on a second main side 9.
  • the carrier 7 now has contact connections 15, 16 both on the first and on the second main side 8, 9.
  • the contact connections 15, 16 are connected to one another via vias and establish an electrical connection between the active structure 5 of the semiconductor chip 1 and the active structure 14 of the semiconductor chip 10.
  • the distance between the semiconductor chips 1, 10 and the carrier 7 due to the contact connections 15, 16 can be filled, for example, with an underfiller (not shown).
  • the semiconductor chip 1 and the semiconductor chip 10 are arranged on the carrier 7 in such a way that their edges lie opposite one another, that is to say the edges of the respective semiconductor chips are approximately flush with one another. In this way, a semiconductor arrangement with small external dimensions can be produced.
  • connection structures can be such that they connect the contacts of a plurality of semiconductor chips to one another on one main side of the carrier.
  • connection structure can also be such that, as shown in FIG. shows, only contacts of a semiconductor chip interconnected.
  • FIGS. 1 and 2 It is also conceivable to stack several of the semiconductor arrangements shown in FIGS. 1 and 2 on top of one another.
  • the active structures of two semiconductor chips would be connected to one another.
  • the layer sequence of such a semiconductor arrangement would then consist, for example, of a semiconductor chip carrier-semiconductor chip-semiconductor chip carrier-semiconductor chip. Since each of the “basic modules” (consisting of a carrier and a semiconductor chip or a semiconductor chip applied on both sides) has a high degree of stability in itself, it is now possible to connect the active structures of two semiconductor chips directly to one another.
  • FIG. 3 shows a third exemplary embodiment of the semiconductor arrangement according to the invention. This differs from the semiconductor arrangement shown in FIG. 2 only in that the carrier has a regular structure of vertical structure, that is to say from the first to the second main side 8, 9 of the carrier 7, alternating between conductive (through-contact 17) and non-conductive Areas. In this case, the contacts of the semiconductor chips and the contact connections on the carrier need not be aligned with one another.
  • a universal carrier can be used, which can be used regardless of the position of the contacts on the semiconductor chips. It should only be noted here that the corresponding minimum distances between the contacts on the semiconductor chips are observed, so that the
  • the invention enables a semiconductor arrangement with which semiconductor chips structured on both sides can be arranged one above the other, wherein simple and inexpensive handling is made possible in the production of the semiconductor arrangement.
  • the semiconductor arrangement according to the invention has good mechanical properties. At the same time, a small layer thickness is made possible due to the thin-ground semiconductor chips.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un ensemble semi-conducteur comportant au moins une puce de semi-conducteur présentant un premier côté principal et un second côté principal pourvus de structures actives qui sont reliées ensemble par des connexions traversant la puce de semi-conducteur. La ou les puces de semi-conducteur sont disposées de sorte qu'un de leurs côtés principaux repose sur un premier côté principal d'un support.
EP99964451A 1998-12-30 1999-12-21 Ensemble semi-conducteur integre verticalement Withdrawn EP1145315A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19860819 1998-12-30
DE19860819 1998-12-30
PCT/DE1999/004056 WO2000041241A1 (fr) 1998-12-30 1999-12-21 Ensemble semi-conducteur integre verticalement

Publications (1)

Publication Number Publication Date
EP1145315A1 true EP1145315A1 (fr) 2001-10-17

Family

ID=7893180

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99964451A Withdrawn EP1145315A1 (fr) 1998-12-30 1999-12-21 Ensemble semi-conducteur integre verticalement

Country Status (8)

Country Link
US (1) US6388320B2 (fr)
EP (1) EP1145315A1 (fr)
JP (1) JP2002534809A (fr)
KR (1) KR20010104320A (fr)
CN (1) CN1332888A (fr)
BR (1) BR9916684A (fr)
RU (1) RU2213391C2 (fr)
WO (1) WO2000041241A1 (fr)

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Publication number Priority date Publication date Assignee Title
JP3910493B2 (ja) * 2002-06-14 2007-04-25 新光電気工業株式会社 半導体装置及びその製造方法
CN100511672C (zh) * 2004-03-25 2009-07-08 日本电气株式会社 芯片层叠型半导体装置
US7511359B2 (en) * 2005-12-29 2009-03-31 Intel Corporation Dual die package with high-speed interconnect
FR2901636A1 (fr) * 2006-05-24 2007-11-30 Commissariat Energie Atomique Connecteur a vias isoles
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US7791175B2 (en) * 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8218329B2 (en) * 2010-03-29 2012-07-10 Xerox Corporation Back-to-back package accomplishing short signal path lengths
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same

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KR900008647B1 (ko) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
US4774632A (en) * 1987-07-06 1988-09-27 General Electric Company Hybrid integrated circuit chip package
US5382827A (en) * 1992-08-07 1995-01-17 Fujitsu Limited Functional substrates for packaging semiconductor chips
JP2001523390A (ja) * 1994-12-22 2001-11-20 ベネディクト・ジー・ペース 反転型のチップが接合された高い実装効率を有するモジュール
JP2905736B2 (ja) * 1995-12-18 1999-06-14 株式会社エイ・ティ・アール光電波通信研究所 半導体装置
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Also Published As

Publication number Publication date
BR9916684A (pt) 2001-09-25
RU2213391C2 (ru) 2003-09-27
US6388320B2 (en) 2002-05-14
WO2000041241A1 (fr) 2000-07-13
JP2002534809A (ja) 2002-10-15
CN1332888A (zh) 2002-01-23
US20020003297A1 (en) 2002-01-10
KR20010104320A (ko) 2001-11-24

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