EP1145286A3 - Procede de structuration d'une couche metallifere - Google Patents
Procede de structuration d'une couche metallifereInfo
- Publication number
- EP1145286A3 EP1145286A3 EP99964395A EP99964395A EP1145286A3 EP 1145286 A3 EP1145286 A3 EP 1145286A3 EP 99964395 A EP99964395 A EP 99964395A EP 99964395 A EP99964395 A EP 99964395A EP 1145286 A3 EP1145286 A3 EP 1145286A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- structuring
- metalliferous layer
- metalliferous
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19856082 | 1998-12-04 | ||
DE19856082A DE19856082C1 (de) | 1998-12-04 | 1998-12-04 | Verfahren zum Strukturieren einer metallhaltigen Schicht |
PCT/DE1999/003876 WO2000034985A2 (fr) | 1998-12-04 | 1999-12-03 | Procede de structuration d'une couche metallifere |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1145286A2 EP1145286A2 (fr) | 2001-10-17 |
EP1145286A3 true EP1145286A3 (fr) | 2002-04-24 |
Family
ID=7890037
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99964395A Withdrawn EP1145286A3 (fr) | 1998-12-04 | 1999-12-03 | Procede de structuration d'une couche metallifere |
Country Status (6)
Country | Link |
---|---|
US (1) | US6511918B2 (fr) |
EP (1) | EP1145286A3 (fr) |
JP (1) | JP2002536817A (fr) |
KR (1) | KR100417724B1 (fr) |
DE (1) | DE19856082C1 (fr) |
WO (1) | WO2000034985A2 (fr) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6818493B2 (en) * | 2001-07-26 | 2004-11-16 | Motorola, Inc. | Selective metal oxide removal performed in a reaction chamber in the absence of RF activation |
US7358171B2 (en) * | 2001-08-30 | 2008-04-15 | Micron Technology, Inc. | Method to chemically remove metal impurities from polycide gate sidewalls |
JP4358556B2 (ja) * | 2003-05-30 | 2009-11-04 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
WO2004109772A2 (fr) * | 2003-05-30 | 2004-12-16 | Tokyo Electron Limited | Procede et systeme de gravure d'une matiere dielectrique a k eleve |
KR100541152B1 (ko) * | 2003-07-18 | 2006-01-11 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선층 형성 방법 |
DE10338422B4 (de) * | 2003-08-18 | 2007-08-16 | Infineon Technologies Ag | Selektiver Plasmaätzprozess zur Aluminiumoxid-Strukturierung und dessen Verwendung |
US7964512B2 (en) * | 2005-08-22 | 2011-06-21 | Applied Materials, Inc. | Method for etching high dielectric constant materials |
JP4853057B2 (ja) * | 2006-03-09 | 2012-01-11 | セイコーエプソン株式会社 | 強誘電体メモリ装置の製造方法 |
JP5028829B2 (ja) * | 2006-03-09 | 2012-09-19 | セイコーエプソン株式会社 | 強誘電体メモリ装置の製造方法 |
US7780862B2 (en) * | 2006-03-21 | 2010-08-24 | Applied Materials, Inc. | Device and method for etching flash memory gate stacks comprising high-k dielectric |
US8722547B2 (en) * | 2006-04-20 | 2014-05-13 | Applied Materials, Inc. | Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries |
CN117238763A (zh) * | 2023-08-30 | 2023-12-15 | 上海稷以科技有限公司 | 基于钛衬底的二氧化硅刻蚀方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4026742A (en) * | 1972-11-22 | 1977-05-31 | Katsuhiro Fujino | Plasma etching process for making a microcircuit device |
US3923568A (en) * | 1974-01-14 | 1975-12-02 | Int Plasma Corp | Dry plasma process for etching noble metal |
US3951709A (en) * | 1974-02-28 | 1976-04-20 | Lfe Corporation | Process and material for semiconductor photomask fabrication |
DE2738839A1 (de) * | 1977-08-29 | 1979-03-15 | Siemens Ag | Plasma-aetzverfahren fuer chrom- schichten |
US4432132A (en) * | 1981-12-07 | 1984-02-21 | Bell Telephone Laboratories, Incorporated | Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features |
US4568410A (en) * | 1984-12-20 | 1986-02-04 | Motorola, Inc. | Selective plasma etching of silicon nitride in the presence of silicon oxide |
JP3160336B2 (ja) * | 1991-12-18 | 2001-04-25 | 株式会社東芝 | 半導体装置の製造方法 |
US5496437A (en) * | 1993-06-10 | 1996-03-05 | Ceram Incorporated | Reactive ion etching of lead zirconate titanate and ruthenium oxide thin films |
JP3238563B2 (ja) | 1994-03-16 | 2001-12-17 | 株式会社東芝 | 半導体装置の製造方法 |
JP2956485B2 (ja) * | 1994-09-07 | 1999-10-04 | 日本電気株式会社 | 半導体装置の製造方法 |
US5866484A (en) * | 1996-07-09 | 1999-02-02 | Nippon Steel Corporation | Semiconductor device and process of producing same |
JPH10178095A (ja) * | 1996-07-09 | 1998-06-30 | Nippon Steel Corp | 半導体装置及びその製造方法 |
US6350699B1 (en) * | 2000-05-30 | 2002-02-26 | Sharp Laboratories Of America, Inc. | Method for anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry |
-
1998
- 1998-12-04 DE DE19856082A patent/DE19856082C1/de not_active Expired - Fee Related
-
1999
- 1999-12-03 EP EP99964395A patent/EP1145286A3/fr not_active Withdrawn
- 1999-12-03 WO PCT/DE1999/003876 patent/WO2000034985A2/fr active IP Right Grant
- 1999-12-03 KR KR10-2001-7006970A patent/KR100417724B1/ko not_active IP Right Cessation
- 1999-12-03 JP JP2000587356A patent/JP2002536817A/ja active Pending
-
2001
- 2001-06-04 US US09/873,229 patent/US6511918B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR20010086078A (ko) | 2001-09-07 |
WO2000034985A2 (fr) | 2000-06-15 |
KR100417724B1 (ko) | 2004-02-11 |
JP2002536817A (ja) | 2002-10-29 |
US6511918B2 (en) | 2003-01-28 |
WO2000034985A3 (fr) | 2002-02-14 |
US20020011461A1 (en) | 2002-01-31 |
DE19856082C1 (de) | 2000-07-27 |
EP1145286A2 (fr) | 2001-10-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
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XX | Miscellaneous (additional remarks) |
Free format text: DERZEIT SIND DIE WIPO-PUBLIKATIONSDATEN A3 NICHT VERFUEGBAR. |
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PUAK | Availability of information related to the publication of the international search report |
Free format text: ORIGINAL CODE: 0009015 |
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AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
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RIC1 | Information provided on ipc code assigned before grant |
Free format text: 7H 01L 21/311 A, 7H 01L 21/3213 B |
|
17P | Request for examination filed |
Effective date: 20010430 |
|
RBV | Designated contracting states (corrected) |
Designated state(s): DE FR GB IE IT |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: QIMONDA AG |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Effective date: 20111118 |