EP1145286A3 - Method for structuring a metalliferous layer - Google Patents

Method for structuring a metalliferous layer

Info

Publication number
EP1145286A3
EP1145286A3 EP99964395A EP99964395A EP1145286A3 EP 1145286 A3 EP1145286 A3 EP 1145286A3 EP 99964395 A EP99964395 A EP 99964395A EP 99964395 A EP99964395 A EP 99964395A EP 1145286 A3 EP1145286 A3 EP 1145286A3
Authority
EP
European Patent Office
Prior art keywords
structuring
metalliferous layer
metalliferous
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99964395A
Other languages
German (de)
French (fr)
Other versions
EP1145286A2 (en
Inventor
Stephan Wege
Kerstin Krahl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1145286A2 publication Critical patent/EP1145286A2/en
Publication of EP1145286A3 publication Critical patent/EP1145286A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
EP99964395A 1998-12-04 1999-12-03 Method for structuring a metalliferous layer Withdrawn EP1145286A3 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19856082A DE19856082C1 (en) 1998-12-04 1998-12-04 Process for structuring a metal-containing layer
DE19856082 1998-12-04
PCT/DE1999/003876 WO2000034985A2 (en) 1998-12-04 1999-12-03 Method for structuring a metalliferous layer

Publications (2)

Publication Number Publication Date
EP1145286A2 EP1145286A2 (en) 2001-10-17
EP1145286A3 true EP1145286A3 (en) 2002-04-24

Family

ID=7890037

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99964395A Withdrawn EP1145286A3 (en) 1998-12-04 1999-12-03 Method for structuring a metalliferous layer

Country Status (6)

Country Link
US (1) US6511918B2 (en)
EP (1) EP1145286A3 (en)
JP (1) JP2002536817A (en)
KR (1) KR100417724B1 (en)
DE (1) DE19856082C1 (en)
WO (1) WO2000034985A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818493B2 (en) * 2001-07-26 2004-11-16 Motorola, Inc. Selective metal oxide removal performed in a reaction chamber in the absence of RF activation
US7358171B2 (en) * 2001-08-30 2008-04-15 Micron Technology, Inc. Method to chemically remove metal impurities from polycide gate sidewalls
EP1629529A2 (en) * 2003-05-30 2006-03-01 Tokyo Electron Limited Method and system for etching a high-k dielectric material
JP4358556B2 (en) * 2003-05-30 2009-11-04 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
KR100541152B1 (en) * 2003-07-18 2006-01-11 매그나칩 반도체 유한회사 Method of forming metal line layer in semiconductor device
DE10338422B4 (en) * 2003-08-18 2007-08-16 Infineon Technologies Ag Selective plasma etching process for alumina structuring and its use
US7964512B2 (en) * 2005-08-22 2011-06-21 Applied Materials, Inc. Method for etching high dielectric constant materials
JP4853057B2 (en) * 2006-03-09 2012-01-11 セイコーエプソン株式会社 Method for manufacturing ferroelectric memory device
JP5028829B2 (en) * 2006-03-09 2012-09-19 セイコーエプソン株式会社 Method for manufacturing ferroelectric memory device
US7780862B2 (en) * 2006-03-21 2010-08-24 Applied Materials, Inc. Device and method for etching flash memory gate stacks comprising high-k dielectric
US8722547B2 (en) * 2006-04-20 2014-05-13 Applied Materials, Inc. Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026742A (en) * 1972-11-22 1977-05-31 Katsuhiro Fujino Plasma etching process for making a microcircuit device
US3923568A (en) * 1974-01-14 1975-12-02 Int Plasma Corp Dry plasma process for etching noble metal
US3951709A (en) * 1974-02-28 1976-04-20 Lfe Corporation Process and material for semiconductor photomask fabrication
DE2738839A1 (en) * 1977-08-29 1979-03-15 Siemens Ag Plasma etching metal coated substrates - by using a reaction gas composed of oxygen and carbon tetra:fluoride
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4568410A (en) * 1984-12-20 1986-02-04 Motorola, Inc. Selective plasma etching of silicon nitride in the presence of silicon oxide
JP3160336B2 (en) * 1991-12-18 2001-04-25 株式会社東芝 Method for manufacturing semiconductor device
US5496437A (en) * 1993-06-10 1996-03-05 Ceram Incorporated Reactive ion etching of lead zirconate titanate and ruthenium oxide thin films
JP3238563B2 (en) 1994-03-16 2001-12-17 株式会社東芝 Method for manufacturing semiconductor device
JP2956485B2 (en) * 1994-09-07 1999-10-04 日本電気株式会社 Method for manufacturing semiconductor device
US5866484A (en) * 1996-07-09 1999-02-02 Nippon Steel Corporation Semiconductor device and process of producing same
JPH10178095A (en) * 1996-07-09 1998-06-30 Nippon Steel Corp Semiconductor device and fabrication thereof
US6350699B1 (en) * 2000-05-30 2002-02-26 Sharp Laboratories Of America, Inc. Method for anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry

Also Published As

Publication number Publication date
US6511918B2 (en) 2003-01-28
KR20010086078A (en) 2001-09-07
KR100417724B1 (en) 2004-02-11
WO2000034985A3 (en) 2002-02-14
JP2002536817A (en) 2002-10-29
DE19856082C1 (en) 2000-07-27
US20020011461A1 (en) 2002-01-31
EP1145286A2 (en) 2001-10-17
WO2000034985A2 (en) 2000-06-15

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