EP1081572B1 - Versorgungsschaltung mit Spannungswähler - Google Patents

Versorgungsschaltung mit Spannungswähler Download PDF

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Publication number
EP1081572B1
EP1081572B1 EP00410109A EP00410109A EP1081572B1 EP 1081572 B1 EP1081572 B1 EP 1081572B1 EP 00410109 A EP00410109 A EP 00410109A EP 00410109 A EP00410109 A EP 00410109A EP 1081572 B1 EP1081572 B1 EP 1081572B1
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EP
European Patent Office
Prior art keywords
transistor
power supply
voltage
supply
supply circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP00410109A
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English (en)
French (fr)
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EP1081572A1 (de
Inventor
Claude Renous
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load

Definitions

  • the present invention relates to circuits supply, and in particular the supply circuits which receive multiple supply voltages and which select the highest supply voltage.
  • Such circuits are used, for example, in a rechargeable battery to power the device, if applicable, from the battery or from a power source external.
  • Figure 1 shows a power circuit conventional receiving two supply voltages V1 and V2 out of two respective supply lines L1 and L2, and providing a voltage Vdd on an output node S.
  • the two lines two are connected to the output node P channel MOS transistors (PMOS), T1 and T2 respectively.
  • a comparator A1 has two inputs connected respectively to the two supply lines so that the output of comparator A1 is at a low level when the voltage V1 is greater than the voltage V2 and at a high level otherwise.
  • the exit of comparator A1 is directly connected to the grid of transistor T1, and is connected to the gate of transistor T2 by through an inverter I1.
  • Such supply circuits are used when we want to obtain a low voltage drop between voltage V1 or V2 and the voltage Vdd. In cases where one can admit a significant voltage drop, we use diodes instead of transistors T1 and T2.
  • FIG. 2 represents the evolution of the gate voltages V G1 and V G2 of the transistors T1 and T2 for an example of relative variation of the two supply voltages V1 and V2.
  • the voltage V1 is constant, while the voltage V2 crosses the voltage V1 by decreasing, then increasing. It is assumed that the comparator A1 and the inverter I1 are both supplied between the voltage Vdd and the ground.
  • the voltage V A1 supplied by the comparator is equal to the voltage Vdd.
  • the gates G1 and G2 are respectively at the voltage Vdd and at ground. It follows that the transistor T2 conducts and that the transistor T1 is blocked, the transistor T2 transmitting the voltage V2 on the output node S.
  • the voltage V A1 supplied by the comparator is grounded, where it follows that the transistor T2 is blocked and that the transistor T1 conducts, the transistor T1 transmitting the voltage V1 on the output node S.
  • the range ⁇ ⁇ V is a range where the comparator, by nature imperfect, behaves linearly.
  • the comparator behaves linearly between instants t1 and t2 where the voltage V2 gradually decreases from the voltage V1 + ⁇ V to the voltage V1- ⁇ V and the voltage V G1 progressively changes from the voltage Vdd to ground.
  • the inverter I1 comprises a PMOS transistor and an N channel MOS transistor (NMOS).
  • the threshold voltage of the PMOS transistor of the inverter I1 is called V TH , which voltage is also that of the PMOS transistors T1 and T2.
  • the threshold voltage of the NMOS transistor is called V TL .
  • the voltage V G1 is equal to the voltage Vdd-V TH , and at an instant t4 the voltage V G1 reaches the voltage V TL .
  • the gate voltage V G2 at the output of the inverter I1, progressively changes between a zero level at time t3 and the level Vdd at time t4.
  • the transistor T1 begins to conduct when its gate voltage V G1 reaches the voltage Vdd-V TH , that is to say at time t3.
  • the gate voltage V G2 reaches the voltage Vdd-V TH .
  • the transistor T2 stops driving at time t5.
  • the sources supply producing the voltages V1 and V2 are short-circuited, which is not desirable.
  • the short circuit of power sources lowers the supply voltage the higher at the other supply voltage and the comparator A1 can no longer determine which of the voltages is the highest. The selection circuit power supply is then blocked in an intermediate state and no longer performs its function properly.
  • EP 0838745 describes a voltage regulator comprising means (11) for automatically selecting the highest supply voltage (VM, VL) among voltages present at two input terminals (EM, EL). This document does not plan to avoid a short circuit of the lines when the two voltages present at the terminals input are equal to each other and greater than the voltage of the output terminal.
  • An object of the present invention is to provide a circuit for selecting the higher of two voltages or more, capable of operating without short circuiting power lines.
  • the present invention provides a supply circuit receiving multiple supply voltages on supply lines respective, each of which is connected to a respective switch, at least one of the switches being a first MOS transistor of a first type of conductivity, connected between the line associated power supply and a common output terminal, which includes, for said at least one switch: a second transistor, of the first type of conductivity, connected between the gate of the first transistor and a supply node maintained at the highest of the other supply voltages, a third transistor, of a second type of conductivity, less conductive to the on state that the second transistor, connected between the gate of the first transistor and a reference potential, and a fourth transistor, of the first type of conductivity, the source is connected to the supply line associated with the switch and whose drain is connected to the reference potential through a power source, and at the grids of second, third and fourth transistors.
  • said current source is a fifth transistor, from the second type of conductivity, the grid of which is connected to said node Power.
  • the supply circuit has two supply lines and two respective switches, the power supply node associated with a switch being connected directly to the power line associated with the other switch.
  • the supply circuit comprises three supply lines, a sixth transistor connected between the third line and the power node and whose grid is connected to the second supply line, and a seventh transistor connected between the second supply line and the power node and whose grid is connected to the third feeder.
  • At least one of the switches is a diode.
  • the second transistor has a width / length ratio of 20/2
  • the third transistor has a W / L ratio of 3/25.
  • the fourth transistor has a W / L ratio of 40/2
  • the fifth transistor has a W / L ratio of 3/50.
  • the first and second types of conductivity are respectively P and N.
  • a comparator is used separate to control each of the T1 and T2 transistors, the characteristics of each of the comparators being chosen from so as to eliminate the range of simultaneous conduction.
  • FIG. 3 represents a supply circuit according to the present invention, receiving two supply voltages V1 and V2 on two respective supply lines L1 and L2.
  • the supply lines are, as in Figure 1, respectively connected to an output node S by PMOS transistors T1 and T2.
  • Transistors T1 and T2 are controlled by two comparators respective A1 and A2 of particular structure.
  • Comparator A1 includes a PMOS transistor T3 whose source is connected to the line L2, and whose drain, constituting the output of the comparator, is connected to grid G1.
  • the drain of an NMOS transistor T4 is connected to grid G1 and its source is connected to a potential of reference, here the mass.
  • the grids of transistors T3 and T4 are connected to the drain and the gate of a PMOS transistor T5 connected as a diode whose source is connected to line L1 and whose the drain is connected to ground via a source of current R1.
  • the comparator A2 associated with the transistor T2 comprises T6, T7 and T8 transistors and a homologous R2 current source respective transistors T3, T4 and T5 and the source of current R1.
  • the sources of transistors T6 and T8 are connected lines L1 and L2 respectively, i.e. inverted with respect to the connection of their T3 counterparts and T5.
  • comparator A1 is behaves like a conventional comparator of the type input by sources.
  • the output of comparator A1 is brought to a near voltage of voltage V2 and transistor T1 is open.
  • the comparator output is brought to a voltage close to ground and transistor T1 is closed.
  • the comparator A2 has homologous functioning.
  • a solution to obtain a transistor T4 aux desired characteristics is to lengthen its grid relative to the gate of transistor T3.
  • the transistor T7 of the comparator A2 has the same properties as the transistor T4, so that the operation of comparator A2 is homologous to that of comparator A1.
  • the transistors T1 and T2 are both open when the voltages V1 and V2 are equal and there is no simultaneous conduction.
  • the present invention can also be adapted to a power circuit receiving more than two voltages Power.
  • Figure 4 schematically represents a circuit receiving three voltages V1, V2 and V3 respectively out of three supply lines L1, L2 and L3.
  • Line L1 is connected to the terminal S by a PMOS transistor T1 controlled by a comparator A1 like the one in figure 3, connected to compare the voltage V1 at a voltage VN present on a node N.
  • the node N is connected to lines L3 and L2 by two PMOS transistors T10 and T11 respective whose grids are respectively connected to lines L2 and L3. With this configuration, node N receives the higher voltages V2 and V3.
  • To prevent conduction simultaneous transistors T10 and T11 does not cause problems mentioned above, these are chosen very resistive.
  • Figure 4 we have only shown Figure 4 as comparator A1.
  • Two A2 peer comparators and A3 can be connected to control two T2 transistors and T3 on lines L2 and L3.
  • comparator A1 The operation of comparator A1 is substantially the same as that described in relation to FIG. 3. Depending on whether the voltage V1 is lower or higher than voltage VN, the transistor T1 is open or closed. Likewise, when the voltage V1 is equal to the voltage VN, the transistor T1 is open so avoid simultaneous conduction with possible transistors homologous to transistor T1 on lines L2 and L3.
  • the current source R1 of Figure 3 is replaced here by an NMOS transistor T9 whose grid is controlled by the voltage VN. This reduces the current consumption of comparator A1. If the voltage V1 is the maximum voltage, the voltages V2 and V3 (therefore VN) are canceled in practice, which causes the blocking of transistor T4 and therefore the cancellation of the current flowing through it, which is not the case with a conventional R1 current source such as a resistance.
  • transistor T9 is intended to be crossed by a current of the same order as the current which crosses transistor T4.
  • the gate of transistor T9 will have preferably a W / L ratio of 3/50.
  • the present invention is capable of various variants and modifications which will appear to the man of the job.
  • one of the supply voltages is relatively high compared to the voltage drop in a diode, we can replace the transistor connecting this voltage supply to the output terminal S by a diode such as the diode D3 shown in Figure 4.
  • a supply circuit has been described in FIG. 4 receiving three supply voltages, but those skilled in the art will easily adapt the present invention to a circuit supply receiving more than three supply voltages.
  • the present application has described supply circuits receiving supply voltages positive, in which the supply lines are connected to the output terminal by PMOS transistors.
  • the skilled person will easily adapt the present invention to a circuit supply receiving negative supply voltages, in which the supply lines are connected to the terminal output by NMOS transistors.
  • the transistors PMOS and NMOS in Figures 3 and 4 will be replaced by transistors of the opposite type.

Claims (8)

  1. Eine Leistungsversorgungsschaltung, die mehrere Versorgungsspannungen (V1, V2) auf entsprechenden Leistungsversorgungsleitungen (L1, L2) empfängt, wobei jede der Leistungsversorgungsleitungen mit einem entsprechenden Schalter (T1, T2) verbunden ist, wobei ein erster Schalter und/oder ein zweiter Schalter aus einem erstem MOS Transistor (T1, T2) eines ersten Leitfähigkeitstyp ausgebildet ist, und zwar verbunden zwischen der zugehörigen Leistungsversorgungsleitung (L1) und einem gemeinsamen Ausgangsanschluss (S), wobei
       jeder erste Transistor durch einen Komparator (A1, A2) gesteuert wird, wobei ferner Folgendes vorgesehen ist:
    ein zweiter Transistor (T3) des ersten Leitfähigkeitstyps, verbunden zwischen dem Gate des ersten Transistors und einem Leistungsversorgungsknoten (N), der auf der höchsten der anderen Versorgungsspannungen gehalten wird,
    ein dritter Transistor (T4) eines zweiten Leitfähigkeitstyps, der in dem Ein-Zustand weniger leitfähig ist, als der zweite Transistor, und zwar geschaltet zwischen das Gate des ersten Transistors und ein Bezugspotential, und
    ein vierter Transistor (T5) des ersten Leitfähigkeitstyps, dessen Source mit der Leistungsversorgungsleitung assoziiert mit dem Schalter verbunden ist und dessen Drain mit dem Bezugspotential über eine Stromquelle (R1) verbunden ist und ferner mit den Gates der zweiten, dritten und vierten Transistoren.
  2. Leistungsversorgungsschaltung nach Anspruch 1, dadurch gekennzeichnet, dass die erwähnte Stromquelle einen fünften Transistor (T9) des zweiten Leitfähigkeitstyps ist, wobei dessen Gate mit dem erwähnten Leistungsversorgungsknoten (N) verbunden ist.
  3. Leistungsversorgungsschaltung nach Anspruch 2, dadurch gekennzeichnet, dass zwei Leistungsversorgungsleitungen (L1, L2) und zwei entsprechende Schalter (T1, T2) vorgesehen sind, wobei der Leistungsversorgungsknoten assoziiert mit einem der Schalter direkt mit der Leistungsversorgungsleitung assoziiert mit dem anderen Schalter verbunden ist.
  4. Leistungsversorgungsschaltung nach Anspruch 2, dadurch gekennzeichnet, dass sie Folgendes aufweist:
    drei Leistungsversorgungsleitungen (L1, L2, L3), und dass
    jeder Steuerkomparator eines ersten Transistors assoziiert mit einer ersten Leistungsversorgungsleitung Folgendes aufweist:
    einen sechsten Transistor (T10) geschaltet zwischen eine zweite Leistungsversorgungsleitung (L3) und den Leistungsversorgungsknoten und mit seinem Gate verbunden, mit einer dritten Leistungsversorgungsleitung (L2), und
    einen siebten Transistor (T11 ) verbunden zwischen der dritten Leistungsversorgungsleitung (L2) und dem Leistungsversorgungsknoten und mit seinem Gate verbunden mit der zweiten Leistungsversorgungsleitung (L3)
  5. Leistungsversorgungsschaltung nach Anspruch 4, dadurch gekennzeichnet, dass mindestens einer der Schalter eine Diode (D3) ist.
  6. Leistungsversorgungsschaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass
       der zweite Transistor (T3) ein Breiten- zu Längenverhältnis (W/L) von 20/2 besitzt und dass,
       der dritte Transistor (T4) ein W/L-Verhältnis von 3/25 besitzt.
  7. Leistungsversorgungsschaltung nach Anspruch 6, dadurch gekennzeichnet, dass der vierte Transistor (T5) ein W/L-Verhältnis von 40/2 besitzt, dass
       der fünfte Transistor (T9) ein W/L-Verhältnis von 3/50 besitzt.
  8. Leistungsversorgungsschaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die ersten und zweiten Leitfähigkeitstypen P bzw. N sind.
EP00410109A 1999-08-31 2000-08-30 Versorgungsschaltung mit Spannungswähler Expired - Lifetime EP1081572B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9911033 1999-08-31
FR9911033A FR2798014B1 (fr) 1999-08-31 1999-08-31 Circuit d'alimentation a selecteur de tension

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EP1081572A1 EP1081572A1 (de) 2001-03-07
EP1081572B1 true EP1081572B1 (de) 2004-11-03

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EP (1) EP1081572B1 (de)
DE (1) DE60015464D1 (de)
FR (1) FR2798014B1 (de)

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Also Published As

Publication number Publication date
US6566935B1 (en) 2003-05-20
FR2798014B1 (fr) 2002-03-29
FR2798014A1 (fr) 2001-03-02
EP1081572A1 (de) 2001-03-07
DE60015464D1 (de) 2004-12-09

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