EP1081572B1 - Supply circuit with voltage selector - Google Patents

Supply circuit with voltage selector Download PDF

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Publication number
EP1081572B1
EP1081572B1 EP00410109A EP00410109A EP1081572B1 EP 1081572 B1 EP1081572 B1 EP 1081572B1 EP 00410109 A EP00410109 A EP 00410109A EP 00410109 A EP00410109 A EP 00410109A EP 1081572 B1 EP1081572 B1 EP 1081572B1
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EP
European Patent Office
Prior art keywords
transistor
power supply
voltage
supply
supply circuit
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EP00410109A
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German (de)
French (fr)
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EP1081572A1 (en
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Claude Renous
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load

Definitions

  • the present invention relates to circuits supply, and in particular the supply circuits which receive multiple supply voltages and which select the highest supply voltage.
  • Such circuits are used, for example, in a rechargeable battery to power the device, if applicable, from the battery or from a power source external.
  • Figure 1 shows a power circuit conventional receiving two supply voltages V1 and V2 out of two respective supply lines L1 and L2, and providing a voltage Vdd on an output node S.
  • the two lines two are connected to the output node P channel MOS transistors (PMOS), T1 and T2 respectively.
  • a comparator A1 has two inputs connected respectively to the two supply lines so that the output of comparator A1 is at a low level when the voltage V1 is greater than the voltage V2 and at a high level otherwise.
  • the exit of comparator A1 is directly connected to the grid of transistor T1, and is connected to the gate of transistor T2 by through an inverter I1.
  • Such supply circuits are used when we want to obtain a low voltage drop between voltage V1 or V2 and the voltage Vdd. In cases where one can admit a significant voltage drop, we use diodes instead of transistors T1 and T2.
  • FIG. 2 represents the evolution of the gate voltages V G1 and V G2 of the transistors T1 and T2 for an example of relative variation of the two supply voltages V1 and V2.
  • the voltage V1 is constant, while the voltage V2 crosses the voltage V1 by decreasing, then increasing. It is assumed that the comparator A1 and the inverter I1 are both supplied between the voltage Vdd and the ground.
  • the voltage V A1 supplied by the comparator is equal to the voltage Vdd.
  • the gates G1 and G2 are respectively at the voltage Vdd and at ground. It follows that the transistor T2 conducts and that the transistor T1 is blocked, the transistor T2 transmitting the voltage V2 on the output node S.
  • the voltage V A1 supplied by the comparator is grounded, where it follows that the transistor T2 is blocked and that the transistor T1 conducts, the transistor T1 transmitting the voltage V1 on the output node S.
  • the range ⁇ ⁇ V is a range where the comparator, by nature imperfect, behaves linearly.
  • the comparator behaves linearly between instants t1 and t2 where the voltage V2 gradually decreases from the voltage V1 + ⁇ V to the voltage V1- ⁇ V and the voltage V G1 progressively changes from the voltage Vdd to ground.
  • the inverter I1 comprises a PMOS transistor and an N channel MOS transistor (NMOS).
  • the threshold voltage of the PMOS transistor of the inverter I1 is called V TH , which voltage is also that of the PMOS transistors T1 and T2.
  • the threshold voltage of the NMOS transistor is called V TL .
  • the voltage V G1 is equal to the voltage Vdd-V TH , and at an instant t4 the voltage V G1 reaches the voltage V TL .
  • the gate voltage V G2 at the output of the inverter I1, progressively changes between a zero level at time t3 and the level Vdd at time t4.
  • the transistor T1 begins to conduct when its gate voltage V G1 reaches the voltage Vdd-V TH , that is to say at time t3.
  • the gate voltage V G2 reaches the voltage Vdd-V TH .
  • the transistor T2 stops driving at time t5.
  • the sources supply producing the voltages V1 and V2 are short-circuited, which is not desirable.
  • the short circuit of power sources lowers the supply voltage the higher at the other supply voltage and the comparator A1 can no longer determine which of the voltages is the highest. The selection circuit power supply is then blocked in an intermediate state and no longer performs its function properly.
  • EP 0838745 describes a voltage regulator comprising means (11) for automatically selecting the highest supply voltage (VM, VL) among voltages present at two input terminals (EM, EL). This document does not plan to avoid a short circuit of the lines when the two voltages present at the terminals input are equal to each other and greater than the voltage of the output terminal.
  • An object of the present invention is to provide a circuit for selecting the higher of two voltages or more, capable of operating without short circuiting power lines.
  • the present invention provides a supply circuit receiving multiple supply voltages on supply lines respective, each of which is connected to a respective switch, at least one of the switches being a first MOS transistor of a first type of conductivity, connected between the line associated power supply and a common output terminal, which includes, for said at least one switch: a second transistor, of the first type of conductivity, connected between the gate of the first transistor and a supply node maintained at the highest of the other supply voltages, a third transistor, of a second type of conductivity, less conductive to the on state that the second transistor, connected between the gate of the first transistor and a reference potential, and a fourth transistor, of the first type of conductivity, the source is connected to the supply line associated with the switch and whose drain is connected to the reference potential through a power source, and at the grids of second, third and fourth transistors.
  • said current source is a fifth transistor, from the second type of conductivity, the grid of which is connected to said node Power.
  • the supply circuit has two supply lines and two respective switches, the power supply node associated with a switch being connected directly to the power line associated with the other switch.
  • the supply circuit comprises three supply lines, a sixth transistor connected between the third line and the power node and whose grid is connected to the second supply line, and a seventh transistor connected between the second supply line and the power node and whose grid is connected to the third feeder.
  • At least one of the switches is a diode.
  • the second transistor has a width / length ratio of 20/2
  • the third transistor has a W / L ratio of 3/25.
  • the fourth transistor has a W / L ratio of 40/2
  • the fifth transistor has a W / L ratio of 3/50.
  • the first and second types of conductivity are respectively P and N.
  • a comparator is used separate to control each of the T1 and T2 transistors, the characteristics of each of the comparators being chosen from so as to eliminate the range of simultaneous conduction.
  • FIG. 3 represents a supply circuit according to the present invention, receiving two supply voltages V1 and V2 on two respective supply lines L1 and L2.
  • the supply lines are, as in Figure 1, respectively connected to an output node S by PMOS transistors T1 and T2.
  • Transistors T1 and T2 are controlled by two comparators respective A1 and A2 of particular structure.
  • Comparator A1 includes a PMOS transistor T3 whose source is connected to the line L2, and whose drain, constituting the output of the comparator, is connected to grid G1.
  • the drain of an NMOS transistor T4 is connected to grid G1 and its source is connected to a potential of reference, here the mass.
  • the grids of transistors T3 and T4 are connected to the drain and the gate of a PMOS transistor T5 connected as a diode whose source is connected to line L1 and whose the drain is connected to ground via a source of current R1.
  • the comparator A2 associated with the transistor T2 comprises T6, T7 and T8 transistors and a homologous R2 current source respective transistors T3, T4 and T5 and the source of current R1.
  • the sources of transistors T6 and T8 are connected lines L1 and L2 respectively, i.e. inverted with respect to the connection of their T3 counterparts and T5.
  • comparator A1 is behaves like a conventional comparator of the type input by sources.
  • the output of comparator A1 is brought to a near voltage of voltage V2 and transistor T1 is open.
  • the comparator output is brought to a voltage close to ground and transistor T1 is closed.
  • the comparator A2 has homologous functioning.
  • a solution to obtain a transistor T4 aux desired characteristics is to lengthen its grid relative to the gate of transistor T3.
  • the transistor T7 of the comparator A2 has the same properties as the transistor T4, so that the operation of comparator A2 is homologous to that of comparator A1.
  • the transistors T1 and T2 are both open when the voltages V1 and V2 are equal and there is no simultaneous conduction.
  • the present invention can also be adapted to a power circuit receiving more than two voltages Power.
  • Figure 4 schematically represents a circuit receiving three voltages V1, V2 and V3 respectively out of three supply lines L1, L2 and L3.
  • Line L1 is connected to the terminal S by a PMOS transistor T1 controlled by a comparator A1 like the one in figure 3, connected to compare the voltage V1 at a voltage VN present on a node N.
  • the node N is connected to lines L3 and L2 by two PMOS transistors T10 and T11 respective whose grids are respectively connected to lines L2 and L3. With this configuration, node N receives the higher voltages V2 and V3.
  • To prevent conduction simultaneous transistors T10 and T11 does not cause problems mentioned above, these are chosen very resistive.
  • Figure 4 we have only shown Figure 4 as comparator A1.
  • Two A2 peer comparators and A3 can be connected to control two T2 transistors and T3 on lines L2 and L3.
  • comparator A1 The operation of comparator A1 is substantially the same as that described in relation to FIG. 3. Depending on whether the voltage V1 is lower or higher than voltage VN, the transistor T1 is open or closed. Likewise, when the voltage V1 is equal to the voltage VN, the transistor T1 is open so avoid simultaneous conduction with possible transistors homologous to transistor T1 on lines L2 and L3.
  • the current source R1 of Figure 3 is replaced here by an NMOS transistor T9 whose grid is controlled by the voltage VN. This reduces the current consumption of comparator A1. If the voltage V1 is the maximum voltage, the voltages V2 and V3 (therefore VN) are canceled in practice, which causes the blocking of transistor T4 and therefore the cancellation of the current flowing through it, which is not the case with a conventional R1 current source such as a resistance.
  • transistor T9 is intended to be crossed by a current of the same order as the current which crosses transistor T4.
  • the gate of transistor T9 will have preferably a W / L ratio of 3/50.
  • the present invention is capable of various variants and modifications which will appear to the man of the job.
  • one of the supply voltages is relatively high compared to the voltage drop in a diode, we can replace the transistor connecting this voltage supply to the output terminal S by a diode such as the diode D3 shown in Figure 4.
  • a supply circuit has been described in FIG. 4 receiving three supply voltages, but those skilled in the art will easily adapt the present invention to a circuit supply receiving more than three supply voltages.
  • the present application has described supply circuits receiving supply voltages positive, in which the supply lines are connected to the output terminal by PMOS transistors.
  • the skilled person will easily adapt the present invention to a circuit supply receiving negative supply voltages, in which the supply lines are connected to the terminal output by NMOS transistors.
  • the transistors PMOS and NMOS in Figures 3 and 4 will be replaced by transistors of the opposite type.

Description

La présente invention concerne les circuits d'alimentation, et en particulier les circuits d'alimentation qui reçoivent plusieurs tensions d'alimentation et qui sélectionnent la tension d'alimentation la plus élevée. De tels circuits d'alimentation sont utilisés, par exemple, dans un appareil à batterie rechargeable pour alimenter l'appareil, le cas échéant, à partir de la batterie ou à partir d'une source d'alimentation externe.The present invention relates to circuits supply, and in particular the supply circuits which receive multiple supply voltages and which select the highest supply voltage. Such circuits are used, for example, in a rechargeable battery to power the device, if applicable, from the battery or from a power source external.

La figure 1 représente un circuit d'alimentation classique recevant deux tensions d'alimentation V1 et V2 sur deux lignes d'alimentation respectives L1 et L2, et fournissant une tension Vdd sur un noeud de sortie S. Les deux lignes d'alimentation sont reliées au noeud de sortie par deux transistors MOS à canal P (PMOS), respectivement T1 et T2. Un comparateur A1 a deux entrées connectées respectivement aux deux lignes d'alimentation de manière que la sortie du comparateur A1 est à un niveau bas lorsque la tension V1 est supérieure à la tension V2 et à un niveau haut dans le cas contraire. La sortie du comparateur A1 est reliée directement à la grille du transistor T1, et est reliée à la grille du transistor T2 par l'intermédiaire d'un inverseur I1. Figure 1 shows a power circuit conventional receiving two supply voltages V1 and V2 out of two respective supply lines L1 and L2, and providing a voltage Vdd on an output node S. The two lines two are connected to the output node P channel MOS transistors (PMOS), T1 and T2 respectively. A comparator A1 has two inputs connected respectively to the two supply lines so that the output of comparator A1 is at a low level when the voltage V1 is greater than the voltage V2 and at a high level otherwise. The exit of comparator A1 is directly connected to the grid of transistor T1, and is connected to the gate of transistor T2 by through an inverter I1.

De tels circuits d'alimentation sont utilisés lorsque l'on veut obtenir une faible chute de tension entre la tension V1 ou V2 et la tension Vdd. Dans les cas où l'on peut admettre une chute de tension importante, on utilise des diodes à la place des transistors T1 et T2.Such supply circuits are used when we want to obtain a low voltage drop between voltage V1 or V2 and the voltage Vdd. In cases where one can admit a significant voltage drop, we use diodes instead of transistors T1 and T2.

La figure 2 représente l'évolution des tensions de grille VG1 et VG2 des transistors T1 et T2 pour un exemple de variation relative des deux tensions d'alimentation V1 et V2. La tension V1 est constante, tandis que la tension V2 croise la tension V1 en décroissant, puis en croissant. On suppose que le comparateur A1 et l'inverseur I1 sont tous deux alimentés entre la tension Vdd et la masse.FIG. 2 represents the evolution of the gate voltages V G1 and V G2 of the transistors T1 and T2 for an example of relative variation of the two supply voltages V1 and V2. The voltage V1 is constant, while the voltage V2 crosses the voltage V1 by decreasing, then increasing. It is assumed that the comparator A1 and the inverter I1 are both supplied between the voltage Vdd and the ground.

Lorsque la tension V2 dépasse la tension V1 d'un seuil ΔV caractéristique du comparateur A1, la tension VA1 fournie par le comparateur est égale à la tension Vdd. Ainsi, les grilles G1 et G2 sont respectivement à la tension Vdd et à la masse. Il en résulte que le transistor T2 conduit et que le transistor T1 est bloqué, le transistor T2 transmettant la tension V2 sur le noeud de sortie S. De même, lorsque la tension V2 est inférieure à la tension V1 du seuil ΔV, la tension VA1 fournie par le comparateur est à la masse, d'où il résulte que le transistor T2 est bloqué et que le transistor T1 conduit, le transistor T1 transmettant la tension V1 sur le noeud de sortie S.When the voltage V2 exceeds the voltage V1 by a threshold ΔV characteristic of the comparator A1, the voltage V A1 supplied by the comparator is equal to the voltage Vdd. Thus, the gates G1 and G2 are respectively at the voltage Vdd and at ground. It follows that the transistor T2 conducts and that the transistor T1 is blocked, the transistor T2 transmitting the voltage V2 on the output node S. Likewise, when the voltage V2 is less than the voltage V1 of the threshold ΔV, the voltage V A1 supplied by the comparator is grounded, where it follows that the transistor T2 is blocked and that the transistor T1 conducts, the transistor T1 transmitting the voltage V1 on the output node S.

La plage ±ΔV est une plage où le comparateur, par nature imparfait, se comporte de manière linéaire. Le comparateur se comporte de manière linéaire entre des instants t1 et t2 où la tension V2 décroít progressivement de la tension V1+ΔV à la tension V1-ΔV et la tension VG1 passe progressivement de la tension Vdd à la masse.The range ± ΔV is a range where the comparator, by nature imperfect, behaves linearly. The comparator behaves linearly between instants t1 and t2 where the voltage V2 gradually decreases from the voltage V1 + ΔV to the voltage V1-ΔV and the voltage V G1 progressively changes from the voltage Vdd to ground.

L'inverseur I1 comporte un transistor PMOS et un transistor MOS à canal N (NMOS). On appelle VTH la tension de seuil du transistor PMOS de l'inverseur I1, laquelle tension est également celle des transistors PMOS T1 et T2. De même, on appelle VTL la tension de seuil du transistor NMOS. The inverter I1 comprises a PMOS transistor and an N channel MOS transistor (NMOS). The threshold voltage of the PMOS transistor of the inverter I1 is called V TH , which voltage is also that of the PMOS transistors T1 and T2. Similarly, the threshold voltage of the NMOS transistor is called V TL .

A un instant t3, la tension VG1 est égale à la tension Vdd-VTH, et à un instant t4 la tension VG1 atteint la tension VTL. La tension de grille VG2, en sortie de l'inverseur I1, évolue progressivement entre un niveau nul à l'instant t3 et le niveau Vdd à l'instant t4.At an instant t3, the voltage V G1 is equal to the voltage Vdd-V TH , and at an instant t4 the voltage V G1 reaches the voltage V TL . The gate voltage V G2 , at the output of the inverter I1, progressively changes between a zero level at time t3 and the level Vdd at time t4.

Le transistor T1 commence à conduire lorsque sa tension de grille VG1 atteint la tension Vdd-VTH, c'est à dire à l'instant t3.The transistor T1 begins to conduct when its gate voltage V G1 reaches the voltage Vdd-V TH , that is to say at time t3.

A un instant t5 la tension de grille VG2 atteint la tension Vdd-VTH. Le transistor T2 cesse de conduire à l'instant t5.At an instant t5 the gate voltage V G2 reaches the voltage Vdd-V TH . The transistor T2 stops driving at time t5.

Ainsi, il y a une plage de conduction simultanée (CS) des transistors T1 et T2 entre les instants t3 et t5. Il y a une plage de conduction simultanée CS similaire de part et d'autre d'un instant tr où la tension V2 devient de nouveau supérieure à la tension V1.So there is a simultaneous conduction range (CS) transistors T1 and T2 between times t3 and t5. There is a similar CS simultaneous conduction range on both sides from an instant tr when the voltage V2 again becomes greater than the voltage V1.

Lors d'une conduction simultanée, les sources d'alimentation produisant les tensions V1 et V2 sont en court-circuit, ce qui n'est pas souhaitable. De plus, si la source d'alimentation fournissant la tension d'alimentation la plus élevée présente une forte impédance, le court-circuit des sources d'alimentation fait chuter la tension d'alimentation la plus élevée au niveau de l'autre tension d'alimentation et le comparateur A1 ne peut plus déterminer laquelle des tensions d'alimentation est la plus élevée. Le circuit de sélection d'alimentation est alors bloqué dans un état intermédiaire et n'assure plus sa fonction correctement.During simultaneous conduction, the sources supply producing the voltages V1 and V2 are short-circuited, which is not desirable. In addition, if the source supplying the most supply voltage high presents a high impedance, the short circuit of power sources lowers the supply voltage the higher at the other supply voltage and the comparator A1 can no longer determine which of the voltages is the highest. The selection circuit power supply is then blocked in an intermediate state and no longer performs its function properly.

D'autre part, le principe utilisé dans le circuit de la figure 1 ne permet pas de sélectionner la plus élevée de trois tensions d'alimentation ou plus.On the other hand, the principle used in the circuit of Figure 1 does not allow you to select the highest of three or more supply voltages.

Le document EP 0838745 décrit un régulateur de tension comprenant un moyen (11) pour sélectionner automatiquement la tension d'alimentation (VM, VL) la plus élevée parmi les tensions présentes à deux bornes d'entrée (EM, EL). Ce document ne prévoit pas d'éviter un court-circuit des lignes d'alimentation lorsque les deux tensions présentes aux bornes d'entrée sont égales entre elles et supérieures à la tension de la borne de sortie.EP 0838745 describes a voltage regulator comprising means (11) for automatically selecting the highest supply voltage (VM, VL) among voltages present at two input terminals (EM, EL). This document does not plan to avoid a short circuit of the lines when the two voltages present at the terminals input are equal to each other and greater than the voltage of the output terminal.

Un objet de la présente invention est de prévoir un circuit de sélection de la plus élevée de deux tensions d'alimentation ou plus, pouvant fonctionner sans mise en court-circuit des lignes d'alimentation. An object of the present invention is to provide a circuit for selecting the higher of two voltages or more, capable of operating without short circuiting power lines.

Pour atteindre cet objet, ainsi que d'autres, la présente invention prévoit un circuit d'alimentation recevant plusieurs tensions d'alimentation sur des lignes d'alimentation respectives, dont chacune est reliée à un commutateur respectif, au moins un des commutateurs étant un premier transistor MOS d'un premier type de conductivité, connecté entre la ligne d'alimentation associée et une borne de sortie commune, qui comprend, pour ledit au moins un commutateur : un deuxième transistor, du premier type de conductivité, relié entre la grille du premier transistor et un noeud d'alimentation maintenu à la plus haute des autres tensions d'alimentation, un troisième transistor, d'un second type de conductivité, moins conducteur à l'état passant que le deuxième transistor, relié entre la grille du premier transistor et un potentiel de référence, et un quatrième transistor, du premier type de conductivité, dont la source est reliée à la ligne d'alimentation associée au commutateur et dont le drain est relié au potentiel de référence par l'intermédiaire d'une source de courant, et aux grilles des deuxième, troisième et quatrième transistors.To achieve this and other objects, the present invention provides a supply circuit receiving multiple supply voltages on supply lines respective, each of which is connected to a respective switch, at least one of the switches being a first MOS transistor of a first type of conductivity, connected between the line associated power supply and a common output terminal, which includes, for said at least one switch: a second transistor, of the first type of conductivity, connected between the gate of the first transistor and a supply node maintained at the highest of the other supply voltages, a third transistor, of a second type of conductivity, less conductive to the on state that the second transistor, connected between the gate of the first transistor and a reference potential, and a fourth transistor, of the first type of conductivity, the source is connected to the supply line associated with the switch and whose drain is connected to the reference potential through a power source, and at the grids of second, third and fourth transistors.

Selon un mode de réalisation de la présente invention, ladite source de courant est un cinquième transistor, du second type de conductivité, dont la grille est reliée audit noeud d'alimentation.According to an embodiment of the present invention, said current source is a fifth transistor, from the second type of conductivity, the grid of which is connected to said node Power.

Selon un mode de réalisation de la présente invention, le circuit d'alimentation comporte deux lignes d'alimentation et deux commutateurs respectifs, le noeud d'alimentation associé à un commutateur étant relié directement à la ligne d'alimentation associée à l'autre commutateur.According to an embodiment of the present invention, the supply circuit has two supply lines and two respective switches, the power supply node associated with a switch being connected directly to the power line associated with the other switch.

Selon un mode de réalisation de la présente invention, le circuit d'alimentation comporte trois lignes d'alimentation, un sixième transistor connecté entre la troisième ligne d'alimentation et le noeud d'alimentation et dont la grille est reliée à la deuxième ligne d'alimentation, et un septième transistor connecté entre la deuxième ligne d'alimentation et le noeud d'alimentation et dont la grille est reliée à la troisième ligne d'alimentation.According to an embodiment of the present invention, the supply circuit comprises three supply lines, a sixth transistor connected between the third line and the power node and whose grid is connected to the second supply line, and a seventh transistor connected between the second supply line and the power node and whose grid is connected to the third feeder.

Selon un mode de réalisation de la présente invention, au moins un des commutateurs est une diode.According to an embodiment of the present invention, at least one of the switches is a diode.

Selon un mode de réalisation de la présente invention, le deuxième transistor a un rapport largeur/longueur de 20/2, et le troisième transistor a un rapport W/L de 3/25.According to an embodiment of the present invention, the second transistor has a width / length ratio of 20/2, and the third transistor has a W / L ratio of 3/25.

Selon un mode de réalisation de la présente invention, le quatrième transistor a un rapport W/L de 40/2, et le cinquième transistor a un rapport W/L de 3/50.According to an embodiment of the present invention, the fourth transistor has a W / L ratio of 40/2, and the fifth transistor has a W / L ratio of 3/50.

Selon un mode de réalisation de la présente invention, les premier et second types de conductivité sont respectivement P et N.According to an embodiment of the present invention, the first and second types of conductivity are respectively P and N.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, décrite précédemment, représente schématiquement un circuit d'alimentation à sélection de tension selon l'art antérieur ;
  • la figure 2, décrite précédemment, illustre le fonctionnement du circuit de la figure 1 ;
  • la figure 3 représente schématiquement un mode de réalisation d'un circuit d'alimentation selon la présente invention ; et
  • la figure 4 représente schématiquement un second mode de réalisation d'un circuit d'alimentation selon la présente invention.
    • These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:
  • FIG. 1, described previously, schematically represents a supply circuit with voltage selection according to the prior art;
  • Figure 2, described above, illustrates the operation of the circuit of Figure 1;
  • FIG. 3 schematically represents an embodiment of a supply circuit according to the present invention; and
  • FIG. 4 schematically represents a second embodiment of a supply circuit according to the present invention.

    • Selon la présente invention, on utilise un comparateur distinct pour commander chacun des transistors T1 et T2, les caractéristiques de chacun des comparateurs étant choisies de manière à supprimer la plage de conduction simultanée.According to the present invention, a comparator is used separate to control each of the T1 and T2 transistors, the characteristics of each of the comparators being chosen from so as to eliminate the range of simultaneous conduction.

    La figure 3 représente un circuit d'alimentation selon la présente invention, recevant deux tensions d'alimentation V1 et V2 sur deux lignes d'alimentation respectives L1 et L2. Les lignes d'alimentation sont, comme en figure 1, respectivement reliées à un noeud de sortie S par des transistors PMOS T1 et T2. Les transistors T1 et T2 sont commandés par deux comparateurs respectifs A1 et A2 de structure particulière. Le comparateur A1 comprend un transistor PMOS T3 dont la source est reliée à la ligne L2, et dont le drain, constituant la sortie du comparateur, est relié à la grille G1. Le drain d'un transistor NMOS T4 est relié à la grille G1 et sa source est reliée à un potentiel de référence, ici la masse. Les grilles des transistors T3 et T4 sont reliées au drain et à la grille d'un transistor PMOS T5 connecté en diode dont la source est reliée à la ligne L1 et dont le drain est relié à la masse par l'intermédiaire d'une source de courant R1.FIG. 3 represents a supply circuit according to the present invention, receiving two supply voltages V1 and V2 on two respective supply lines L1 and L2. The supply lines are, as in Figure 1, respectively connected to an output node S by PMOS transistors T1 and T2. Transistors T1 and T2 are controlled by two comparators respective A1 and A2 of particular structure. Comparator A1 includes a PMOS transistor T3 whose source is connected to the line L2, and whose drain, constituting the output of the comparator, is connected to grid G1. The drain of an NMOS transistor T4 is connected to grid G1 and its source is connected to a potential of reference, here the mass. The grids of transistors T3 and T4 are connected to the drain and the gate of a PMOS transistor T5 connected as a diode whose source is connected to line L1 and whose the drain is connected to ground via a source of current R1.

    Le comparateur A2 associé au transistor T2 comprend des transistors T6, T7 et T8 et une source de courant R2 homologues respectifs des transistors T3, T4 et T5 et de la source de courant R1. Les sources des transistors T6 et T8 sont connectées respectivement aux lignes L1 et L2, c'est à dire de façon intervertie par rapport à la connexion de leurs homologues T3 et T5.The comparator A2 associated with the transistor T2 comprises T6, T7 and T8 transistors and a homologous R2 current source respective transistors T3, T4 and T5 and the source of current R1. The sources of transistors T6 and T8 are connected lines L1 and L2 respectively, i.e. inverted with respect to the connection of their T3 counterparts and T5.

    Si l'on considère, selon une première approximation, que le transistor T4 se comporte comme une source de courant semblable à la source de courant R1, le comparateur A1 se comporte comme un comparateur classique du type à entrée par les sources. Ainsi, lorsque la tension V2 est supérieure à la tension V1, la sortie du comparateur A1 est amenée à une tension proche de la tension V2 et le transistor T1 est ouvert. Dans le cas contraire, la sortie du comparateur est amenée à une tension proche de la masse et le transistor T1 est fermé. Le comparateur A2 a un fonctionnement homologue.If we consider, according to a first approximation, that transistor T4 behaves like a current source similar to current source R1, comparator A1 is behaves like a conventional comparator of the type input by sources. Thus, when the voltage V2 is greater than the voltage V1, the output of comparator A1 is brought to a near voltage of voltage V2 and transistor T1 is open. In the case on the contrary, the comparator output is brought to a voltage close to ground and transistor T1 is closed. The comparator A2 has homologous functioning.

    Selon cette approximation cependant, lorsque V1 = V2, l'équilibre des courants dans les transistors T3 et T5 est tel que la sortie du comparateur est amenée à une tension comprise entre la masse et V1 ou V2. Les transistors T1 et T2 ne sont alors pas franchement bloqués et il y a conduction simultanée.According to this approximation, however, when V1 = V2, the balance of the currents in the transistors T3 and T5 is such that the comparator output is brought to a voltage comprised between ground and V1 or V2. The transistors T1 and T2 are only then not frankly blocked and there is simultaneous conduction.

    Selon la présente invention, le transistor T4 est prévu pour être moins conducteur que le transistor T3, notamment lorsque V1 = V2. Alors, lorsque V1 = V2, le transistor T3 tend à fournir un courant plus élevé que celui que tend à absorber le transistor T4. Il en résulte que la sortie du comparateur est amenée vers le potentiel V2 et que le transistor T1 se bloque. Bien entendu, la sortie du comparateur doit pouvoir être amenée à la masse lorsque V1 > V2, et donc le transistor T4 devenir plus conducteur que le transistor T3. Pour cela, la grille du transistor T4 est connectée au drain du transistor T5, d'où il résulte que le transistor T4 devient d'autant plus conducteur que la tension V1 est élevée. On notera que, selon une variante de mode de réalisation, on pourra connecter la grille du transistor T4 à la source du transistor T5.According to the present invention, the transistor T4 is provided to be less conductive than transistor T3, in particular when V1 = V2. So when V1 = V2, the transistor T3 tends to provide a higher current than that which the transistor T4. As a result, the comparator output is brought to the potential V2 and that the transistor T1 is blocked. Of course, the comparator output must be able to be brought to the mass when V1> V2, and therefore the transistor T4 become more conductor than transistor T3. For this, the grid of transistor T4 is connected to the drain of transistor T5, from where it result that the transistor T4 becomes all the more conductive as the voltage V1 is high. It will be noted that, according to a variant of embodiment, it will be possible to connect the gate of the transistor T4 at the source of transistor T5.

    Une solution pour obtenir un transistor T4 aux caractéristiques souhaitées est d'allonger sa grille par rapport à la grille du transistor T3. On peut ainsi par exemple utiliser un transistor T4 dont la grille a un rapport largeur/longueur (W/L) de 3/25 alors que le transistor T3 a une grille dont le rapport W/L est de 20/2.A solution to obtain a transistor T4 aux desired characteristics is to lengthen its grid relative to the gate of transistor T3. We can for example use a transistor T4 whose gate has a width / length ratio (W / L) of 3/25 while the transistor T3 has a gate whose W / L ratio is 20/2.

    Le transistor T7 du comparateur A2 a les mêmes propriétés que le transistor T4, de manière que le fonctionnement du comparateur A2 soit homologue à celui du comparateur A1.The transistor T7 of the comparator A2 has the same properties as the transistor T4, so that the operation of comparator A2 is homologous to that of comparator A1.

    Ainsi, selon la présente invention, les transistors T1 et T2 se trouvent tous deux ouverts lorsque les tensions V1 et V2 sont égales et il n'y a pas de conduction simultanée.Thus, according to the present invention, the transistors T1 and T2 are both open when the voltages V1 and V2 are equal and there is no simultaneous conduction.

    La présente invention peut également être adaptée à un circuit d'alimentation recevant plus de deux tensions d'alimentation.The present invention can also be adapted to a power circuit receiving more than two voltages Power.

    La figure 4 représente schématiquement un circuit recevant trois tensions V1, V2 et V3 respectivement sur trois lignes d'alimentation L1, L2 et L3. La ligne L1 est reliée à la borne S par un transistor PMOS T1 commandé par un comparateur A1 tel que celui de la figure 3, connecté pour comparer la tension V1 à une tension VN présente sur un noeud N. Le noeud N est relié aux lignes L3 et L2 par deux transistors PMOS T10 et T11 respectifs dont les grilles sont reliées respectivement aux lignes L2 et L3. Avec cette configuration, le noeud N reçoit la plus élevée des tensions V2 et V3. Pour éviter qu'une conduction simultanée des transistors T10 et T11 n'entraíne les problèmes mentionnés précédemment, ces derniers sont choisis très résistifs. Pour des raisons de clarté, on n'a représenté en figure 4 que le comparateur A1. Deux comparateurs homologues A2 et A3 peuvent être connectés pour commander deux transistors T2 et T3 sur les lignes L2 et L3.Figure 4 schematically represents a circuit receiving three voltages V1, V2 and V3 respectively out of three supply lines L1, L2 and L3. Line L1 is connected to the terminal S by a PMOS transistor T1 controlled by a comparator A1 like the one in figure 3, connected to compare the voltage V1 at a voltage VN present on a node N. The node N is connected to lines L3 and L2 by two PMOS transistors T10 and T11 respective whose grids are respectively connected to lines L2 and L3. With this configuration, node N receives the higher voltages V2 and V3. To prevent conduction simultaneous transistors T10 and T11 does not cause problems mentioned above, these are chosen very resistive. For reasons of clarity, we have only shown Figure 4 as comparator A1. Two A2 peer comparators and A3 can be connected to control two T2 transistors and T3 on lines L2 and L3.

    Le fonctionnement du comparateur A1 est sensiblement le même que celui décrit en relation avec la figure 3. Selon que la tension V1 est plus faible ou plus élevée que la tension VN, le transistor T1 est ouvert ou fermé. De même, lorsque la tension V1 est égale à la tension VN, le transistor T1 est ouvert de manière à éviter une conduction simultanée avec d'éventuels transistors homologues au transistor T1 sur les lignes L2 et L3.The operation of comparator A1 is substantially the same as that described in relation to FIG. 3. Depending on whether the voltage V1 is lower or higher than voltage VN, the transistor T1 is open or closed. Likewise, when the voltage V1 is equal to the voltage VN, the transistor T1 is open so avoid simultaneous conduction with possible transistors homologous to transistor T1 on lines L2 and L3.

    Comme cela est représenté, la source de courant R1 de la figure 3 est ici remplacée par un transistor NMOS T9 dont la grille est commandée par la tension VN. Ceci permet de diminuer la consommation de courant du comparateur A1. Si la tension V1 est la tension maximale, les tensions V2 et V3 (donc VN) sont annulées en pratique, ce qui provoque le blocage du transistor T4 et donc l'annulation du courant qui le traverse, ce qui n'est pas le cas avec une source de courant R1 classique telle qu'une résistance.As shown, the current source R1 of Figure 3 is replaced here by an NMOS transistor T9 whose grid is controlled by the voltage VN. This reduces the current consumption of comparator A1. If the voltage V1 is the maximum voltage, the voltages V2 and V3 (therefore VN) are canceled in practice, which causes the blocking of transistor T4 and therefore the cancellation of the current flowing through it, which is not the case with a conventional R1 current source such as a resistance.

    On notera que le transistor T9 est prévu pour être traversé par un courant du même ordre que le courant qui traverse le transistor T4. A titre d'exemple, si l'on utilise les rapports W/L cités précédemment, la grille du transistor T9 aura de préférence un rapport W/L de 3/50.It will be noted that the transistor T9 is intended to be crossed by a current of the same order as the current which crosses transistor T4. For example, if we use reports W / L mentioned above, the gate of transistor T9 will have preferably a W / L ratio of 3/50.

    Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaítront à l'homme du métier. En particulier, si l'une des tensions d'alimentation est relativement élevée par rapport à la chute de tension dans une diode, on pourra remplacer le transistor reliant cette tension d'alimentation à la borne de sortie S par une diode telle que la diode D3 représentée en figure 4.Of course, the present invention is capable of various variants and modifications which will appear to the man of the job. In particular, if one of the supply voltages is relatively high compared to the voltage drop in a diode, we can replace the transistor connecting this voltage supply to the output terminal S by a diode such as the diode D3 shown in Figure 4.

    On a décrit en figure 4 un circuit d'alimentation recevant trois tensions d'alimentation, mais l'homme du métier adaptera sans difficulté la présente invention à un circuit d'alimentation recevant plus de trois tensions d'alimentation.A supply circuit has been described in FIG. 4 receiving three supply voltages, but those skilled in the art will easily adapt the present invention to a circuit supply receiving more than three supply voltages.

    Enfin, on a décrit dans la présente demande des circuits d'alimentation recevant des tensions d'alimentation positives, dans lesquels les lignes d'alimentation sont reliées à la borne de sortie par des transistors PMOS. L'homme du métier adaptera sans difficulté la présente invention à un circuit d'alimentation recevant des tensions d'alimentation négatives, dans lequel les lignes d'alimentation sont reliées à la borne de sortie par des transistors NMOS. Dans ce cas, les transistors PMOS et NMOS des figures 3 et 4 seront remplacés par des transistors du type opposé.Finally, the present application has described supply circuits receiving supply voltages positive, in which the supply lines are connected to the output terminal by PMOS transistors. The skilled person will easily adapt the present invention to a circuit supply receiving negative supply voltages, in which the supply lines are connected to the terminal output by NMOS transistors. In this case, the transistors PMOS and NMOS in Figures 3 and 4 will be replaced by transistors of the opposite type.

    Claims (8)

    1. A power supply circuit receiving several supply voltages (V1, V2) on respective power supply lines (L1, L2), each of which is connected to a respective switch (T1, T2), at least one of a first and a second switch being made of a first MOS transistor (T1, T2) of a first conductivity type, connected between the associated power supply line (L1) and a common output terminal (S),
         each first transistor being controlled by a comparator (A1, A2) comprising:
      a second transistor (T3), of the first conductivity type, connected between the gate of the first transistor and a power supply node (N) maintained at the highest of the other supply voltages,
      a third transistor (T4), of a second conductivity type, which is less conductive in the on state than the second transistor, connected between the gate of the first transistor and a reference potential, and
      a fourth transistor (T5), of the first conductivity type, having its source connected to the power supply line associated with the switch and its drain connected to the reference potential via a current source (R1), and to the gates of the second, third, and fourth transistors.
    2. The power supply circuit of claim 1, characterized in that said current source is a fifth transistor (T9), of the second conductivity type, having its gate connected to said power supply node (N).
    3. The power supply circuit of claim 2, characterized in that it includes two power supply lines (L1, L2) and two respective switches (T1, T2), the power supply node associated with one of the switches being directly connected to the power supply line associated with the other switch.
    4. The power supply circuit of claim 2, characterized in that it includes:
      three power supply lines (L1, L2, L3), and in that each control comparator of a first transistor associated with a first power supply line comprises:
      a sixth transistor (T10) connected between a second power supply line (L3) and the power supply node, and having its gate connected to a third power supply line (L2), and
      a seventh transistor (T11) connected between the third power supply line (L2) and the power supply node and having its gate connected to the second power supply line (L3).
    5. The power supply circuit of claim 4, characterized in that at least one of the switches is a diode (D3).
    6. The power supply circuit of any of the preceding claims, characterized in that:
      the second transistor (T3) has a width-to-length ratio (W/L) of 20/2, and
      the third transistor (T4) has a W/L ratio of 3/25.
    7. The power supply circuit of claim 6, characterized in that:
      the fourth transistor (T5) has a W/L ratio of 40/2, and
      the fifth transistor (T9) has a W/L ratio of 3/50.
    8. The power supply circuit of any of the preceding claims, characterized in that the first and second conductivity types respectively are P and N.
    EP00410109A 1999-08-31 2000-08-30 Supply circuit with voltage selector Expired - Lifetime EP1081572B1 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    FR9911033A FR2798014B1 (en) 1999-08-31 1999-08-31 SUPPLY CIRCUIT WITH VOLTAGE SELECTOR
    FR9911033 1999-08-31

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    EP1081572A1 EP1081572A1 (en) 2001-03-07
    EP1081572B1 true EP1081572B1 (en) 2004-11-03

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    FR2755316B1 (en) * 1996-10-25 1999-01-15 Sgs Thomson Microelectronics VOLTAGE REGULATOR WITH AUTOMATIC SELECTION OF THE HIGHEST SUPPLY VOLTAGE
    US6040718A (en) * 1997-12-15 2000-03-21 National Semiconductor Corporation Median reference voltage selection circuit

    Also Published As

    Publication number Publication date
    FR2798014B1 (en) 2002-03-29
    US6566935B1 (en) 2003-05-20
    FR2798014A1 (en) 2001-03-02
    DE60015464D1 (en) 2004-12-09
    EP1081572A1 (en) 2001-03-07

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