EP1081572A1 - Supply circuit with voltage selector - Google Patents

Supply circuit with voltage selector Download PDF

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Publication number
EP1081572A1
EP1081572A1 EP20000410109 EP00410109A EP1081572A1 EP 1081572 A1 EP1081572 A1 EP 1081572A1 EP 20000410109 EP20000410109 EP 20000410109 EP 00410109 A EP00410109 A EP 00410109A EP 1081572 A1 EP1081572 A1 EP 1081572A1
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EP
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Prior art keywords
transistor
connected
power supply
t1
supply circuit
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EP20000410109
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German (de)
French (fr)
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EP1081572B1 (en )
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Claude Renous
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STMicroelectronics SA
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STMicroelectronics SA
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T307/00Electrical transmission or interconnection systems
    • Y10T307/50Plural supply circuits or sources
    • Y10T307/696Selective or optional sources
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T307/00Electrical transmission or interconnection systems
    • Y10T307/74Switching systems
    • Y10T307/766Condition responsive
    • Y10T307/826Electrical
    • Y10T307/832Power or energy

Abstract

The circuit receives several supply voltages (V1,V2,V3) via connections (L1,L2,L3) each of which is connected to respective switches (T1,T2,T3). At least one of the switches (T1) is a first MOS transistor of P conductivity type connected between the line (L1) and a common output terminal (S). The circuit also includes: - a second transistor (T3) of P conductivity type, connected between the grid of the first transistor (T1) and a node (N) maintained at the highest of the supply voltages; - a third transistor (T4), of N conductivity type, of less conductivity in the conducting state as the first transistor (T1), connected between the grid of the first transistor (T1) and a reference potential, and; - a fourth transistor (T5), of P type of conductivity, whose source is connected to a supply line associated with a switch, and whose drain is connected to a current source (R1) and to the grids of the second (T3), third (T4) and fourth (T5) transistors..

Description

La présente invention concerne les circuits d'alimentation, et en particulier les circuits d'alimentation qui reçoivent plusieurs tensions d'alimentation et qui sélectionnent la tension d'alimentation la plus élevée. The present invention relates to power supply circuits, and particularly the power supply circuits receiving several supply voltages and which select the highest supply voltage. De tels circuits d'alimentation sont utilisés, par exemple, dans un appareil à batterie rechargeable pour alimenter l'appareil, le cas échéant, à partir de la batterie ou à partir d'une source d'alimentation externe. Such power supply circuits are used, for example, in a rechargeable battery unit for powering the unit, if any, from the battery or from an external power source.

La figure 1 représente un circuit d'alimentation classique recevant deux tensions d'alimentation V1 et V2 sur deux lignes d'alimentation respectives L1 et L2, et fournissant une tension Vdd sur un noeud de sortie S. Les deux lignes d'alimentation sont reliées au noeud de sortie par deux transistors MOS à canal P (PMOS), respectivement T1 et T2. 1 shows a conventional power supply circuit receiving both V1 and V2 supply voltages of two respective supply lines L1 and L2, and providing a Vdd voltage on an output node S. The two feed lines are connected to the output node by two P channel MOS transistors (PMOS), T1 and T2 respectively. Un comparateur A1 a deux entrées connectées respectivement aux deux lignes d'alimentation de manière que la sortie du comparateur A1 est à un niveau bas lorsque la tension V1 est supérieure à la tension V2 et à un niveau haut dans le cas contraire. A comparator A1 has two inputs respectively connected to two feed lines such that the output of comparator A1 is at a low level when the voltage V1 is higher than the voltage V2 and to a high level otherwise. La sortie du comparateur A1 est reliée directement à la grille du transistor T1, et est reliée à la grille du transistor T2 par l'intermédiaire d'un inverseur I1. The output of comparator A1 is connected directly to the gate of transistor T1, and is connected to the gate of transistor Q2 via an inverter I1.

De tels circuits d'alimentation sont utilisés lorsque l'on veut obtenir une faible chute de tension entre la tension V1 ou V2 et la tension Vdd. Such supply circuits are used when we want to get a low voltage drop between the voltage V1 and V2 and the voltage Vdd. Dans les cas où l'on peut admettre une chute de tension importante, on utilise des diodes à la place des transistors T1 et T2. In cases where it may be admitted a significant voltage drop, are used diodes in place of transistors T1 and T2.

La figure 2 représente l'évolution des tensions de grille V G1 et V G2 des transistors T1 et T2 pour un exemple de variation relative des deux tensions d'alimentation V1 et V2. 2 shows changes in voltages V G1 and V gate G2 of the transistors T1 and T2 for a sample relative variation of the two supply voltages V1 and V2. La tension V1 est constante, tandis que la tension V2 croise la tension V1 en décroissant, puis en croissant. The voltage V1 is constant, while the voltage V2 intersects the voltage V1 decreasing, then increasing. On suppose que le comparateur A1 et l'inverseur I1 sont tous deux alimentés entre la tension Vdd et la masse. It is assumed that the comparator A1 and the inverter I1 are both supplied between Vdd and ground.

Lorsque la tension V2 dépasse la tension V1 d'un seuil ΔV caractéristique du comparateur A1, la tension V A1 fournie par le comparateur est égale à la tension Vdd. When the voltage V2 exceeds the voltage V1 of a .DELTA.V characteristic threshold of the comparator A1, the voltage V supplied by the comparator A1 is equal to the voltage Vdd. Ainsi, les grilles G1 et G2 sont respectivement à la tension Vdd et à la masse. Thus, the gates G1 and G2 are at the voltage Vdd and to ground respectively. Il en résulte que le transistor T2 conduit et que le transistor T1 est bloqué, le transistor T2 transmettant la tension V2 sur le noeud de sortie S. De même, lorsque la tension V2 est inférieure à la tension V1 du seuil ΔV, la tension V A1 fournie par le comparateur est à la masse, d'où il résulte que le transistor T2 est bloqué et que le transistor T1 conduit, le transistor T1 transmettant la tension V1 sur le noeud de sortie S. As a result, the transistor T2 conducts and the transistor T1 is off, the transistor T2 transmitting the voltage V2 on the output node S. Similarly, when the voltage V2 is lower than the V1 voltage .DELTA.V threshold voltage V A1 supplied by the comparator is grounded, whereby the transistor T2 is off and the transistor T1 is, the transistor T1 transmits the voltage V1 on the output node S.

La plage ±ΔV est une plage où le comparateur, par nature imparfait, se comporte de manière linéaire. The range ± .DELTA.V is a range where the comparator, by imperfect nature behaves linearly. Le comparateur se comporte de manière linéaire entre des instants t1 et t2 où la tension V2 décroít progressivement de la tension V1+ΔV à la tension V1-ΔV et la tension V G1 passe progressivement de la tension Vdd à la masse. The comparator behaves linearly between times t1 and t2 where the voltage V2 gradually decreases from the voltage V1 + .DELTA.V in the V1-.DELTA.V voltage and the voltage V G1 passes progressively from the voltage Vdd to ground.

L'inverseur I1 comporte un transistor PMOS et un transistor MOS à canal N (NMOS). The inverter I1 comprises a PMOS transistor and an N-channel MOS transistor (NMOS). On appelle V TH la tension de seuil du transistor PMOS de l'inverseur I1, laquelle tension est également celle des transistors PMOS T1 et T2. Called V TH of the transistor threshold voltage PMOS of the inverter I1, which is also the voltage of the PMOS transistors T1 and T2. De même, on appelle V TL la tension de seuil du transistor NMOS. Similarly, V TL called the threshold voltage of the NMOS transistor.

A un instant t3, la tension V G1 est égale à la tension Vdd-V TH , et à un instant t4 la tension V G1 atteint la tension V TL . At a time t3, the voltage V G1 is equal to Vdd-V TH voltage, and at an instant t4 the voltage V G1 reaches the voltage V TL. La tension de grille V G2 , en sortie de l'inverseur I1, évolue progressivement entre un niveau nul à l'instant t3 et le niveau Vdd à l'instant t4. V G2 grid voltage, the output of the inverter I1, is gradually moving between a zero level at time t3 and the Vdd level at time t4.

Le transistor T1 commence à conduire lorsque sa tension de grille V G1 atteint la tension Vdd-V TH , c'est à dire à l'instant t3. The transistor T1 begins to conduct when its gate voltage V G1 reaches the voltage Vdd-V TH, i.e. at instant t3.

A un instant t5 la tension de grille V G2 atteint la tension Vdd-V TH . At time t5 the gate voltage V G2 reaches Vdd-V TH voltage. Le transistor T2 cesse de conduire à l'instant t5. The transistor T2 stops conducting at time t5.

Ainsi, il y a une plage de conduction simultanée (CS) des transistors T1 et T2 entre les instants t3 et t5. Thus, there is a simultaneous conduction pad (CS) of the transistors T1 and T2 between the instants t3 and t5. Il y a une plage de conduction simultanée CS similaire de part et d'autre d'un instant tr où la tension V2 devient de nouveau supérieure à la tension V1. There is a similar CS simultaneous conduction of beach either side of a time tr where the voltage V2 again becomes greater than the voltage V1.

Lors d'une conduction simultanée, les sources d'alimentation produisant les tensions V1 et V2 sont en court-circuit, ce qui n'est pas souhaitable. During simultaneous conduction, the power sources producing the voltages V1 and V2 are short-circuited, which is not desirable. De plus, si la source d'alimentation fournissant la tension d'alimentation la plus élevée présente une forte impédance, le court-circuit des sources d'alimentation fait chuter la tension d'alimentation la plus élevée au niveau de l'autre tension d'alimentation et le comparateur A1 ne peut plus déterminer laquelle des tensions d'alimentation est la plus élevée. Moreover, if the power source providing the highest supply voltage presents a high impedance, short circuit the power source drops the highest supply voltage at the other voltage supply and the comparator A1 can not determine which of the supply voltages is the highest. Le circuit de sélection d'alimentation est alors bloqué dans un état intermédiaire et n'assure plus sa fonction correctement. The power selection circuit is blocked in an intermediate state and no longer performs its function properly.

D'autre part, le principe utilisé dans le circuit de la figure 1 ne permet pas de sélectionner la plus élevée de trois tensions d'alimentation ou plus. On the other hand, the principle used in the circuit of Figure 1 does not select the highest of three supply voltages or more.

Un objet de la présente invention est de prévoir un circuit de sélection de la plus élevée de deux tensions d'alimentation ou plus, pouvant fonctionner sans mise en court-circuit des lignes d'alimentation. An object of the present invention is to provide a highest selection circuit of two power supply voltages or more operable without setting short-circuit of the supply lines.

Pour atteindre cet objet, ainsi que d'autres, la présente invention prévoit un circuit d'alimentation recevant plusieurs tensions d'alimentation sur des lignes d'alimentation respectives, dont chacune est reliée à un commutateur respectif, au moins un des commutateurs étant un premier transistor MOS d'un premier type de conductivité, connecté entre la ligne d'alimentation associée et une borne de sortie commune, qui comprend, pour ledit au moins un commutateur : un deuxième transistor, du premier type de conductivité, relié entre la grille du premier transistor et un noeud d'alimentation maintenu à la plus haute des autres tensions d'alimentation, un troisième transistor, d'un second type de conductivité, moins conducteur à l'état passant que le deuxième transistor, relié entre la grille du premier transistor et un potentiel de référence, et un quatrième transistor, du premier type de conductivité, dont la source est reliée à la ligne d'alimentation associée au To achieve this object and others, the present invention provides a power supply circuit receiving several supply voltages at respective power supply lines, each connected to a respective switch, at least one of the switches being a first MOS transistor of a first conductivity type, connected between the associated power supply line and a common output terminal, which comprises, for said at least one switch: a second transistor of the first conductivity type connected between the gate the first transistor and a supply node maintained at the highest of the other supply voltages, a third transistor of a second conductivity type less conductive in the on state than the second transistor, connected between the gate of first transistor and a reference potential, and a fourth transistor of the first conductivity type whose source is connected to the feed line associated with the commutateur et dont le drain est relié au potentiel de référence par l'intermédiaire d'une source de courant, et aux grilles des deuxième, troisième et quatrième transistors. switch and whose drain is connected to the reference potential via a current source, and gates of the second, third and fourth transistors.

Selon un mode de réalisation de la présente invention, ladite source de courant est un cinquième transistor, du second type de conductivité, dont la grille est reliée audit noeud d'alimentation. According to one embodiment of the present invention said current source is a fifth transistor of the second conductivity type whose gate is connected to said supply node.

Selon un mode de réalisation de la présente invention, le circuit d'alimentation comporte deux lignes d'alimentation et deux commutateurs respectifs, le noeud d'alimentation associé à un commutateur étant relié directement à la ligne d'alimentation associée à l'autre commutateur. According to one embodiment of the present invention, the power supply circuit includes two power supply lines and two respective switches, the power supply node associated with one switch being connected directly to the power supply line associated with the other switch .

Selon un mode de réalisation de la présente invention, le circuit d'alimentation comporte trois lignes d'alimentation, un sixième transistor connecté entre la troisième ligne d'alimentation et le noeud d'alimentation et dont la grille est reliée à la deuxième ligne d'alimentation, et un septième transistor connecté entre la deuxième ligne d'alimentation et le noeud d'alimentation et dont la grille est reliée à la troisième ligne d'alimentation. According to one embodiment of the present invention, the supply circuit comprises three power supply lines, a sixth transistor connected between the third power supply line and the power supply node and whose gate is connected to the second line supply, and a seventh transistor connected between the second power supply line and the power supply node and whose gate is connected to the third supply line.

Selon un mode de réalisation de la présente invention, au moins un des commutateurs est une diode. According to one embodiment of the present invention, at least one of the switches is a diode.

Selon un mode de réalisation de la présente invention, le deuxième transistor a un rapport largeur/longueur de 20/2, et le troisième transistor a un rapport W/L de 3/25. According to one embodiment of the present invention, the second transistor has a width / length ratio of 20/2, and the third transistor has a W / L ratio of 3/25.

Selon un mode de réalisation de la présente invention, le quatrième transistor a un rapport W/L de 40/2, et le cinquième transistor a un rapport W/L de 3/50. According to one embodiment of the present invention, the fourth transistor has a W / L ratio of 40/2, and the fifth transistor has a W / L ratio of 3/50.

Selon un mode de réalisation de la présente invention, les premier et second types de conductivité sont respectivement P et N. According to one embodiment of the present invention, the first and second conductivity types are respectively P and N.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : These objects, features and advantages, and others of the present invention will be discussed in detail in the following description of specific embodiments in non-limiting in connection with the accompanying drawings:

  • la figure 1, décrite précédemment, représente schématiquement un circuit d'alimentation à sélection de tension selon l'art antérieur ; Figure 1, previously described, schematically shows a selection voltage supply circuit according to the prior art;
  • la figure 2, décrite précédemment, illustre le fonctionnement du circuit de la figure 1 ; Figure 2, previously described, illustrates the operation of the circuit of Figure 1;
  • la figure 3 représente schématiquement un mode de réalisation d'un circuit d'alimentation selon la présente invention ; FIG 3 schematically shows an embodiment of a supply circuit according to the present invention; et and
  • la figure 4 représente schématiquement un second mode de réalisation d'un circuit d'alimentation selon la présente invention. 4 schematically shows a second embodiment of a supply circuit according to the present invention.

Selon la présente invention, on utilise un comparateur distinct pour commander chacun des transistors T1 et T2, les caractéristiques de chacun des comparateurs étant choisies de manière à supprimer la plage de conduction simultanée. According to the present invention, a separate comparator is used for controlling each of the transistors T1 and T2, the characteristics of each of the comparators being chosen so as to suppress the simultaneous conduction range.

La figure 3 représente un circuit d'alimentation selon la présente invention, recevant deux tensions d'alimentation V1 et V2 sur deux lignes d'alimentation respectives L1 et L2. 3 shows a power supply circuit according to the present invention, receiving two voltages V1 and V2 supply two respective supply lines L1 and L2. Les lignes d'alimentation sont, comme en figure 1, respectivement reliées à un noeud de sortie S par des transistors PMOS T1 et T2. The feed lines are, as in Figure 1, respectively connected to an output node S by the PMOS transistors T1 and T2. Les transistors T1 et T2 sont commandés par deux comparateurs respectifs A1 et A2 de structure particulière. The transistors T1 and T2 are controlled by two respective comparators A1 and A2 of particular structure. Le comparateur A1 comprend un transistor PMOS T3 dont la source est reliée à la ligne L2, et dont le drain, constituant la sortie du comparateur, est relié à la grille G1. The comparator A1 includes a PMOS transistor T3 whose source is connected to the line L2, and its drain constituting the output of the comparator is connected to the gate G1. Le drain d'un transistor NMOS T4 est relié à la grille G1 et sa source est reliée à un potentiel de référence, ici la masse. The drain of an NMOS transistor T4 is connected to the gate G1 and its source is connected to a reference potential, here ground. Les grilles des transistors T3 et T4 sont reliées au drain et à la grille d'un transistor PMOS T5 connecté en diode dont la source est reliée à la ligne L1 et dont le drain est relié à la masse par l'intermédiaire d'une source de courant R1. The gates of transistors T3 and T4 are connected to the drain and the gate of a PMOS transistor T5 connected as a diode having its source connected to the line L1 and whose drain is connected to ground via a source R1 current.

Le comparateur A2 associé au transistor T2 comprend des transistors T6, T7 et T8 et une source de courant R2 homologues respectifs des transistors T3, T4 et T5 et de la source de courant R1. The comparator A2 associated with the transistor T2 includes transistors T6, T7 and T8 and a source of respective counterparts current R2 of the transistors T3, T4 and T5 and the current source R1. Les sources des transistors T6 et T8 sont connectées respectivement aux lignes L1 et L2, c'est à dire de façon intervertie par rapport à la connexion de leurs homologues T3 et T5. The sources of the transistors T6 and T8 are respectively connected to lines L1 and L2, ie so inverted with respect to the connection of their counterparts T3 and T5.

Si l'on considère, selon une première approximation, que le transistor T4 se comporte comme une source de courant semblable à la source de courant R1, le comparateur A1 se comporte comme un comparateur classique du type à entrée par les sources. If we consider, as a first approximation, that the transistor T4 acts as a source of current similar to the current source R1, the comparator A1 behaves as a conventional comparator input by sources such. Ainsi, lorsque la tension V2 est supérieure à la tension V1, la sortie du comparateur A1 est amenée à une tension proche de la tension V2 et le transistor T1 est ouvert. Thus, when the voltage V2 exceeds the voltage V1, the output of comparator A1 is supplied to a voltage close to the voltage V2 and the transistor T1 is open. Dans le cas contraire, la sortie du comparateur est amenée à une tension proche de la masse et le transistor T1 est fermé. Otherwise, the comparator output is supplied to a voltage near ground and the transistor T1 is closed. Le comparateur A2 a un fonctionnement homologue. The comparator A2 is a counterpart operation.

Selon cette approximation cependant, lorsque V1 = V2, l'équilibre des courants dans les transistors T3 et T5 est tel que la sortie du comparateur est amenée à une tension comprise entre la masse et V1 ou V2. According to this approximation, however, when V1 = V2, the balance of currents in the transistors T3 and T5 is such that the comparator output is supplied to a voltage between ground and V1 or V2. Les transistors T1 et T2 ne sont alors pas franchement bloqués et il y a conduction simultanée. The transistors T1 and T2 are not frankly then blocked and there is simultaneous conduction.

Selon la présente invention, le transistor T4 est prévu pour être moins conducteur que le transistor T3, notamment lorsque V1 = V2. According to the present invention, the transistor T4 is arranged to be less conductive than the transistor T3, in particular when V1 = V2. Alors, lorsque V1 = V2, le transistor T3 tend à fournir un courant plus élevé que celui que tend à absorber le transistor T4. So when V1 = V2, the transistor T3 tends to provide a higher current than that tends to absorb the transistor T4. Il en résulte que la sortie du comparateur est amenée vers le potentiel V2 et que le transistor T1 se bloque. As a result, the comparator output is supplied to the potential V2 and the transistor T1 is blocked. Bien entendu, la sortie du comparateur doit pouvoir être amenée à la masse lorsque V1 > V2, et donc le transistor T4 devenir plus conducteur que le transistor T3. Of course, the comparator output must be brought to ground when V1> V2, and therefore the transistor T4 become more conductive than the transistor T3. Pour cela, la grille du transistor T4 est connectée au drain du transistor T5, d'où il résulte que le transistor T4 devient d'autant plus conducteur que la tension V1 est élevée. For this, the gate of the transistor T4 is connected to the drain of the transistor T5, whereby the transistor T4 becomes more conductive than the voltage V1 is high. On notera que, selon une variante de mode de réalisation, on pourra connecter la grille du transistor T4 à la source du transistor T5. Note that according to one embodiment variant, it is possible to connect the gate of the transistor T4 the source of the transistor T5.

Une solution pour obtenir un transistor T4 aux caractéristiques souhaitées est d'allonger sa grille par rapport à la grille du transistor T3. A solution to obtain a transistor T4 to the desired characteristics is to lengthen its gate relative to the gate of transistor T3. On peut ainsi par exemple utiliser un transistor T4 dont la grille a un rapport largeur/longueur (W/L) de 3/25 alors que le transistor T3 a une grille dont le rapport W/L est de 20/2. a transistor T4 whose gate has a width / length ratio can thus be used, for example (W / L) of 3/25 while the transistor T3 has a gate which the ratio W / L of 20/2.

Le transistor T7 du comparateur A2 a les mêmes propriétés que le transistor T4, de manière que le fonctionnement du comparateur A2 soit homologue à celui du comparateur A1. The transistor T7 of the comparator A2 has the same properties as the transistor T4, so that the operation of the comparator A2 is homologous to the comparator A1.

Ainsi, selon la présente invention, les transistors T1 et T2 se trouvent tous deux ouverts lorsque les tensions V1 et V2 sont égales et il n'y a pas de conduction simultanée. Thus, according to the present invention, the transistors T1 and T2 are both opened when the voltages V1 and V2 are equal and there is no simultaneous conduction.

La présente invention peut également être adaptée à un circuit d'alimentation recevant plus de deux tensions d'alimentation. The present invention can also be adapted to a power supply circuit receiving more than two supply voltages.

La figure 4 représente schématiquement un circuit recevant trois tensions V1, V2 et V3 respectivement sur trois lignes d'alimentation L1, L2 et L3. 4 schematically shows a circuit receiving three voltages V1, V2 and V3 respectively on three supply lines L1, L2 and L3. La ligne L1 est reliée à la borne S par un transistor PMOS T1 commandé par un comparateur A1 tel que celui de la figure 3, connecté pour comparer la tension V1 à une tension VN présente sur un noeud N. Le noeud N est relié aux lignes L3 et L2 par deux transistors PMOS T10 et T11 respectifs dont les grilles sont reliées respectivement aux lignes L2 et L3. The line L1 is connected to the S terminal by a PMOS transistor T1 controlled by a comparator A1 such as that of Figure 3, connected to compare the voltage V1 to VN voltage at a node N. The node N is connected to the lines L3 and L2 by respective two PMOS transistors T10 and T11 whose gates are respectively connected to lines L2 and L3. Avec cette configuration, le noeud N reçoit la plus élevée des tensions V2 et V3. With this configuration, the node N receives the higher of the voltages V2 and V3. Pour éviter qu'une conduction simultanée des transistors T10 et T11 n'entraíne les problèmes mentionnés précédemment, ces derniers sont choisis très résistifs. To prevent a simultaneous conduction of transistors T10 and T11 does not cause the problems mentioned above, these are chosen very resistive. Pour des raisons de clarté, on n'a représenté en figure 4 que le comparateur A1. For clarity, we have shown in Figure 4 that the comparator A1. Deux comparateurs homologues A2 et A3 peuvent être connectés pour commander deux transistors T2 et T3 sur les lignes L2 et L3. Both A2 and A3 counterparts comparators may be connected to control two transistors T2 and T3 on the lines L2 and L3.

Le fonctionnement du comparateur A1 est sensiblement le même que celui décrit en relation avec la figure 3. Selon que la tension V1 est plus faible ou plus élevée que la tension VN, le transistor T1 est ouvert ou fermé. The operation of the comparator A1 is substantially the same as that described in connection with Figure 3. Depending on whether the voltage V1 is lower or higher than the voltage VN, the transistor T1 is open or closed. De même, lorsque la tension V1 est égale à la tension VN, le transistor T1 est ouvert de manière à éviter une conduction simultanée avec d'éventuels transistors homologues au transistor T1 sur les lignes L2 et L3. Similarly, when the voltage V1 is equal to the VN voltage, the transistor T1 is open so as to avoid simultaneous conduction with potential homologous transistors to the transistor T1 on lines L2 and L3.

Comme cela est représenté, la source de courant R1 de la figure 3 est ici remplacée par un transistor NMOS T9 dont la grille est commandée par la tension VN. As shown, the current source R1 3 is here replaced by an NMOS transistor T9 whose gate is controlled by the voltage VN. Ceci permet de diminuer la consommation de courant du comparateur A1. This reduces the current consumption of the comparator A1. Si la tension V1 est la tension maximale, les tensions V2 et V3 (donc VN) sont annulées en pratique, ce qui provoque le blocage du transistor T4 et donc l'annulation du courant qui le traverse, ce qui n'est pas le cas avec une source de courant R1 classique telle qu'une résistance. If the voltage V1 is the maximum voltage, the voltages V2 and V3 (ie VN) are canceled in practice, which causes blocking of the transistor T4 and therefore the cancellation of the current flowing through it, which is not the case with a conventional power source such as a resistance R1.

On notera que le transistor T9 est prévu pour être traversé par un courant du même ordre que le courant qui traverse le transistor T4. Note that the transistor T9 is designed to be traversed by a current of the same order as the current flowing through the transistor T4. A titre d'exemple, si l'on utilise les rapports W/L cités précédemment, la grille du transistor T9 aura de préférence un rapport w/L de 3/50. For example, if one uses the W / L ratios mentioned above, the gate of the transistor T9 will preferably have a W / L ratio of 3/50.

Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaítront à l'homme du métier. Of course, the present invention is capable of various modifications which will occur to the skilled person. En particulier, si l'une des tensions d'alimentation est relativement élevée par rapport à la chute de tension dans une diode, on pourra remplacer le transistor reliant cette tension d'alimentation à la borne de sortie S par une diode telle que la diode D3 représentée en figure 4. In particular, if one of the supply voltages is relatively high compared to the voltage drop across a diode, it is possible to replace the transistor connecting the supply voltage to the output terminal S via a diode such as the diode D3 shown in Figure 4.

On a décrit en figure 4 un circuit d'alimentation recevant trois tensions d'alimentation, mais l'homme du métier adaptera sans difficulté la présente invention à un circuit d'alimentation recevant plus de trois tensions d'alimentation. It was described in FIG 4 a supply circuit receiving three supply voltages, but the art will readily adapt the present invention to a power supply circuit receiving more than three supply voltages.

Enfin, on a décrit dans la présente demande des circuits d'alimentation recevant des tensions d'alimentation positives, dans lesquels les lignes d'alimentation sont reliées à la borne de sortie par des transistors PMOS. Finally, it was described in the present application power supply circuits receiving the positive supply voltage, wherein the supply lines are connected to the output terminal by PMOS transistors. L'homme du métier adaptera sans difficulté la présente invention à un circuit d'alimentation recevant des tensions d'alimentation négatives, dans lequel les lignes d'alimentation sont reliées à la borne de sortie par des transistors NMOS. Those skilled in the art will easily adapt the present invention to a power supply circuit receiving negative power supply voltages, wherein the supply lines are connected to the output terminal of the NMOS transistors. Dans ce cas, les transistors PMOS et NMOS des figures 3 et 4 seront remplacés par des transistors du type opposé. In this case, the PMOS and NMOS transistors of Figures 3 and 4 will be replaced by transistors of the opposite type.

Claims (8)

  1. Circuit d'alimentation recevant plusieurs tensions d'alimentation (V1, V2, V3) sur des lignes d'alimentation respectives (L1, L2, L3), dont chacune est reliée à un commutateur respectif (T1, T2, T3), au moins un des commutateurs (T1) étant un premier transistor MOS, d'un premier type de conductivité, connecté entre la ligne d'alimentation associée (L1) et une borne de sortie commune (S), A power supply circuit receiving several supply voltages (V1, V2, V3) on respective power supply lines (L1, L2, L3), each connected to a respective switch (T1, T2, T3), at least one of the switches (T1) being a first MOS transistor of a first conductivity type, connected between the associated power supply line (L1) and a common output terminal (S),
    comprenant, pour ledit au moins un commutateur : comprising for said at least one switch:
    un deuxième transistor (T3), du premier type de conductivité, relié entre la grille du premier transistor et un noeud d'alimentation (N) maintenu à la plus haute des autres tensions d'alimentation, a second transistor (T3) of the first conductivity type connected between the gate of the first transistor and a supply node (N) maintained at the highest of the other supply voltages,
    un troisième transistor (T4), d'un second type de conductivité, moins conducteur à l'état passant que le deuxième transistor, relié entre la grille du premier transistor et un potentiel de référence, et a third transistor (T4) of a second conductivity type less conductive in the on state than the second transistor, connected between the gate of the first transistor and a reference potential, and
    un quatrième transistor (T5), du premier type de conductivité, dont la source est reliée à la ligne d'alimentation associée au commutateur et dont le drain est relié au potentiel de référence par l'intermédiaire d'une source de courant (R1), et aux grilles des deuxième, troisième et quatrième transistors. a fourth transistor (T5) of the first conductivity type whose source is connected to the feed line associated with the switch and whose drain is connected to the reference potential via a current source (R1) , and gates of the second, third and fourth transistors.
  2. Circuit d'alimentation selon la revendication 1, caractérisé en ce que ladite source de courant est un cinquième transistor (T9), du second type de conductivité, dont la grille est reliée audit noeud d'alimentation (N). Supply circuit according to Claim 1, characterized in that said current source is a fifth transistor (T9) of the second conductivity type whose gate is connected to said power supply node (N).
  3. Circuit d'alimentation selon la revendication 2 caractérisé en ce qu'il comporte deux lignes d'alimentation (L1, L2) et deux commutateurs respectifs (T1, T2), le noeud d'alimentation associé à un commutateur étant relié directement à la ligne d'alimentation associée à l'autre commutateur. A power supply circuit according to claim 2 characterized in that it comprises two supply lines (L1, L2) and two respective switches (T1, T2), the power supply node associated with one switch being connected directly to the line power associated with the other switch.
  4. Circuit d'alimentation selon la revendication 2, caractérisé en ce qu'il comporte : A power supply circuit according to claim 2, characterized in that it comprises:
    trois lignes d'alimentation (L1, L2, L3), three power supply lines (L1, L2, L3),
    un sixième transistor (T10) connecté entre la troisième ligne d'alimentation (L3) et le noeud d'alimentation, dont la grille est reliée à la deuxième ligne d'alimentation (L2), et a sixth transistor (T10) connected between the third power supply line (L3) and the power supply node, the gate is connected to the second supply line (L2), and
    un septième transistor (T11) connecté entre la deuxième ligne d'alimentation (L2) et le noeud d'alimentation, dont la grille est reliée à la troisième ligne d'alimentation (L3). a seventh transistor (T11) connected between the second supply line (L2) and the supply node, the gate is connected to the third power supply line (L3).
  5. Circuit d'alimentation selon la revendication 4, caractérisé en ce qu'au moins un des commutateurs est une diode (D3). Supply circuit according to Claim 4, characterized in that at least one of the switches is a diode (D3).
  6. Circuit d'alimentation selon l'une quelconque des revendications précédentes, caractérisé en ce que : A power supply circuit according to any one of the preceding claims, characterized in that:
    le deuxième transistor (T3) a un rapport largeur/longueur (W/L) de 20/2, et the second transistor (T3) has a width / length ratio (W / L) of 20/2, and
    le troisième transistor (T4) a un rapport W/L de 3/25. the third transistor (T4) has a W / L ratio of 3/25.
  7. Circuit d'alimentation selon la revendication 6, caractérisé en ce que : Supply circuit according to Claim 6, characterized in that:
    le quatrième transistor (T5) a un rapport W/L de 40/2, et the fourth transistor (T5) has a W / L ratio of 40/2, and
    le cinquième transistor (T9) a un rapport W/L de 3/50. the fifth transistor (T9) has a W / L ratio of 3/50.
  8. Circuit d'alimentation selon l'une quelconque des revendications précédentes, caractérisé en ce que les premier et second types de conductivité sont respectivement P et N. A power supply circuit according to any one of the preceding claims, characterized in that the first and second conductivity types are respectively P and N.
EP20000410109 1999-08-31 2000-08-30 Supply circuit with voltage selector Expired - Fee Related EP1081572B1 (en)

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