Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/10—Intensity circuits
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes

Definitions

• This invention relates generally to a buss arrangement for display devices and particularly to a system for applying brightness signals to pixels of a display device, such as a liquid crystal display (LCD) or a plasma display.
• a display device such as a liquid crystal display (LCD) or a plasma display.
• Display devices such as liquid crystal displays or plasma displays, are composed of a matrix or an array of pixels arranged horizontally in rows and vertically in columns.
• the video information to be displayed is applied as brightness (gray scale) signals to data lines which are individually associated with each column of pixels.
• the rows of pixels are sequentially scanned and the capacitances of the pixels within the activated row are charged to the various brightness levels in accordance with the levels of the brightness signals applied to the individual columns.
• the M brightness information signals are applied to an input port of an input demultiplexer of the array.
• the demultiplexer converts the M brightness information signals to MXN signals developed in MXN parallel conductors that are coupled via MXN data line drives to MXN column conductors of the array.
• the input demultiplexer may be formed by MXN thin film transistor (TFT's). Groups of M parallel conductors are successively selected, during each horizontal line interval of the video signal. The selection of each group of M parallel conductors is obtained by selection pulse signals developed in a bus of N parallel conductors.
• the capacitance of the input bussing structure associated with the N selection parallel conductors and the input bussing structure associated with the M brightness information carrying parallel conductors can be a major source of both power dissipation and yield loss, especially for higher resolution self-scanned Active- Matrix Liquid Crystal Displays (AMLCDs).
• AMLCDs Active- Matrix Liquid Crystal Displays
• Long metal runs across the display and multiple crossovers (Source/Drain metal-to-Gate metal ) cause significant capacitive loads, resulting in both capacitance shorting failures, unwanted crosstalk among the brightness information carrying conductors and excessive dynamic power dissipation. It is desirable to reduce the number of crossovers of the input bussing structure associated with the N selection parallel conductors and of the input bussing structure associated with the M brightness information carrying parallel conductors.
• An arrangement, embodying an inventive feature, for transferring pixel information with respect to pixels arranged in columns and rows of an array of a display device includes semiconductor switches. Each switch has a first terminal, a second terminal and a third terminal. A first buss is coupled to a first plurality of terminals for communicating signals between the first plurality of terminals and the first terminals of the switches. Local busses that are separated from one another are provided. A given local buss has a first buss section coupled to a second plurality of terminals associated with the given local buss and extends in a manner to cross over the first buss.
• the local buss has a second buss section extending from the first buss section has conductors coupled in a local, clustering buss arrangement to the second terminals of switches associated with the given local buss.
• the associated switches have their third terminals coupled to consecutively disposed column conductors, respectively, of the array.
• FIGURE 1 illustrates an AMLCD with integrated driver circuits, according to an aspect of the invention, when incorporating the bussing arrangement of FIGURE 3 ;
• FIGURE 2 illustrates a prior art bussing structure
• FIGURE 3 illustrates a bussing structure, in accordance with an aspect of the invention, that may be incorporated in the arrangement of FIGURE 1.
• FIGURE 1 illustrates an integrated driver arrangement for storing information in an SVGA liquid crystal array. It should be understood that the invention may be utilized for storing information in pixels of a plasma display.
• Analog circuitry 1 1 receives a video signal representative of picture information to be displayed from, for example, an antenna 12. The analog circuitry 11 provides a video signal on a line 13 as an input signal to an analog-to-digital converter (A D) 14.
• a D analog-to-digital converter
• A/D converter 14 includes an output bus 19- to provide brightness levels, or gray scale codes, to a memory 21 having 100 groups of output lines 22. Each group of output lines 22 of memory 21 applies the stored digital information to a corresponding digital-to- analog (D/A) converter 23. There are 100 D/A converters 23 that correspond to the 100 groups of lines 22, respectively.
• An output analog signal DBS(j) from a given D/A converter 23 is coupled via a corresponding brightness information carrying conductor DB(j) to a demultiplexer transistor MNl associated with a corresponding column.
• Transistors MNl may be thin film transistors (TFTs).
• TFTs thin film transistors
• Demultiplexer transistor MN l applies the information of signal DBS(j) developed on corresponding brightness information carrying conductor DB(j) to a corresponding sampling capacitor C43 for storing an analog signal VC43 in capacitor C43.
• Signal VC43 is coupled to a corresponding data line driver 100 that drives corresponding data line 17 associated with a corresponding column.
• a select line scanner 60 produces row select signals in lines 18 for selecting, in a conventional manner, a given row of array 16.
• the voltages developed in 100 data lines 17 are applied during a 32 microsecond line time to pixels 16a of the selected row.
• FIGURE 1 developed in brightness information carrying conductors DB(j) occurs simultaneously under the control of a corresponding data-word pulse signal DWS(i) forming a selection word.
• the symbol (i) assumes values from 1 to 24 associated with the 24 separate conductors DW(i).
• Each pulse signal DWS(i) controls the sampling of a corresponding group of 100 signals DBS(j) in capacitors C43.
• a two-stage pipeline cycle may be used. Signals DBS(j) are demultiplexed and stored in 2400 capacitors C43 by the operation of pulse signals DWS(i). Then, the information in capacitors C43 is transferred simultaneously to data line driver 100. Thus, capacitors C43 become available for the demultiplexing of the next row information, while the previous row information is applied to the pixels.
• circuitry of FIGURE 1 may operate, for example, similarly to that described in, for example, U.S. Patent No. 5,673.063 in the name of
• FIGURE 2 A possible bussing arrangement of conductors DW(i) and DB(j) is explained in connection with FIGURE 2.
• the crossover capacitance of the input bussing structure associated with conductors DW(i) and DB(j) can be a major source of both power dissipation and yield loss, especially for higher resolution self-scanned Active Matrix Liquid Crystal Displays (AMLCDs).
• AMLCDs Active Matrix Liquid Crystal Displays
• Long metal runs across the display and multiple crossovers (Source/Drain metal-to-Gate metal) cause significant capacitive loads, resulting in both capacitance shorting failures, unwanted crosstalk among the brightness information carrying conductors, and excessive dynamic power dissipation.
• the bussing arrangement of FIGURE 3 reduces the number of capacitive crossovers associated with the input buss structure thus reducing the power dissipation and improving yield.
• all conductors In the bussing arrangement of FIGURE 2, all conductors
• DW(i) that develop gate signals DWS(i) of demultiplexer transistor MNl of FIGURE 1, are bussed together or globally across the entire display.
• Each column of the array is associated with a corresponding transistor MNl having a gate electrode connected to one of those buss conductors DW(i) via a corresponding extention conductor DWC(i ).
• Connection of extention conductor DWC(i) to the corresponding buss conductor DW(i), located closest to data scanner transistors MNl does not cause excessive capacitance problem.
• MNl means that extension conductor DWC(i) must cross all of the other buss conductors DW(i) to which it is not connected. Capacitive coupling CP to the other conductors DW(i), is incurred at each cross over as shown in FIGURE 2. Disadvantageously, the number of capacitive crossovers increases geometrically with the number of data-word conductors
• number of crossovers number of brightness information carrying conductors DB(j) x 1/2 x (number of data- word conductors DW(i) ). It may be desirable to reduce the number of times conductors DWC(i) cross the buss of conductors DW(i) so as to reduce dynamic power dissipation and improve yield.
• the brightness information carrying conductors DB(j) instead of being arranged individually and uniformly across the display, are grouped together into local “clusters" such as, for example, brightness information carrying conductors
• the cluster of brightness information carrying conductors DB(1)-DB(4) are coupled to four transistors MNl having gate electrodes that share, in common, conductor DW(24).
• the number of crossovers of brightness information carrying conductors DB(j)-to-data-word conductors DW(i) have been reduced by a factor of about 4: 1. This, advantageously, reduces dynamic power dissipation, improves yield and reduces the crosstalk among the brightness information carrying-conductors.
• transistors MNl associated with .24 adjacent columns of matrix 16 of FIGURE 1 have gates that are controlled by consecutive data-word signals DWS(i) and apply a common signal DBS(i) to the corresponding columns.
• transistors MNl associated with 4 adjacent columns of matrix 16 of FIGURE 1 have gates that are controlled by common data-word signal DW(24) and apply 4 different signals DBS(i) to the corresponding columns.
• the cluster bussing arrangement adds a multiplicity of new local sub-arrays DBSA to the bus structure. Although these new local sub-arrays do add some additional crossovers of their own (2.5 per brightness information carrying conductor), this is a small price to pay for reducing the average number of crossovers in the main brightness information carrying conductor to data-word conductor matrix from 20/data-line to only 5/data-line.
• the total capacitive coupling in the input buss structure is thereby cut by a factor of approximately 4 using the cluster buss technique. For example: in a display with 100 DB(j) and 24 DW(i) the total number of crossovers is 28,800 using the buss technique of FIGURE 2, while cluster bussing of FIGURE 3 yields 7450 total crossovers.
• cluster bussing therefore, include higher yield, lower power dissipation, and reduced crosstalk.
• another advantage to cluster bussing is that we now break up the pattern of consecutive columns connected to a single signal DBS(j). Small errors in signal DBS(j)-to-signal DBS(j) will normally result in noticeable "block” errors because the human eye is very sensitive to large block patterns.
• the blocks are broken-up into a finer pitch that is, advantageously, less obvious to the viewer.
• the structure may be improved through the addition of clusters of sub-arrays to reduce the complexity and capacitance of the main array.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Liquid Crystal Display Device Control (AREA)
• Liquid Crystal (AREA)
• Electronic Switches (AREA)

Applications Claiming Priority (3)

Publications (2)

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Family Applications (1)

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• 1999
  • 1999-05-11 KR KR1020007012843A patent/KR100660446B1/ko not_active Expired - Lifetime
  • 1999-05-11 AU AU38947/99A patent/AU3894799A/en not_active Abandoned
  • 1999-05-11 CN CNB998062235A patent/CN1183501C/zh not_active Expired - Lifetime
  • 1999-05-11 EP EP99921838.1A patent/EP1078352B1/de not_active Expired - Lifetime
  • 1999-05-11 JP JP2000550091A patent/JP5240884B2/ja not_active Expired - Lifetime
  • 1999-05-11 MX MXPA00011202A patent/MXPA00011202A/es active IP Right Grant
  • 1999-05-11 WO PCT/US1999/010227 patent/WO1999060555A2/en not_active Ceased
  • 1999-05-15 TW TW088107917A patent/TW519612B/zh not_active IP Right Cessation
• 2000
  • 2000-11-08 ZA ZA200006423A patent/ZA200006423B/xx unknown

Non-Patent Citations (1)

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