EP1067473B1 - Intégrateur - Google Patents

Intégrateur Download PDF

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Publication number
EP1067473B1
EP1067473B1 EP00107682A EP00107682A EP1067473B1 EP 1067473 B1 EP1067473 B1 EP 1067473B1 EP 00107682 A EP00107682 A EP 00107682A EP 00107682 A EP00107682 A EP 00107682A EP 1067473 B1 EP1067473 B1 EP 1067473B1
Authority
EP
European Patent Office
Prior art keywords
resistance
capacitance
output
input
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00107682A
Other languages
German (de)
English (en)
Other versions
EP1067473A1 (fr
Inventor
Reiner Bidenbach
Ulrich Dr. Theus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
TDK Micronas GmbH
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Filing date
Publication date
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Publication of EP1067473A1 publication Critical patent/EP1067473A1/fr
Application granted granted Critical
Publication of EP1067473B1 publication Critical patent/EP1067473B1/fr
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • G06G7/186—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop

Definitions

  • the invention relates to an integrator comprising a transconductance amplifier, the output of which is fed back to its inverting input via an integration capacitor, and a first current source having a parasitic parallel capacitance.
  • Such integrators can be used for example in an analog-to-digital converter.
  • analog-to-digital converters which will be described and explained below.
  • the Indian Fig. 4 Imaged integrator is composed of a transconductance amplifier V whose output is fed back via an integration capacitor Ci to its inverting input and at the non-inverting input a reference voltage V2 is applied.
  • a reference voltage V1 is connected to a series connection of an adjustable resistor R1 and a current source Q1 with a parasitic parallel capacitance Cp.
  • the common connection point of the variable resistor R1 and the current source Q1 is connected to the inverting input of the transconductance amplifier V.
  • FIG. 5 an integrator is shown in which the adjustable resistor is realized as a switched capacitor C1. This integrator can therefore be integrated to save space.
  • the in the 4 and 5 shown integrators are used for example as an analog-to-digital converter.
  • the adjustable resistor R1 and the switched capacitor C1 are adjusted in response to the voltage V0 at the output of the transconductance amplifier so that the current flowing through the adjustable resistor receives the input current from the power source.
  • the analog-to-digital converter is to convert the analog current of an integrated photodiode PD into digital values
  • the unfavorable case arises that the photodiode has a large parasitic parallel capacitance Cp and, due to the low input current, an unfavorable ratio of parasitic parallel capacitance Cp to integration capacity Ci of Cp / Ci of about 100, whereby the amplification bandwidth product is reduced by about this factor, ie by about two powers of ten.
  • the bandwidth should be large enough, while at the same time the DC gain should also be large in order to ensure the integration function even at low frequencies.
  • acceptable bandwidth and DC gain can be achieved.
  • the document FR 2 226 785 A (CORECI CIE REGUL CONTROLE INDL, 1974-11-15) discloses an integrator having a transconductance amplifier whose output is fed back to its inverting input via an integrating capacitance and a parasitic parallel capacitance current source having one terminal at a reference potential and another Terminal is connected via a resistive device to a second reference voltage.
  • the invention solves this problem according to claim 1, characterized in that at a voltage divider of a first and a second resistor and the current source with the parasitic Parallel capacitor is a second reference voltage and that the connection point of the first and the second resistor is connected to the inverting input of the transconductance amplifier.
  • the output of a transconductance amplifier V at which an output voltage Vo is removable, according to the embodiment of Fig. 1 connected via an integration capacitor Ci with its inverting input.
  • a reference voltage V1 At the ends of the series connection of the resistors R1 and R2 and the Current source Q1 formed voltage divider is a reference voltage V1.
  • the additional resistance R2 makes it possible to achieve a significantly higher gain bandwidth product if the resistance R2 is dimensioned accordingly.
  • the additional resistor R2 acts as a decoupling resistor.
  • resistor R2 With a capacitance value of the integration capacitor Ci of about 30.10 -15 F, the value of resistor R2 is about 450 K ⁇ , assuming a 10 MHz bandwidth. Appropriately, R2 is dimensioned slightly larger.
  • a second embodiment of the invention is shown, which differs from the first in the Fig. 1 illustrated embodiment differs in that the additional resistor R2 is replaced by a MOS transistor, which operates in the region of weak inversion.
  • a voltage is applied to the gate electrode of the MOS transistor T1, which is lower than the reference voltage V2 in accordance with V G > V ⁇ 2 + V TH is chosen, where V G. the gate voltage at the Tranwssitor T1 and V TH is the threshold voltage of the Transsitors T1.
  • the resistor R1 may be replaced by a switchable capacitance.
  • the example shown is a first-order sigma-delta analog-to-digital converter which converts analog optical signals into digital electrical signals as a measuring converter with a photodiode input.
  • the output of the transconductance amplifier V is connected via the integration capacitor Ci to its inverting input.
  • a reference voltage V2 At the non-inverting input of the transconductance amplifier V is a reference voltage V2.
  • V1 At the two ends of a voltage divider, which is constructed as a series circuit of a switched capacitor C1, the source-drain path of a MOS transistor T1 and a photodiode PD, there is a reference voltage V1.
  • the source of the MOS transistor T1 is connected to the inverting input of the transconductance amplifier V whose output is connected to the input of a threshold detector D.
  • the gate electrode of the MOS transistor T1 is connected to the gate electrode and the drain electrode of a MOS transistor T2.
  • the photodiode PD is represented by its equivalent circuit diagram drawn as a current source Q1 with a parasitic parallel capacitance Cp whose capacitance value is on the order of 3.10 -12 F. Furthermore, it is expedient to choose a value of, for example, about 30.10 -15 F for the integration capacity CI. This value depends on the capacitance value of the capacitor C1, which in turn depends on the photocurrent and the resolution of the A / D converter.
  • the control circuit S controls in response to the voltage Vo at the output of the transconductance amplifier V, the switched capacitor C1 and the count of the counter Z.
  • the transistor T1 acting as an ohmic resistor R2 is shown connected in series with a switched capacitor C1, the invention is not limited thereto. Rather, the switched capacitor C1 can also be realized by a switched current source, a switched resistor or a resistor itself.
  • "ohmic device” always means the series connection of an ohmic resistor (R2 or T1) to a further circuit part, wherein the circuit part may be an ohmic resistor R2, a switched capacitor C1 or a switched current source.
  • the invention is suitable for integrators that receive their input signal from an analog signal source with a relatively high parasitic parallel capacitance. It is therefore particularly suitable for sigma-delta analog-to-digital converters, which are often also called delta-sigma analog-to-digital converters be designated and their input signals are supplied by a photodiode.
  • Sigma-delta analog-to-digital converters are for example in Herbert Bernstein, Analog Circuit Technology with Discrete and Integrated Components, Wegig Verlag, Heidelberg 1997 (ISBN 3-7785-2296-5) on page 480 to 485 and in David A. Jons, Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, New York, Toronto 1997 (ISBN 0-471-14448-7) at pages 531-551 described. For purposes of disclosure, this publication is incorporated herein by reference.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Claims (6)

  1. Intégrateur comprenant
    un amplificateur opérationnel de transcon- ductance (V) dont la sortie est rétrocouplée à travers un condensateur d'intégration (Ci) sur son entrée inverseuse et sur l'entrée non inverseuse duquel une première tension de référence (V2) est montée dans le circuit
    et comprenant
    une première source de courant (Q1) présentant une capacité parallèle parasite (Cp) qui est montée dans le circuit par une borne à une tension de référence et par une autre borne à une deuxième tension de référence (V1) à travers un dispositif ohmique
    caractérisé en ce que
    le dispositif ohmique est un diviseur de tension comprenant une première résistance (R1) et une deuxième résistance (R2)
    et en ce que
    le point de liaison entre la première résistance (R1) et la deuxième résistance (R2) est relié directement à l'entrée inverseuse de l'amplificateur opérationnel de transconductance.
  2. Intégrateur selon la revendication 1 caractérisé en ce que la première source de courant (Q1) comprenant la capacité parallèle parasite (Cp) est une photodiode (PD).
  3. Intégrateur selon la revendication 1 ou 2 caractérisé en ce que pour la deuxième résistance (R1) est prévu un transistor MOS (T1) qui est exploité dans la zone de faible inversion.
  4. Intégrateur selon les revendications de 1 à 3 caractérisé en ce que la première résistance (R1) est une capacité commutée (C1) ou une source de courant commutée ou une résistance pilotable.
  5. Intégrateur selon la revendication 3 ou 4 caractérisé en ce que l'électrode gâchette du premier transistor MOS (T1) est reliée à l'électrode gâchette et à l'électrode drain d'un deuxième transistor MOS (T2), la première tension de référence (V2) venant de cette source et dont le drain est relié à travers une deuxième source de courant (Q2) à une tension de référence, en ce que la sortie de l'amplificateur opérationnel de transconductance (V) est reliée à l'entrée d'un détecteur de seuil (D), cette sortie étant reliée à l'entrée d'un circuit de commande (S) dont la première sortie est reliée à l'entrée d'un compteur (Z) et dont la deuxième sortie est reliée à l'entrée de commande de la capacité (C1) dans le circuit ou à la résistance pilotable.
  6. Intégrateur selon les revendications de 1 à 5 caractérisé en ce que la valeur de la deuxième résistance (R2) est au moins aussi grande que 2π fois la largeur de la bande d'amplification avec (ou multiplié avec) la valeur du condensateur d'intégration (Ci).
EP00107682A 1999-07-09 2000-04-10 Intégrateur Expired - Lifetime EP1067473B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19931879 1999-07-09
DE19931879A DE19931879A1 (de) 1999-07-09 1999-07-09 Integrator

Publications (2)

Publication Number Publication Date
EP1067473A1 EP1067473A1 (fr) 2001-01-10
EP1067473B1 true EP1067473B1 (fr) 2012-02-22

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EP00107682A Expired - Lifetime EP1067473B1 (fr) 1999-07-09 2000-04-10 Intégrateur

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US (1) US6501322B1 (fr)
EP (1) EP1067473B1 (fr)
DE (1) DE19931879A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10131635B4 (de) * 2001-06-29 2004-09-30 Infineon Technologies Ag Vorrichtung und Verfahren zur Kalibrierung der Pulsdauer einer Signalquelle
US6650177B1 (en) * 2001-08-07 2003-11-18 Globespanvirata, Inc. System and method for tuning an RC continuous-time filter
US7173230B2 (en) * 2001-09-05 2007-02-06 Canesta, Inc. Electromagnetic wave detection arrangement with capacitive feedback
DE102009015586A1 (de) 2009-03-30 2010-10-14 Perkinelmer Optoelectronics Gmbh & Co.Kg Sensorausleseschaltung, Sensor und Verfahren zum Auslesen eines Sensorelements
US7924194B2 (en) * 2009-08-27 2011-04-12 Texas Instruments Incorporated Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding
CN103197122B (zh) * 2013-04-12 2015-04-08 矽力杰半导体技术(杭州)有限公司 一种电流检测电路以及应用其的开关型调节器
CN110081991B (zh) * 2019-05-05 2021-02-09 聚辰半导体股份有限公司 一种可用于温度传感器的小数倍信号放大装置及方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2226785A1 (en) * 1973-04-17 1974-11-15 Coreci Cie Regul Controle Indl Function controller based on amplitude - for electronic regulators, uses FET integration
US3902139A (en) * 1974-01-14 1975-08-26 Mobil Oil Corp Temperature compensated pulse generator
DE2732298A1 (de) * 1977-07-16 1979-02-01 Bosch Gmbh Robert Vorrichtung zur erzeugung einer impulsfolge mit in abhaengigkeit von einer steuerspannung einstellbarem tastverhaeltnis
JPH0828054B2 (ja) 1983-11-30 1996-03-21 ソニー株式会社 デイスク状記録媒体
JPS60181981A (ja) * 1984-02-29 1985-09-17 Nec Corp スイツチド・キヤパシタ−・積分器
DE69128509T2 (de) * 1990-09-28 1998-05-14 Yokogawa Electric Corp Zeitgeber
US5627995A (en) 1990-12-14 1997-05-06 Alfred P. Gnadinger Data compression and decompression using memory spaces of more than one size
US5490260A (en) 1990-12-14 1996-02-06 Ceram, Inc. Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size
US5473326A (en) 1990-12-14 1995-12-05 Ceram Incorporated High speed lossless data compression method and apparatus using side-by-side sliding window dictionary and byte-matching adaptive dictionary
US5237460A (en) 1990-12-14 1993-08-17 Ceram, Inc. Storage of compressed data on random access storage devices
DE4214360C2 (de) * 1992-04-30 2002-11-07 Perkinelmer Optoelectronics Lichtdetektorschaltung
US5727037A (en) * 1996-01-26 1998-03-10 Silicon Graphics, Inc. System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits
US5832085A (en) 1997-03-25 1998-11-03 Sony Corporation Method and apparatus storing multiple protocol, compressed audio video data
US5949225A (en) * 1998-03-19 1999-09-07 Astec International Limited Adjustable feedback circuit for adaptive opto drives
KR100280492B1 (ko) * 1998-08-13 2001-02-01 김영환 적분기 입력회로

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Publication number Publication date
EP1067473A1 (fr) 2001-01-10
US6501322B1 (en) 2002-12-31
DE19931879A1 (de) 2001-01-18

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