EP1067473A1 - Intégrateur - Google Patents
Intégrateur Download PDFInfo
- Publication number
- EP1067473A1 EP1067473A1 EP00107682A EP00107682A EP1067473A1 EP 1067473 A1 EP1067473 A1 EP 1067473A1 EP 00107682 A EP00107682 A EP 00107682A EP 00107682 A EP00107682 A EP 00107682A EP 1067473 A1 EP1067473 A1 EP 1067473A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- capacitance
- resistor
- output
- current source
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
- G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
- G06G7/186—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements using an operational amplifier comprising a capacitor or a resistor in the feedback loop
Definitions
- the invention relates to an integrator comprising a transconductance amplifier. its output via an integration capacity fed back to its inverting input and a first current source with a parasitic parallel capacitance.
- Such integrators can be used, for example, in an analog-to-digital converter be used. 4 and 5 known analog-to-digital converters are shown, the following be described and explained.
- the integrator shown in FIG. 4 is made of a transconductance amplifier V built, the output of which via a Integration capacity Ci on its inverting input is fed back and at its non-inverting input a reference voltage V2 is present.
- a reference voltage V2 On a series connection from an adjustable resistor R1 and a current source Q1 with a parasitic parallel capacitance Cp is a reference voltage V1.
- the common connection point of the divisible Resistor R1 and the current source Q1 is connected to that inverting input of the transconductance amplifier V connected.
- Fig. 5 an integrator is shown, the bel the adjustable Resistance realized as switched capacitance C1 is. This integrator can therefore be integrated to save space.
- the integrators shown in Figs. 4 and 5 are used for example as an analog-to-digital converter.
- the adjustable resistance R1 or the switched capacitance C1 are dependent on the voltage Vo at the output of the transconductance amplifier set so that the adjustable Resistance current flowing through the input current from the power source.
- the analog-to-digital converter for example, the analog Convert current of an integrated photodiode PD into digital values should, the unfavorable case arises that in Result of the large parasitic parallel capacitance Cp of the photodiode and due to the low input current an unfavorable one Ratio of parasitic parallel capacitance Cp to integration capacity Ci of Cp / Ci of about 100 results in that Gain bandwidth product by about this factor - well is reduced by about two powers of ten.
- the bandwidth should be large enough while at the same time the DC amplification also should be large, the integrator function even with small ones Ensure frequencies. Because of these two demands but opposing each other is a compromise between the two Claims needed to be both an acceptable bandwidth to achieve a tolerable direct current gain.
- the invention solves this problem according to claim 1 in that that on a voltage divider from a first and a second resistor and the current source with the parasitic Parallel capacitance is a second reference voltage and that the junction of the first and second resistors with the inverting input of the transconductance amplifier connected is.
- the output of a transconductance amplifier V is according to the embodiment 1 about an integration capacity Ci connected to its inverting input.
- the common one Junction point of two resistors R1 and R2, the together with a series-connected current source Q1 a parasitic parallel capacitance Cp a voltage divider form is also with the inverting input of the Transconductance amplifier V connected.
- a reference voltage V1 At the ends of the as Series connection from the resistors R1 and R2 and the Current source Q1 formed voltage divider is a reference voltage V1.
- V2 At the non-inverting input of the transconductance amplifier V is a reference voltage V2.
- the additional resistor R2 acts as Decoupling resistance.
- FIG. 2 shows a second exemplary embodiment of the invention, which differs from the first exemplary embodiment shown in FIG. 1 in that the additional resistor R2 is replaced by a MOS transistor which operates in the region of weak inversion.
- a voltage is applied to the gate electrode of the MOS transistor T1 which is lower than the reference voltage V2 according to V G > V2 + V TH is selected, where V G. the gate voltage at the transistor T1 and V TH is the threshold voltage of the transistor T1.
- the resistor R1 can be switched Capacity to be replaced.
- FIG. 3 is a First order sigma-delta analog-to-digital converter, which as Measuring converter with a photo diode input analog optical signals converted into digital electrical signals.
- the output of the transconductance amplifier V is connected to its inverting input via the integration capacitance Ci.
- a reference voltage V2 is present at the non-inverting input of the transconductance amplifier V.
- a reference voltage V1 is present at the two ends of a voltage divider, which is constructed as a series connection of a switched capacitor C1, the source-drain path of a MOS transistor T1 and a photodiode PD.
- the source of the MOS transistor T1 is connected to the inverting input of the transconductance amplifier V, the output of which is connected to the input of a threshold value detector D.
- the gate electrode of the MOS transistor T1 is connected to the gate electrode and the drain electrode of a MOS transistor T2.
- the reference voltage V2 is at the source of the MOS transistor T2, while the collector of the MOS transistor T2 is connected to a reference potential via a current source Q2.
- the output of the threshold value detector D is connected to the input of a control circuit S, the first output of which is connected to the input of a counter Z and the second output of which is connected to the switching input of the switched capacitor C1.
- the photodiode PD is represented by its equivalent circuit diagram, which is drawn as a current source Q1 with a parasitic parallel capacitance Cp, the capacitance value of which is in the order of 3.10 -12 F. Furthermore, it is expedient to choose a value of about 30.10 -15 F for the integration capacity CI. This value depends on the capacitance value of the capacitor C1, which in turn depends on the photocurrent and the resolution of the A / D converter.
- the control circuit S controls depending on the voltage Vo at the output of the transconductance amplifier V die switched capacitance C1 and the counter reading of the counter Z.
- the invention is not limited to this. Rather, the switched capacitance C1 can also be achieved by a switched current source, switched resistor or a resistance itself can be realized.
- a switched current source switched resistor or a resistance itself can be realized.
- ohmic device is always in the sense of the invention described above the series connection of an ohmic resistor (R2 or T1) meant with a further circuit part, the circuit part an ohmic resistor R2, a switched one Capacitance C1 or a switched current source can be.
- the invention is suitable for integrators that have their input signal from an analog signal source with a get relatively high parasitic parallel capacitance. It is therefore particularly suitable for sigma-delta analog-digital converters suitable, often as a delta-sigma analog-to-digital converter are referred to and their input signals can be supplied by a photodiode.
- Sigma-delta analog-to-digital converters are for example in Herbert Bernstein, Analog Circuit Technology with Discrete and integrated components, Wegig Verlag, Heidelberg 1997 (ISBN 3-7785-2296-5) on pages 480 to 485 and in David A. Jons, Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, New York, Toronto 1997 (ISBN 0-471-14448-7) described on pages 531 to 551. For the purpose of revelation full reference is made to this publication.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19931879A DE19931879A1 (de) | 1999-07-09 | 1999-07-09 | Integrator |
DE19931879 | 1999-07-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1067473A1 true EP1067473A1 (fr) | 2001-01-10 |
EP1067473B1 EP1067473B1 (fr) | 2012-02-22 |
Family
ID=7914114
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00107682A Expired - Lifetime EP1067473B1 (fr) | 1999-07-09 | 2000-04-10 | Intégrateur |
Country Status (3)
Country | Link |
---|---|
US (1) | US6501322B1 (fr) |
EP (1) | EP1067473B1 (fr) |
DE (1) | DE19931879A1 (fr) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10131635B4 (de) | 2001-06-29 | 2004-09-30 | Infineon Technologies Ag | Vorrichtung und Verfahren zur Kalibrierung der Pulsdauer einer Signalquelle |
US6650177B1 (en) * | 2001-08-07 | 2003-11-18 | Globespanvirata, Inc. | System and method for tuning an RC continuous-time filter |
US7173230B2 (en) * | 2001-09-05 | 2007-02-06 | Canesta, Inc. | Electromagnetic wave detection arrangement with capacitive feedback |
DE102009015586A1 (de) | 2009-03-30 | 2010-10-14 | Perkinelmer Optoelectronics Gmbh & Co.Kg | Sensorausleseschaltung, Sensor und Verfahren zum Auslesen eines Sensorelements |
US7924194B2 (en) * | 2009-08-27 | 2011-04-12 | Texas Instruments Incorporated | Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding |
CN103197122B (zh) * | 2013-04-12 | 2015-04-08 | 矽力杰半导体技术(杭州)有限公司 | 一种电流检测电路以及应用其的开关型调节器 |
CN110081991B (zh) * | 2019-05-05 | 2021-02-09 | 聚辰半导体股份有限公司 | 一种可用于温度传感器的小数倍信号放大装置及方法 |
US12015427B2 (en) | 2022-04-05 | 2024-06-18 | Stmicroelectronics (Research & Development) Limited | Photodiode current compatible input stage for a sigma-delta analog-to-digital converter |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2226785A1 (en) * | 1973-04-17 | 1974-11-15 | Coreci Cie Regul Controle Indl | Function controller based on amplitude - for electronic regulators, uses FET integration |
JPS60181981A (ja) * | 1984-02-29 | 1985-09-17 | Nec Corp | スイツチド・キヤパシタ−・積分器 |
DE4214360A1 (de) * | 1992-04-30 | 1993-11-04 | Heimann Optoelectronics Gmbh | Lichtdetektorschaltung |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3902139A (en) * | 1974-01-14 | 1975-08-26 | Mobil Oil Corp | Temperature compensated pulse generator |
DE2732298A1 (de) * | 1977-07-16 | 1979-02-01 | Bosch Gmbh Robert | Vorrichtung zur erzeugung einer impulsfolge mit in abhaengigkeit von einer steuerspannung einstellbarem tastverhaeltnis |
JPH0828054B2 (ja) | 1983-11-30 | 1996-03-21 | ソニー株式会社 | デイスク状記録媒体 |
EP0477537B1 (fr) * | 1990-09-28 | 1997-12-29 | Yokogawa Electric Corporation | Générateur de temporisation |
US5473326A (en) | 1990-12-14 | 1995-12-05 | Ceram Incorporated | High speed lossless data compression method and apparatus using side-by-side sliding window dictionary and byte-matching adaptive dictionary |
US5627995A (en) | 1990-12-14 | 1997-05-06 | Alfred P. Gnadinger | Data compression and decompression using memory spaces of more than one size |
US5237460A (en) | 1990-12-14 | 1993-08-17 | Ceram, Inc. | Storage of compressed data on random access storage devices |
US5490260A (en) | 1990-12-14 | 1996-02-06 | Ceram, Inc. | Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size |
US5727037A (en) * | 1996-01-26 | 1998-03-10 | Silicon Graphics, Inc. | System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits |
US5832085A (en) | 1997-03-25 | 1998-11-03 | Sony Corporation | Method and apparatus storing multiple protocol, compressed audio video data |
US5949225A (en) * | 1998-03-19 | 1999-09-07 | Astec International Limited | Adjustable feedback circuit for adaptive opto drives |
KR100280492B1 (ko) * | 1998-08-13 | 2001-02-01 | 김영환 | 적분기 입력회로 |
-
1999
- 1999-07-09 DE DE19931879A patent/DE19931879A1/de not_active Ceased
-
2000
- 2000-04-10 EP EP00107682A patent/EP1067473B1/fr not_active Expired - Lifetime
- 2000-07-07 US US09/611,599 patent/US6501322B1/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2226785A1 (en) * | 1973-04-17 | 1974-11-15 | Coreci Cie Regul Controle Indl | Function controller based on amplitude - for electronic regulators, uses FET integration |
JPS60181981A (ja) * | 1984-02-29 | 1985-09-17 | Nec Corp | スイツチド・キヤパシタ−・積分器 |
DE4214360A1 (de) * | 1992-04-30 | 1993-11-04 | Heimann Optoelectronics Gmbh | Lichtdetektorschaltung |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 010, no. 034 (P - 427) 8 February 1986 (1986-02-08) * |
Also Published As
Publication number | Publication date |
---|---|
EP1067473B1 (fr) | 2012-02-22 |
US6501322B1 (en) | 2002-12-31 |
DE19931879A1 (de) | 2001-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69003385T2 (de) | Logarithmischer verstärker. | |
DE1901804C3 (de) | Stabilisierter Differentialverstärker | |
DE3123735C2 (de) | Schaltung zur Zuführung eines Stromes an eine Last | |
DE102018221294A1 (de) | LDO-Regler mit Schaltungen zur Reduzierung von Rauschen | |
DE959561C (de) | Negativer Impedanzwandler mit Transistoren | |
EP1067473B1 (fr) | Intégrateur | |
EP0252540B1 (fr) | Dispositif de circuit pour l'ajustage d'un niveau de référence dans un signal périodique | |
DE19746113C2 (de) | Spannungsversorgungsschaltung | |
EP3042167B1 (fr) | Procédé pour le fonctionnement d'un détecteur infrarouge | |
WO2003005561A2 (fr) | Circuit interface destine a etre connecte a une sortie d'un convertisseur de frequence | |
DE68920785T2 (de) | Logische Schaltung. | |
EP0025029A1 (fr) | Dispositif de pont de mesure capacitif | |
DE4212934A1 (de) | Schaltungsanordnung für einen optischen Empfänger | |
EP0696741B1 (fr) | Circuit cascadable bipolaire pour limiter le signal et détection de champs | |
EP0133618A1 (fr) | Circuit oscillateur haute fréquence à quartz sous forme de circuit intégré monolithique | |
DE3437923C1 (de) | Spannungsgesteuerter Oszillator | |
DE1487395B2 (fr) | ||
DE4033856A1 (de) | Schaltender umrichter mit einer schaltungsanordnung zur stromistwertbildung | |
DE1562081C3 (de) | Mit Feldeffekttransistoren aufgebauter Transistorverstärker mit mehreren gleichspannungsgekoppelten Stufen | |
EP0849881A2 (fr) | Circuit de traitement de signal, intégré monolithique | |
DE2600594C3 (de) | Transistorverstärker | |
DE10337285B4 (de) | Verstärkeranordnung | |
DE3612378C2 (fr) | ||
DE2318587C2 (fr) | ||
WO2021069071A1 (fr) | Circuit électrique |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IT NL |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 20010216 |
|
AKX | Designation fees paid |
Free format text: DE FR GB IT NL |
|
17Q | First examination report despatched |
Effective date: 20071011 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT NL |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 50016206 Country of ref document: DE Effective date: 20120419 |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: VDEP Effective date: 20120222 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120222 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20120222 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20121123 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 50016206 Country of ref document: DE Effective date: 20121123 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20150420 Year of fee payment: 16 Ref country code: DE Payment date: 20150421 Year of fee payment: 16 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20150421 Year of fee payment: 16 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 50016206 Country of ref document: DE |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20160410 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20161230 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160502 Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20161101 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20160410 |