EP1062651A1 - Method for display matrix display screen with alternating scanning control in adjacent groups of columns - Google Patents

Method for display matrix display screen with alternating scanning control in adjacent groups of columns

Info

Publication number
EP1062651A1
EP1062651A1 EP99907671A EP99907671A EP1062651A1 EP 1062651 A1 EP1062651 A1 EP 1062651A1 EP 99907671 A EP99907671 A EP 99907671A EP 99907671 A EP99907671 A EP 99907671A EP 1062651 A1 EP1062651 A1 EP 1062651A1
Authority
EP
European Patent Office
Prior art keywords
lines
columns
data
block
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP99907671A
Other languages
German (de)
French (fr)
Other versions
EP1062651B1 (en
Inventor
Thierry Kretz
Bruno Mourey
Hugues Lebrun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Avionics LCD SA
Original Assignee
Thomson-LCD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson-LCD filed Critical Thomson-LCD
Publication of EP1062651A1 publication Critical patent/EP1062651A1/en
Application granted granted Critical
Publication of EP1062651B1 publication Critical patent/EP1062651B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to a method for displaying data on a matrix display, more particularly a matrix display consisting of N data lines and M selection lines at the intersections of which are located image points or pixels, in which the N lines of data are grouped into P blocks of N 'data lines each.
  • liquid crystal screens used in direct vision or projection. These screens are, in general, composed of a first substrate comprising selection lines, referenced below lines, and data lines, referenced below columns, at the intersections of which the image points are located and of a second substrate comprising a counter electrode, the liquid crystals being inserted between the two substrates.
  • the image points consist in particular of pixel electrodes connected through switching circuits, such as transistors, to the selection lines and to the data lines.
  • the selection lines and the data lines are respectively connected to peripheral control circuits generally called "drivers" (in English).
  • the line drivers scan the lines one after the other and close the switching circuits, that is to say pass the transistors of each line.
  • the column drivers apply information to each line of data, namely, charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal included between these electrodes and the counter-electrode, thus allowing the formation of images on the screen.
  • each column is connected by its own connection line to the screen column drivers.
  • Each block consists of transistors 3, one of the electrodes of which is connected to a column and the other electrode of which is connected to the same electrode of the other transistors of the block, all of these electrodes being connected to a video input referenced DB1 for the first block, DB2 for the second block, DBP for the last block.
  • the gates of the transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 ... DW9.
  • Each block has the same structure.
  • FIG. 2 The timing diagrams of the voltages recorded on the successive columns of the same block 1 receiving a video signal DB1 to DBP are shown in FIG. 2. It was assumed for the plotting of these timing diagrams, that the DC and AC voltage errors introduced by the column - line - column coupling (referenced 2 in FIGURE 1), the origin of which was described in French patent n ° 96 00259 filed on January 11, 1996, are perfectly corrected by the compensation circuit presented in this same patent .
  • Each chronogram represents a time-line of a given column (1 to 9) of a block connected for example to DB1. In the case of a line time of 32 ⁇ s, the decomposition of the signals can be done as follows: 1. Preload of all columns of the 4 ⁇ s matrix
  • the present invention aims to provide a method of displaying data on a matrix display which overcomes this drawback.
  • the scanning from 1 to N ′ and then from N ′ to 1 is carried out every other selection line.
  • the scanning from 1 to N 'then from N' to 1 is carried out on
  • the present invention also relates to a circuit for implementing the above method.
  • This circuit consists of at least one programmable logic circuit associated with a line counter determining the reversal of the scanning direction.
  • FIGURE 1 already described is a schematic representation of a matrix display in which the columns are grouped by blocks, which will be used for the implementation of the present invention.
  • FIGURE 2 already described, represents the chronograms, on a time-line, of the odd columns of a DB block made up of 9 columns, and
  • FIGURE 3 is a schematic representation of a circuit used to implement the present invention.
  • the method according to the present invention applies mainly to a matrix display of the type of that shown in FIGURE 1.
  • This display is made up of N data lines or columns and M selection lines at the intersections of which the image points are located. or pixels not shown.
  • the N columns are grouped into P blocks 1 of N 'columns each.
  • P blocks 1 of N 'columns each.
  • FIGURE 1 a block of 9 columns is shown.
  • the column control circuit will comprise 80 blocks of 9 adjacent columns and will operate with a sampling frequency of approximately 500 kHz.
  • each block 1 receives in parallel one of the P or 80 data signals which is demultiplexed by the signals DW1 to DW9 on the N 'or 9 columns of a block.
  • each block 1 is successively scanned from line C1 to C9 by applying sampling pulses DW1 to DW9, and signals such as shown in FIGURE are obtained on each column C1 to C9 2.
  • each block is scanned starting from column C9 to column C1 by applying sampling pulses from DW9 to DW1 so as to reduce the DC error as explained in the introduction with reference in FIGURE 2.
  • the inversion of the scanning is carried out by reversing the arrival of the sampling pulses each two lines among four lines according to the following table: line frame 1 frame 2 frame 3
  • the present invention also relates to a circuit making it possible to implement this method.
  • This circuit consists of at least one programmable logic circuit associated with a line counter determining the reversal of the scanning direction.
  • FIG. 3 An example of a circuit making it possible to generate the scanning of each block receiving the demultiplexing signals DW1 to DWN 'from 1 to N' then from N 'to 1 every 2 lines is represented in FIG. 3.
  • the signal referenced Preset at the output of the line counter 11 controlled by the line clock CL is sent respectively to a modulo counter N '15 and to a DW counter 16.
  • the DW 16 counter is controlled by the DW DWC clock and operates as follows:
  • Preset 0
  • the words are transferred in the normal order. If Preset ⁇ 0 Words are transferred in reverse order.
  • This information at the output of the counter DW is sent to a level shift circuit 17 and returned to the modulo counter N '18.

Abstract

The invention concerns a method for displaying data on a matrix display screen consisting of N data lines (C1, C2, C3,...) and P selection lines (L1, L2, L3, L4,...) at the intersection of which are located the picture elements or pixels (2). The N data lines are assembled in P blocks (1) of N' lines (1 to Cg) with N = P x N', each block (1) receiving in parallel one of the P' data signals (DB1,...) which is demultiplexed (DW1, DW2, DW3, ..., DW9) on said block N' lines. The scanning of N' data lines is produced from 1 to N' or from N' to 1, alternately along the selection lines. The invention is applicable to matrix display screens such as LCD screens.

Description

PROCEDE D'AFFICHAGE DE DONNEES SUR AFFICHEUR MATRICIEL AVEC ORDRE DE BALAYAGE ALTERNE EN GROUPES ADJACENTS DE COLONNESMETHOD FOR DISPLAYING DATA ON A MATRIX DISPLAY WITH ALTERNATE SCAN ORDER IN ADJACENT COLUMNS
La présente invention concerne un procédé d'affichage de données sur un afficheur matriciel, plus particulièrement un afficheur matriciel constitué par N lignes de données et M lignes de sélection aux intersections desquelles sont situés des points-image ou pixels, dans lequel les N lignes de données sont regroupées en P blocs de N' lignes de données chacun.The present invention relates to a method for displaying data on a matrix display, more particularly a matrix display consisting of N data lines and M selection lines at the intersections of which are located image points or pixels, in which the N lines of data are grouped into P blocks of N 'data lines each.
Parmi les afficheurs matriciels, on connaît notamment les écrans à cristaux liquides utilisés en vision directe ou en projection. Ces écrans sont, en général, composés d'un premier substrat comportant des lignes de sélection, référencées ci-après lignes, et des lignes de données, référencées ci-après colonnes, aux intersections desquelles sont situés les points-image et d'un deuxième substrat comportant une contre-électrode, les cristaux liquides étant insérés entre les deux substrats. Les points-image sont constitués notamment par des électrodes de pixels connectées au travers de circuits de commutation, tels que des transistors, aux lignes de sélection et aux lignes de données. Les lignes de sélection et les lignes de données sont respectivement connectées à des circuits de commande périphériques généralement appelés « drivers » (en langue anglaise). Les drivers-lignes balayent les lignes les unes après les autres et ferment les circuits de commutation, c'est-à-dire rendent passants les transistors de chaque ligne. D'autre part, les drivers-colonnes appliquent sur chaque ligne de données une information, à savoir chargent les électrodes des pixels sélectionnés et modifient les propriétés optiques du cristal liquide compris entre ces électrodes et la contre-électrode, permettant ainsi la formation d'images sur l'écran. Lorsque l'afficheur matriciel comporte un nombre de lignes et de colonnes limité, chaque colonne est connectée par sa propre ligne de connexion aux drivers-colonnes de l'écran.Among the matrix displays, there are in particular known liquid crystal screens used in direct vision or projection. These screens are, in general, composed of a first substrate comprising selection lines, referenced below lines, and data lines, referenced below columns, at the intersections of which the image points are located and of a second substrate comprising a counter electrode, the liquid crystals being inserted between the two substrates. The image points consist in particular of pixel electrodes connected through switching circuits, such as transistors, to the selection lines and to the data lines. The selection lines and the data lines are respectively connected to peripheral control circuits generally called "drivers" (in English). The line drivers scan the lines one after the other and close the switching circuits, that is to say pass the transistors of each line. On the other hand, the column drivers apply information to each line of data, namely, charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal included between these electrodes and the counter-electrode, thus allowing the formation of images on the screen. When the matrix display has a limited number of rows and columns, each column is connected by its own connection line to the screen column drivers.
Dans le cas d'écran de définition importante, le principe du multiplexage est utilisé entre les sorties du driver-colonnes et les colonnes de l'écran de manière à réduire le nombre de pistes en entrée de la cellule. Ainsi, dans la demande de brevet française n° 96 00259 déposée le 11 janvier 1996 au nom de la demanderesse, on a décrit un circuit de commande-colonnes d'un afficheur matriciel tel que représenté sur la FIGURE 1. Dans ce cas, les colonnes sont regroupées en P blocs 1 de N' colonnes, à savoir 9 colonnes C1 , C2, C3... C9 dans le mode de réalisation représenté. Chaque bloc est constitué de transistors 3 dont une des électrodes est reliée à une colonne et dont l'autre électrode est connectée à la même électrode des autres transistors du bloc, l'ensemble de ces électrodes étant connecté à une entrée vidéo référencée DB1 pour le premier bloc, DB2 pour le second bloc, DBP pour le dernier bloc. Les grilles des transistors 3 reçoivent chacune un signal de demultiplexage DW1 , DW2, DW3... DW9. Chaque bloc présente la même structure.In the case of an important definition screen, the principle of multiplexing is used between the outputs of the driver-columns and the columns of the screen so as to reduce the number of tracks at the input of the cell. Thus, in French patent application No. 96 00259 filed on January 11, 1996 in the name of the applicant, there has been described a column control circuit of a matrix display as shown in FIGURE 1. In this case, the columns are grouped into P blocks 1 of N 'columns, namely 9 columns C1, C2, C3 ... C9 in the embodiment shown. Each block consists of transistors 3, one of the electrodes of which is connected to a column and the other electrode of which is connected to the same electrode of the other transistors of the block, all of these electrodes being connected to a video input referenced DB1 for the first block, DB2 for the second block, DBP for the last block. The gates of the transistors 3 each receive a demultiplexing signal DW1, DW2, DW3 ... DW9. Each block has the same structure.
Les chronogrammes des tensions relevées sur les colonnes successives d'un même bloc 1 recevant un signal vidéo DB1 à DBP sont représentés sur la figure 2. II a été supposé pour le tracé de ces chronogrammes, que les erreurs de tensions DC et AC introduites par le couplage colonne - ligne - colonne (référencé 2 sur la FIGURE 1), dont l'origine a été décrite dans le brevet français n° 96 00259 déposé le 11 janvier 1996, sont parfaitement corrigées par le circuit de compensation présenté dans ce même brevet. Chaque chronogramme représente un temps-ligne d'une colonne donnée (1 à 9) d'un bloc connecté par exemple à DB1. Dans le cas d'un temps-ligne de 32μs, la décomposition des signaux peut se faire comme suit : 1. Précharge de toutes les colonnes de la matrice 4μsThe timing diagrams of the voltages recorded on the successive columns of the same block 1 receiving a video signal DB1 to DBP are shown in FIG. 2. It was assumed for the plotting of these timing diagrams, that the DC and AC voltage errors introduced by the column - line - column coupling (referenced 2 in FIGURE 1), the origin of which was described in French patent n ° 96 00259 filed on January 11, 1996, are perfectly corrected by the compensation circuit presented in this same patent . Each chronogram represents a time-line of a given column (1 to 9) of a block connected for example to DB1. In the case of a line time of 32 μs, the decomposition of the signals can be done as follows: 1. Preload of all columns of the 4μs matrix
2. Stabilisation de la précharge 0,5μs2. Stabilization of the 0.5 μs preload
3. Echantillonnage de la vidéo sur les 9 colonnes du bloc DB 9 x 2μs3. Sampling of the video on the 9 columns of the DB block 9 x 2μs
4. Egalisation entre colonne et pixel 7,5μs 5. Désélection de la ligne 2μs.4. Equalization between column and pixel 7.5 μs 5. Deselection of the line 2 μs.
Ces diagrammes montrent que la tension des colonnes et donc la tension RMS aux bornes de la cellule à cπstal liquide, dont les électrodes sont respectivement la colonne et l'électrode CE en vis-à-vis, évolue selon l'ordre d'échantillonnage des colonnes d'un bloc connecté à DBP. Or, comme la constante diélectrique du cristal liquide varie en fonction de la tension appliquée à ses bornes, les colonnes d'un même bloc recevant un signal DBi ne présentent donc pas la même capacité de charge. Par conséquent,, le couplage entre les grHIes des transistors d'échantillonnage et les colonnes d'un même bloc recevant le signal DBi augmente en fonction de l'ordre d'échantillonnage des colonnes ce qui introduit une erreur DC de plusieurs dizaines de mV entre la première colonne échantillonnée dans le bloc recevant le signal DBi et la dernière.These diagrams show that the voltage of the columns and therefore the RMS voltage at the terminals of the liquid cπstal cell, the electrodes of which are respectively the column and the opposite CE electrode, changes according to the sampling order of the columns of a block connected to DBP. However, as the dielectric constant of the liquid crystal varies as a function of the voltage applied to its terminals, the columns of the same block receiving a signal DBi therefore do not have the same charge capacity. Consequently, the coupling between the grHIes of the sampling transistors and the columns of the same block receiving the signal DBi increases as a function of the sampling order of the columns which introduces a DC error of several tens of mV between the first column sampled in the block receiving the signal DBi and the last.
La présente invention a pour but de proposer un procédé d'affichage de données sur un afficheur matriciel qui permet de remédier à cet inconvénient.The present invention aims to provide a method of displaying data on a matrix display which overcomes this drawback.
En conséquence, la présente invention a pour objet un procédé d'affichage de données sur un afficheur matriciel constitué par N lignes de données et M lignes de sélection aux intersections desquelles sont situés les points-image ou pixels, dans lequel les N lignes de données sont regroupées en P blocs de N' lignes de données chacun (N = P x N'), chaque bloc recevant en parallèle un des P signaux de données qui est démultiplexé sur les N' lignes dudit bloc, caractérisé en ce que, alternativement selon les lignes de sélection, le balayage des N' lignes de données d'un bloc est réalisé de 1 à N' ou de N' à 1.Consequently, the subject of the present invention is a method of displaying data on a matrix display consisting of N data lines and M selection lines at the intersections of which the image points or pixels are located, in which the N data lines are grouped into P blocks of N 'data lines each (N = P x N'), each block receiving in parallel one of the P data signals which is demultiplexed on the N 'lines of said block, characterized in that, alternately according to the selection lines, the scanning of the N 'data lines of a block is carried out from 1 to N' or from N 'to 1.
Selon un mode de réalisation de la présente invention, le balayage de 1 à N' puis de N' à 1 est réalisé une ligne de sélection sur deux. Selon un autre mode de réalisation qui permet d'obtenir le même niveau continu sur toutes les colonnes, le balayage de 1 à N' puis de N' à 1 est réalisé surAccording to an embodiment of the present invention, the scanning from 1 to N ′ and then from N ′ to 1 is carried out every other selection line. According to another embodiment which makes it possible to obtain the same continuous level on all the columns, the scanning from 1 to N 'then from N' to 1 is carried out on
4 lignes de sélection successives, le balayage étant réalisé dans un premier sens pendant 2 lignes de sélection successives et dans un second sens pendant les 2 autres lignes de sélection suivantes. La présente invention concerne aussi un circuit pour la mise en oeuvre du procédé ci-dessus. Ce circuit est constitué par au moins un circuit logique programmable associé à un compteur-lignes déterminant l'inversion du sens de balayage.4 successive selection lines, the scanning being carried out in a first direction during 2 successive selection lines and in a second direction during the following 2 other selection lines. The present invention also relates to a circuit for implementing the above method. This circuit consists of at least one programmable logic circuit associated with a line counter determining the reversal of the scanning direction.
D'autres caractéristiques et avantages de la présente invention apparaîtront à la lecture de la description faite ci-après, cette description étant faite avec référence aux dessins ci-annexés dans lesquels :Other characteristics and advantages of the present invention will appear on reading the description given below, this description being made with reference to the attached drawings in which:
- La FIGURE 1 déjà décrite est une représentation schématique d'un afficheur matriciel dans lequel les colonnes sont regroupées par blocs, qui sera utilisé pour la mise en oeuvre de la présente invention. - La FIGURE 2, déjà décrite, représente les chronogrammes, sur un temps-ligne, des colonnes impaires d'un bloc DB constitué de 9 colonnes, et- FIGURE 1 already described is a schematic representation of a matrix display in which the columns are grouped by blocks, which will be used for the implementation of the present invention. FIGURE 2, already described, represents the chronograms, on a time-line, of the odd columns of a DB block made up of 9 columns, and
- La FIGURE 3 est une représentation schématique d'un circuit utilisé pour mettre en oeuvre la présente invention..- FIGURE 3 is a schematic representation of a circuit used to implement the present invention.
Pour simplifier la description ci-après, sur les figures les mêmes éléments portent les mêmes références. Le procédé conforme à la présente invention s'applique principalement à un afficheur matriciel du type de celui représenté sur la FIGURE 1. Cet afficheur est constitué par N lignes de données ou colonnes et M lignes de sélection aux intersections desquelles sont situés les points-image ou pixels non représentés. Les N colonnes sont regroupées en P blocs 1 de N' colonnes chacun. A titre d'exemple, sur la FIGURE 1 , on a représenté un bloc de 9 colonnes. Le plus souvent pour un écran utilisé pour un affichage vidéo, le circuit de commande colonnes comportera 80 blocs de 9 colonnes adjacentes et fonctionnera avec une fréquence d'échantillonnage d'environ 500 kHz. Comme représenté sur la FIGURE 1 , chaque bloc 1 reçoit en parallèle un des P ou 80 signaux de données qui est démultiplexé par les signaux DW1 à DW9 sur les N' ou 9 colonnes d'un bloc. Conformément à la présente invention, pour éviter l'erreur DC entre les colonnes d'un même bloc due au couplage entre la grille du transistor d'échantillonnage et la colonne, erreur qui évolue en fonction de l'ordre d'échantillonnage des colonnes, pour la ligne de sélection L1 , chaque bloc 1 est balayé successivement de la ligne C1 à C9 en appliquant des impulsions d'échantillonnage DW1 à DW9, et l'on obtient sur chaque colonne C1 à C9, des signaux tels que représentés sur la FIGURE 2. Puis pour la ligne L2 suivante, chaque bloc est balayé en commençant de la colonne C9 vers la colonne C1 en appliquant des impulsions d'échantillonnage de DW9 à DW1 de manière à réduire l'erreur DC comme expliqué dans l'introduction avec référence à la FIGURE 2.To simplify the description below, in the figures the same elements have the same references. The method according to the present invention applies mainly to a matrix display of the type of that shown in FIGURE 1. This display is made up of N data lines or columns and M selection lines at the intersections of which the image points are located. or pixels not shown. The N columns are grouped into P blocks 1 of N 'columns each. By way of example, in FIGURE 1, a block of 9 columns is shown. Most often for a screen used for a video display, the column control circuit will comprise 80 blocks of 9 adjacent columns and will operate with a sampling frequency of approximately 500 kHz. As shown in FIGURE 1, each block 1 receives in parallel one of the P or 80 data signals which is demultiplexed by the signals DW1 to DW9 on the N 'or 9 columns of a block. In accordance with the present invention, to avoid the DC error between the columns of the same block due to the coupling between the gate of the sampling transistor and the column, an error which evolves as a function of the sampling order of the columns, for the selection line L1, each block 1 is successively scanned from line C1 to C9 by applying sampling pulses DW1 to DW9, and signals such as shown in FIGURE are obtained on each column C1 to C9 2. Then for the next line L2, each block is scanned starting from column C9 to column C1 by applying sampling pulses from DW9 to DW1 so as to reduce the DC error as explained in the introduction with reference in FIGURE 2.
Selon une variante de réalisation du procédé qui permet d'obtenir le même niveau continu sur toutes les colonnes, l'inversion du balayage est réalisée en inversant l'arrivée des impulsions d'échantillonnage chaque deux lignes parmi quatre lignes selon le tableau suivant : ligne trame 1 trame 2 trame 3According to an alternative embodiment of the method which makes it possible to obtain the same continuous level on all the columns, the inversion of the scanning is carried out by reversing the arrival of the sampling pulses each two lines among four lines according to the following table: line frame 1 frame 2 frame 3
1 DW1 à 9 DW1 à 9 DW1 à 91 DW1 to 9 DW1 to 9 DW1 to 9
2 DW1 à 9 DW1 à 9 DW1 à 92 DW1 to 9 DW1 to 9 DW1 to 9
3 DW9à1 DW9à1 DW9à13 DW9à1 DW9à1 DW9à1
4 DW9à1 DW9à1 DW9à14 DW9à1 DW9à1 DW9à1
5 DW1 à 9 DW1 à 9 DW1 à 95 DW1 to 9 DW1 to 9 DW1 to 9
6 DW1 à 9 DW1 à 9 DW1 à 9 6 DW1 to 9 DW1 to 9 DW1 to 9
A noter dans le tableau précédent, que contrairement aux données vidéos qui sont inversées sur les points-image d'une trame à l'autre afin d'éviter le marquage de la cellule, la direction de balayage des signaux DWj est conservée d'une trame à l'autre pour une ligne de sélection donnée afin d'éviter l'erreur AC qui en découlerait.Note in the previous table, that unlike the video data which are inverted on the image points from one frame to another in order to avoid marking the cell, the scanning direction of the signals DWj is retained by frame to another for a given selection line in order to avoid the AC error which would result therefrom.
La présente invention concerne aussi un circuit permettant de mettre en oeuvre ce procédé. Ce circuit est constitué par au moins un circuit logique programmable associé à un compteur-lignes déterminant l'inversion du sens de balayage.The present invention also relates to a circuit making it possible to implement this method. This circuit consists of at least one programmable logic circuit associated with a line counter determining the reversal of the scanning direction.
Un exemple de circuit permettant de générer le balayage de chaque bloc recevant les signaux de demultiplexage DW1 à DWN' de 1 à N' puis de N' à 1 toutes les 2 lignes est représenté sur la figure 3. La base de ce circuit repose sur un circuit logique programmable EPLD 10 qui gouverne l'ordre d'envoi des données vidéo (DB) sur la cellule et le sens de balayage des signaux DW (j = 1 à N') dans un bloc recevant un signal DB (i = 1 à P) donné selon le bit de poids 2 de l'adresse en sortie du compteur-lignes (11) dans le cas de l'exemple représenté ; c'est-à-dire : - si le bit de poids 2 en sortie du compteur-lignes (11) vaut 0 (xxxxxxOO ou xxxxxxOI), les mots DWj' sont lus de 1 à N' et les P données vidéos, stockées dans la mémoire ligne 13, sont transférées à un circuit de commande D/A 14, à savoir un convertisseur numérique/analogique en amont de la cellule suivant l'ordre des DWs selon le tableau ci-dessous :An example of a circuit making it possible to generate the scanning of each block receiving the demultiplexing signals DW1 to DWN 'from 1 to N' then from N 'to 1 every 2 lines is represented in FIG. 3. The base of this circuit rests on a programmable logic circuit EPLD 10 which governs the order of sending of the video data (DB) on the cell and the scanning direction of the signals DW (j = 1 to N ') in a block receiving a signal DB (i = 1 to P) given according to the bit of weight 2 of the address at the output of the line counter (11) in the case of the example shown; that is to say : - if the bit of weight 2 at the output of the line counter (11) is worth 0 (xxxxxxOO or xxxxxxOI), the words DWj 'are read from 1 to N' and the P video data, stored in the memory line 13, are transferred to a D / A control circuit 14, namely a digital / analog converter upstream of the cell in the order of the DWs according to the table below:
DW DB numéro de colonneDW DB column number
1 k N' x (k-1) + 1 avec k entier et 1 < k < P avec k entier et 1 < k < P1 k N 'x (k-1) + 1 with k integer and 1 <k <P with k integer and 1 <k <P
2 k N' x (k-1) + 2 avec k entier et 1 < k ≤ P avec k entier et 1 < k < P2 k N 'x (k-1) + 2 with k integer and 1 <k ≤ P with k integer and 1 <k <P
NT k N' x (k-1) + N' avec k entier et 1 < k < P avec k entier et 1 ≤ k ≤ P NT k N 'x (k-1) + N' with k integer and 1 <k <P with k integer and 1 ≤ k ≤ P
- sinon les mots DWj sont lus de N' à 1 et les P données vidéo sont transférées au circuit de commande D/A 14 selon l'ordre indiqué dans le tableau qui suit :- otherwise the words DWj are read from N 'to 1 and the P video data are transferred to the control circuit D / A 14 in the order indicated in the table below:
DW DB numéro de colonneDW DB column number
N' k N' x (k-1) + N' avec k entier et 1 < k < P avec k entier et 1 < k < PN 'k N' x (k-1) + N 'with k integer and 1 <k <P with k integer and 1 <k <P
2 k N' x (k-1) + 2 avec k entier et 1 < k ≤ P avec k entier et 1 < k < P2 k N 'x (k-1) + 2 with k integer and 1 <k ≤ P with k integer and 1 <k <P
1 k N' x (k-1) + 1 avec k entier et 1 < k < P avec k entier et 1 < k < P De manière plus détaillée, le signal référencé Preset en sortie du compteur-lignes 11 commandé par l'horloge-ligne CL est envoyé respectivement sur un compteur modulo N' 15 et sur un compteur DW 16. Le compteur modulo N' 15 est commandé par l'horloge de données CD et fonctionne de telle sorte que : Si Preset = 0 On transfère les données vidéo telles qu'elles.1 k N 'x (k-1) + 1 with k integer and 1 <k <P with k integer and 1 <k <P In more detail, the signal referenced Preset at the output of the line counter 11 controlled by the line clock CL is sent respectively to a modulo counter N '15 and to a DW counter 16. The modulo counter N' 15 is controlled by the CD data clock and operates in such a way that: If Preset = 0 The video data is transferred as it is.
Si Preset ≠ 0 On transfère N' + 1 - les données vidéo.If Preset ≠ 0 We transfer N '+ 1 - the video data.
De même, le compteur DW 16 est commandé par l'horloge des DW DWC et fonctionne de la manière suivante :Similarly, the DW 16 counter is controlled by the DW DWC clock and operates as follows:
Si Preset = 0 Les mots sont transférés dans l'ordre normal. Si Preset ≠ 0 Les mots sont transférés dans l'ordre inverse.If Preset = 0 The words are transferred in the normal order. If Preset ≠ 0 Words are transferred in reverse order.
Cette information en sortie du compteur DW est envoyée sur un circuit de décalage de niveau 17 et renvoyée sur le compteur modulo N' 18.This information at the output of the counter DW is sent to a level shift circuit 17 and returned to the modulo counter N '18.
II est évident pour l'homme de l'art qu'il s'agit uniquement d'un mode de réalisation particulier qui peut être modifié sans sortir des revendications. It is obvious to those skilled in the art that it is only a particular embodiment which can be modified without departing from the claims.

Claims

REVENDICATIONS
1. Procédé d'affichage de données sur un afficheur matriciel constitué par N lignes de données et P lignes de sélection aux intersections desquelles sont situés les points-images ou pixels, dans lequel les N lignes de données sont regroupées en P' blocs de N' lignes de données chacun (N = P x N'), chaque bloc recevant en parallèle un des P' signaux de données qui est démultiplexé sur les N' lignes dudit bloc, caractérisé en ce que, alternativement selon les lignes de sélection, le balayage des N' lignes de données d'un bloc est réalisé de 1 à N' ou de N' à1. Method for displaying data on a matrix display consisting of N data lines and P selection lines at the intersections of which the image points or pixels are located, in which the N data lines are grouped in P 'blocks of N 'data lines each (N = P x N'), each block receiving in parallel one of the P 'data signals which is demultiplexed on the N' lines of said block, characterized in that, alternately according to the selection lines, the scanning of the N 'data lines of a block is carried out from 1 to N' or from N 'to
2. Procédé selon la revendication 1 , caractérisé en ce que le balayage de 1 à N' puis de N' à 1 est réalisé une ligne de sélection sur deux.2. Method according to claim 1, characterized in that the scanning from 1 to N 'then from N' to 1 is carried out one selection line out of two.
3. Procédé selon la revendication 1 , caractérisé en ce que le balayage de 1 à N' puis de N' à 1 est réalisé sur quatre lignes de sélection successives, le balayage étant réalisé dans un premier sens pendant deux lignes de sélection successives et dans un second sens pendant les deux autres lignes de sélection suivantes.3. Method according to claim 1, characterized in that the scanning from 1 to N 'then from N' to 1 is carried out on four successive selection lines, the scanning being carried out in a first direction during two successive selection lines and in a second direction during the next two other selection lines.
4. Circuit pour la mise en oeuvre du procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce qu'il est constitué par au moins un circuit logique programmable associé à un compteur ligne déterminant l'inversion du sens de balayage. 4. Circuit for implementing the method according to any one of claims 1 to 3, characterized in that it is constituted by at least one programmable logic circuit associated with a line counter determining the inversion of the scanning direction.
EP99907671A 1998-03-10 1999-03-09 Method for display matrix display screen with alternating scanning control in adjacent groups of columns Expired - Lifetime EP1062651B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9802919 1998-03-10
FR9802919A FR2776107A1 (en) 1998-03-10 1998-03-10 Display control system for liquid crystal display screens
PCT/FR1999/000524 WO1999046753A1 (en) 1998-03-10 1999-03-09 Method for display matrix display screen with alternating scanning control in adjacent groups of columns

Publications (2)

Publication Number Publication Date
EP1062651A1 true EP1062651A1 (en) 2000-12-27
EP1062651B1 EP1062651B1 (en) 2002-07-03

Family

ID=9523867

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99907671A Expired - Lifetime EP1062651B1 (en) 1998-03-10 1999-03-09 Method for display matrix display screen with alternating scanning control in adjacent groups of columns

Country Status (7)

Country Link
US (1) US6924785B1 (en)
EP (1) EP1062651B1 (en)
JP (1) JP4727038B2 (en)
KR (1) KR100587433B1 (en)
DE (1) DE69902015T2 (en)
FR (1) FR2776107A1 (en)
WO (1) WO1999046753A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW540020B (en) * 2001-06-06 2003-07-01 Semiconductor Energy Lab Image display device and driving method thereof
JP2004037498A (en) * 2002-06-28 2004-02-05 Seiko Epson Corp Driving circuit for optoelectronic device, optoelectronic device, electronic apparatus, and method for driving optoelectronic device
JP2004145300A (en) * 2002-10-03 2004-05-20 Seiko Epson Corp Electronic circuit, method for driving electronic circuit, electronic device, electrooptical device, method for driving electrooptical device, and electronic apparatus
JP2006072385A (en) * 2002-10-03 2006-03-16 Seiko Epson Corp Electronic device and electronic equipment
FR2873227B1 (en) * 2004-07-13 2006-09-15 Thales Sa MATRICIAL DISPLAY
FR2889763B1 (en) * 2005-08-12 2007-09-21 Thales Sa MATRIX DISPLAY WITH SEQUENTIAL COLOR DISPLAY AND ADDRESSING METHOD
WO2008033870A2 (en) 2006-09-11 2008-03-20 Lumexis Corporation Fiber-to-the-seat (ftts) fiber distribution system
FR2913818B1 (en) * 2007-03-16 2009-04-17 Thales Sa ACTIVE MATRIX OF AN ORGANIC ELECTROLUMINESCENT SCREEN
TWI334126B (en) * 2007-07-17 2010-12-01 Au Optronics Corp Voltage adjusting circuit, method, and display apparatus having the same
FR2934919B1 (en) * 2008-08-08 2012-08-17 Thales Sa FIELD EFFECT TRANSISTOR SHIFT REGISTER
ES2715850T3 (en) 2009-08-06 2019-06-06 Global Eagle Entertainment Inc In-flight system of interconnection in series fiber network to the seat
US8424045B2 (en) 2009-08-14 2013-04-16 Lumexis Corporation Video display unit docking assembly for fiber-to-the-screen inflight entertainment system
WO2011022708A1 (en) 2009-08-20 2011-02-24 Lumexis Corp. Serial networking fiber optic inflight entertainment system network configuration

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5692573A (en) * 1979-12-26 1981-07-27 Citizen Watch Co Ltd Display panel
FR2573899B1 (en) 1984-11-28 1986-12-26 France Etat ELECTRONIC CIRCUIT FORMED OF THIN FILM TRANSISTORS FOR CONTROLLING A MATRIX DEVICE
JPS61223791A (en) * 1985-03-29 1986-10-04 松下電器産業株式会社 Active matrix substrate
DE3630779C1 (en) * 1986-09-10 1992-12-10 Ant Nachrichtentech Secret transmission of video signals e.g. for pay TV - sending image in permutated series by placing lines in meandering form e.g. first line scanning left to right second right to left etc.
JPS63261326A (en) * 1987-04-20 1988-10-28 Seiko Instr & Electronics Ltd Circuit for driving electrooptic device
JPH01143024A (en) * 1987-11-30 1989-06-05 Sony Corp Optical information processor
JPH05143024A (en) * 1991-11-22 1993-06-11 Matsushita Electric Ind Co Ltd Driving method and driving circuit for matrix type liquid image display device
FR2693005B1 (en) 1992-06-26 1995-03-31 Thomson Lcd Circuit encapsulation and passivation arrangement for flat screens.
US5426447A (en) * 1992-11-04 1995-06-20 Yuen Foong Yu H.K. Co., Ltd. Data driving circuit for LCD display
JP3329008B2 (en) * 1993-06-25 2002-09-30 ソニー株式会社 Bidirectional signal transmission network and bidirectional signal transfer shift register
JP2646974B2 (en) * 1993-11-11 1997-08-27 日本電気株式会社 Scanning circuit and driving method thereof
JP3590648B2 (en) * 1994-03-23 2004-11-17 株式会社日立国際電気 Method of compressing original image data and method of expanding original image data
JPH0850465A (en) * 1994-05-30 1996-02-20 Sanyo Electric Co Ltd Shift register and driving circuit of display device
JPH0830242A (en) * 1994-07-13 1996-02-02 Casio Comput Co Ltd Liquid crystal driving device
JPH08106272A (en) * 1994-10-03 1996-04-23 Semiconductor Energy Lab Co Ltd Display device driving circuit
JPH08234169A (en) * 1994-10-20 1996-09-13 Canon Inc Display control device and display control method
US5880707A (en) 1994-10-20 1999-03-09 Canon Kabushiki Kaisha Display control apparatus and method
JP3487660B2 (en) * 1994-12-26 2004-01-19 株式会社日立製作所 Liquid crystal display
JP3454971B2 (en) * 1995-04-27 2003-10-06 株式会社半導体エネルギー研究所 Image display device
JP3639969B2 (en) * 1995-08-03 2005-04-20 カシオ計算機株式会社 Display device
FR2743662B1 (en) 1996-01-11 1998-02-13 Thomson Lcd IMPROVEMENT IN SHIFT REGISTERS USING TRANSISTORS OF THE SAME POLARITY
FR2743658B1 (en) 1996-01-11 1998-02-13 Thomson Lcd METHOD FOR ADDRESSING A FLAT SCREEN USING A PRECHARGE OF THE PIXELS CONTROL CIRCUIT ALLOWING THE IMPLEMENTATION OF THE METHOD AND ITS APPLICATION TO LARGE DIMENSION SCREENS
KR100214484B1 (en) * 1996-06-07 1999-08-02 구본준 Driving circuit for tft-lcd using sequential or dual scanning method
JP2980042B2 (en) * 1996-11-27 1999-11-22 日本電気株式会社 Scanning circuit
JP3077650B2 (en) * 1997-10-27 2000-08-14 日本ビクター株式会社 Active matrix liquid crystal panel drive

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9946753A1 *

Also Published As

Publication number Publication date
WO1999046753A1 (en) 1999-09-16
KR20010041675A (en) 2001-05-25
JP2002507007A (en) 2002-03-05
DE69902015D1 (en) 2002-08-08
JP4727038B2 (en) 2011-07-20
EP1062651B1 (en) 2002-07-03
KR100587433B1 (en) 2006-06-09
US6924785B1 (en) 2005-08-02
DE69902015T2 (en) 2003-03-06
FR2776107A1 (en) 1999-09-17

Similar Documents

Publication Publication Date Title
US6333729B1 (en) Liquid crystal display
US5907314A (en) Liquid-crystal display apparatus
EP1062651B1 (en) Method for display matrix display screen with alternating scanning control in adjacent groups of columns
EP0216188B1 (en) Matrix display panel
EP0815552B1 (en) Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screens
JP3039404B2 (en) Active matrix type liquid crystal display
FR2569294A1 (en) DISPLAY PANEL AND ITS CONTROL METHOD
EP0863498A2 (en) Data signal line structure in an active matrix liquid crystal display
JP4271414B2 (en) Image display device and display driving method
US4736137A (en) Matrix display device
EP3079142B1 (en) Method for displaying images on a matrix screen
JP2714161B2 (en) Liquid crystal display device
US4838652A (en) Image forming apparatus
EP0641475B1 (en) Method for displaying different levels of gray and system for implementing such method
FR2784489A1 (en) METHOD FOR DISPLAYING DATA ON A MATRIX DISPLAY
US20060232543A1 (en) Display device and drive method thereof
JP2854621B2 (en) Display device drive circuit
EP0494826B1 (en) Method for displaying images with Q grey levels on a matrix screen
JP3226092B2 (en) Liquid crystal display
FR2776108A1 (en) Display control system for liquid crystal display screens
FR2615993A1 (en) METHOD AND DEVICE FOR THE ELIMINATION OF COUPLING IN MATRIX ADDRESSED THIN FILM TRANSISTOR LIQUID CRYSTAL SCREENS
FR2580826A1 (en) METHOD AND APPARATUS FOR CONTROLLING AN OPTICAL MODULATION DEVICE
JP3385910B2 (en) Active matrix liquid crystal display
JP2001035180A (en) Shift register and electronic equipment
JPH07281648A (en) Liquid crystal display device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20000908

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB NL

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 20011017

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THALES AVIONICS LCD S.A.

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB NL

REF Corresponds to:

Ref document number: 69902015

Country of ref document: DE

Date of ref document: 20020808

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20020721

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20030404

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20070301

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20081001

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 18

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 19

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

Free format text: REGISTERED BETWEEN 20171214 AND 20171222

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20180327

Year of fee payment: 20

Ref country code: NL

Payment date: 20180314

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20180329

Year of fee payment: 20

REG Reference to a national code

Ref country code: NL

Ref legal event code: MK

Effective date: 20190308

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20190308

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20190308

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230527