EP1000506A1 - Kamera mit digitaler korrelierter doppelabtastung - Google Patents

Kamera mit digitaler korrelierter doppelabtastung

Info

Publication number
EP1000506A1
EP1000506A1 EP98938145A EP98938145A EP1000506A1 EP 1000506 A1 EP1000506 A1 EP 1000506A1 EP 98938145 A EP98938145 A EP 98938145A EP 98938145 A EP98938145 A EP 98938145A EP 1000506 A1 EP1000506 A1 EP 1000506A1
Authority
EP
European Patent Office
Prior art keywords
digital
signal
image
pixel
ofthe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98938145A
Other languages
English (en)
French (fr)
Inventor
Steven W. Tonkin
Scott S. Liebert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PPT Vision Inc
Original Assignee
PPT Vision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PPT Vision Inc filed Critical PPT Vision Inc
Publication of EP1000506A1 publication Critical patent/EP1000506A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/16Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
    • H04N5/18Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
    • H04N5/185Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit for the black level
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50Constructional details
    • H04N23/51Housings
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
    • H04N25/633Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75Circuitry for providing, modifying or processing image signals from the pixel array

Definitions

  • This invention relates to the field of electronic cameras, and in particular to analog and digital electronic circuitry to improve cameras using charge- coupled devices (CCDs) in digital-output machine-vision applications.
  • CCDs charge- coupled devices
  • a circuit for converting an analog image-bearing signal from an electronic imaging device.
  • the image-bearing signal provides both an pixel-reference signal and a pixel-image signal for each one of a plurality of pixels ofthe imaging device.
  • the circuit includes a voltage clamp that adjusts a level ofthe image-bearing signal based on a black reference level to produce a clamped image-bearing signal.
  • An analog-to-digital converter (ADC) is coupled to digitize the clamped image-bearing signal and operated to produce a first digital value representative ofthe pixel-reference signal for a pixel, and operated to produce a second digital value representative ofthe pixel- image signal.
  • the above circuit further includes a first digital register having an input connected to the ADC to receive and temporarily store the first digital value, and a second digital register having an input connected to the ADC to receive and temporarily store the second digital value, wherein the first digital subtractor has an input connected to the first register and second registers.
  • the method steps (a) through (d) are performed on a plurality of imaging pixels within a row of pixels ofthe imaging device. In another such embodiment, the method steps (a) through (d) are performed on a plurality of non-imaging pixels ofthe imaging device.
  • FIG. 4B is a stylized timing diagram showing the relationship of sampling clock 205 and signal V out 119 (as represented by idealized signal 440).
  • FIG. 4C is a flow chart showing one method for adjusting sampling clock 205 relative to signal V out 119.
  • FIG. 8 A is a drawing ofthe mounting mechanism of one embodiment of a machine- vision camera.
  • FIGs. 8B, 8C, 8D, 8E are drawings ofthe mounting mechanism of another embodiment of a machine- vision camera.
  • FIG. 9 is a drawing of a system 900 that uses machine- vision camera 100 in an automated manufacturing situation.
  • FIG. 10 shows a multiple-dovetail unit 8100, dovetail-slot guiderail 890, and a dovetail slot 512 formed onto strobe 940.
  • the reference voltage for a pixel is stored in a sample-and-hold circuit, and this reference voltage and the image voltage for that pixel are fed to a differential amplifier to generate a difference voltage representing the true image for that pixel. If a source of noise or error affects both the reference and image voltages, generating this difference will remove the effect ofthe noise from the image signal.
  • Some CCD circuits also provide one or more "black pixels" at the beginning and/or end of each row and/or column. In some embodiments, these black pixels have opaque coverings but are otherwise identical in signal characteristics as imaging pixels, and thus the signal from those pixels is representative ofthe signals of other pixels were those pixels to receive a black image (i.e., a pixel having no light).
  • Packetizer, serializer, & transmitter block 140 outputs the serial digital image 149 from machine- vision camera 100, as well as other information necessary for the operation of machine- vision camera 100 onto user interface 190.
  • Receiver, deserializer, & depacketizer block 150 receives data into camera 100, such as operational commands, frame timing signals, and aperture control from user interface 190.
  • Block 150 deserializes the information and passes the information onto command processing circuit 160.
  • Command processing circuit 160 controls the aperture speed and timing, and clock circuitry 180.
  • the control output of clock circuitry 180 provides clocks for the output timing of CCD sensor 110, timing for digitizing & digital-signal-conditioning 130, and output timing for output onto user interface 190 by block 140.
  • Figure 2 A shows a more detailed block diagram of one embodiment of machine-vision camera 100 ofthe present invention.
  • Image sensor 110 includes an array 112 of CCD pixels and output circuitry 114.
  • image sensor 110 includes a full-frame 640-by-480 pixel CCD image sensor, Model KAI-0310 (available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010).
  • image sensor 110 includes a full-frame 1024-by-1024 CCD image sensor, Model KAI 1001 series CCD sensor (also available from Eastman Kodak Company - Microelectronics Division, Rochester, New York 14650-2010).
  • Output circuitry 114 serially outputs an analog image-bearing signal, V out 119, to analog-signal-conditioning circuit 120.
  • V ou ⁇ 119 is supplied as a 300 millivolt image-bearing signal on top of, for example, an 8-volt DC component.
  • V out 119 is applied through DC-blocking capacitor 122 (which removes the DC component just mentioned) to the input of amplifier 124, which is also coupled to "clamp" or integrator/offset-level adjustor 126 (which provides a replacement adjustable "DC” or “offset-level” component for the signal from the CCD 110 that can be varied, as described below).
  • the output of amplifier 124 is applied to the input of analog-to-digital converter (ADC) 132.
  • ADC analog-to-digital converter
  • amplifier 124 is omitted, and the clamped signal is coupled directly to ADC 132.
  • Clock generator 180 includes circuitry that generates clocks, including clocks 171 and 205, and clock-enables 207 and 209.
  • clock generator 180 includes phase-locked loop circuitry to generate control clocks for output circuitry 114 (clocks 171) and ADC 132 (clock 205) which are synchronized to one another and are automatically varied in edge timing (and/or frequency) as outside stimuli, e.g., ambient temperature, affects the timing ofthe output signal 119 ofthe CCD image sensor.
  • a tapped delay line 281 coupled to multiplexors for example, multiplexors 283 and 284 in a suitable programmed field-programmable gate array (FPGA) 282, programmable array logic (PAL) or application-specific integrated circuit (ASIC) chip are used to implement suitable multiplexors
  • FPGA field-programmable gate array
  • PAL programmable array logic
  • ASIC application-specific integrated circuit
  • oscillator 280 drives FPGA 282, which in turn drives tapped delay line 281, and receives the N tapped, delay signals from delay line 281.
  • tapped delay line 281 provides ten taps at one nanosecond (ns) intervals, i.e., each delayed one nanosecond more than the one before.
  • Multiplexor (mux) 283 and mux 284 each select one (either the same or different ones) ofthe delayed signals under the control of clock control logic 286, thus allowing selection at an output such as 287 of a clock that is delayed by the same amount on both its rising and falling edges.
  • both the rising-edge delay and the falling edge delay can be separately specified at output 288, where latch 285 is set by the output of mux 283 and reset by the output of mux 284.
  • divider 289 provides the ability to divide the frequency ofthe clock from oscillator 280 as required for various clock requirements.
  • the ADC would not output the correct value for the condition of maximum difference between the reference level and the image level since the ADC cannot output negative values.
  • the dynamic range of the system would then be limited to 800 values.
  • the V ⁇ mg for a pixel n is measured; at block 472, the delay of P ⁇ mg for a subsequent pixel n+1 is increased slightly, and at block 474, the V ⁇ mg for the subsequent pixel n+1 is measured; at block 476 the V ⁇ mg(n+1) is compared to V ⁇ mg(n) and if it has changed significantly, control drops to block 478 where the delay is shortened by an empirically determined (or predetermined) amount to ensure operability ofthe system, and at block 480, this delay is saved for later use; and if at block 476 the measured V ref had not changed significantly, control is passed back in the loop to block 472 and the process is iterated until the "correct" timing edge is determined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
EP98938145A 1997-07-31 1998-07-30 Kamera mit digitaler korrelierter doppelabtastung Withdrawn EP1000506A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US90415997A 1997-07-31 1997-07-31
US904159 1997-07-31
PCT/US1998/015848 WO1999007138A1 (en) 1997-07-31 1998-07-30 Digital correlated double sample camera

Publications (1)

Publication Number Publication Date
EP1000506A1 true EP1000506A1 (de) 2000-05-17

Family

ID=25418679

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98938145A Withdrawn EP1000506A1 (de) 1997-07-31 1998-07-30 Kamera mit digitaler korrelierter doppelabtastung

Country Status (2)

Country Link
EP (1) EP1000506A1 (de)
WO (1) WO1999007138A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005014296A1 (de) * 2005-03-24 2006-09-28 Man Roland Druckmaschinen Ag Bogenhinterkantenstütze

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Publication number Priority date Publication date Assignee Title
JP4454750B2 (ja) * 1999-12-28 2010-04-21 日本バーブラウン株式会社 イメージセンサ用のフロントエンド信号処理の方法および装置
JP2002057581A (ja) 2000-08-10 2002-02-22 Sony Corp サンプリング処理装置及びこれを用いた撮像装置
KR100360415B1 (ko) * 2001-02-28 2002-11-13 삼성전자 주식회사 입력 영상 신호의 동적 범위를 넓히고 라인 노이즈를최소화할 수 있는 클램프 회로 및 방법
US6830387B2 (en) 2002-12-17 2004-12-14 Raytheon Company Modular thermal security camera system
US7385636B2 (en) 2004-04-30 2008-06-10 Eastman Kodak Company Low noise sample and hold circuit for image sensors
EP2183910B1 (de) * 2007-07-30 2021-08-25 Contour IP Holding, LLC Komponenten einer tragbaren digitalvideokamera
US11212424B2 (en) * 2018-10-05 2021-12-28 Synaptics Incorporated Device and method for compensation of power source voltage drop
US11331818B2 (en) * 2018-10-11 2022-05-17 Foster-Miller, Inc. Remotely controlled packable robot
US11812187B2 (en) 2021-05-28 2023-11-07 Varex Imaging Corporation Combined imaging array and strip
US11750944B2 (en) 2021-05-28 2023-09-05 Varex Imaging Corporation Pixel noise cancellation system

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NL8901019A (nl) * 1989-04-24 1990-11-16 Philips Nv Sensorschakeling voor gecorreleerde dubbele signaalbemonstering.
JPH04184509A (ja) * 1990-11-20 1992-07-01 Canon Inc サンプルホールド回路
EP0579838B1 (de) * 1992-01-08 1998-09-09 Ikegami Tsushinki Co., Ltd. Festkörperbildaufnahmevorrichtung und -element hierfür
US5321315A (en) * 1992-03-09 1994-06-14 Eastman Kodak Company Tracking control pulse generation for variable frame rate CCD sensors for electronic imaging applications
CA2121610C (en) * 1993-04-27 1999-09-21 Fumikazu Nagano Image scanning device
US5659355A (en) * 1994-10-31 1997-08-19 Eastman Kodak Company CCD dark mean level correction circuit employing digital processing and analog subtraction requiring no advance knowledge of dark mean level

Non-Patent Citations (1)

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See references of WO9907138A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005014296A1 (de) * 2005-03-24 2006-09-28 Man Roland Druckmaschinen Ag Bogenhinterkantenstütze

Also Published As

Publication number Publication date
WO1999007138A1 (en) 1999-02-11

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