Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
  • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
  • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66234—Bipolar junction transistors [BJT]
  • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
  • H01L29/66333—Vertical insulated gate bipolar transistors
  • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate

Definitions

• This invention relates to methods of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect power transistor (commonly termed a "MOSFET”) or an insulated-gate bipolar transistor (commonly termed an "IGBT").
• MOSFET insulated-gate field-effect power transistor
• IGBT insulated-gate bipolar transistor
• Such trench-gate semiconductor devices are known having source and drain regions of a first conductivity type separated by a channel-accommodating body region of the opposite second conductivity type.
• An advantageous method of manufacture is disclosed in United States patent US-A-5,378,655 (our reference PHB 33836), in which the formation of the source region is self- aligned with the trench (also termed "groove") which comprises the gate.
• the self-alignment is achieved by forming a second mask from a first mask, by the provision of sidewall extensions on the first mask. These sidewall extensions act as self-aligned spacers.
• the method of US-A-5,378,655 includes the steps of:
• United States patent US-A-5, 665,619 describes a modified extension of this known method, in which the trench is defined and filled with silicon gate material using an etchant mask which is of complementary window pattern to the first mask and comprises silicon nitride.
• the silicon nitride masks underlying areas of the body against oxidation while oxidising an upper part of the gate material to form the first mask.
• Being of a differently-etchable material (silicon nitride) from the first mask (silicon dioxide) a subsequent etch-removal of the silicon nitride leaves the first mask (silicon dioxide) as the desired protruding step.
• Trench-gate semiconductor devices are also known in which the channel-accommodating body region is of the same, first conductivity type as the source and drain regions.
• the conductive channel is formed by charge-carrier accumulation by means of the trench-gate. Similar considerations arise with respect to the doping of the regions and the etching of the trench, as in the more usual device in which the channel-accommodating region is of the opposite, second conductivity type.
• a source region is formed by introducing dopant of a first conductivity type into an area of a semiconductor body via a first window in a first mask at a surface of the body, sidewall extensions of the first mask are provided at the first window so as to form a second mask having a second window smaller than the first window, a trench is etched into the body at the second window to extend through the source region and into an underlying drain region of the first conductivity type, a gate is provided in the trench, and a source electrode is provided at the surface of the body.
• the method as set out in Claim 1 includes quite different steps (a) to (f) from the method steps of US-A-5,378,655.
• the trench is etched at the smaller window in the second mask, either before or after providing the source region dopant at the window in the first mask.
• the remaining (contactable) area of the source region at the surface of the body is related to the lateral extent of the side-wall extensions of the first mask.
• This technology can be chosen to give the side-wall extensions a well-defined lateral extent on the surface of the body.
• the interface location between the source region and the adjacent region at the surface of the body is defined by the first window in the first mask.
• dopant of an opposite second conductivity type may be introduced into an area of the body via the complementary window in the previous mask before forming the first mask at the complementary window.
• a doping step may be used to form, for example, a localised region of the second conductivity type which the source electrode contacts at the surface.
• This localised region which is formed via the window in the previous mask may be diffused deep into the body before forming the source region. In this way a deep opposite-conductivity-type region can be obtained to improve the blocking/breakdown characteristics of the device, without adversely affecting the doping profile of the (subsequently formed) source region.
• Figures 1 to 9 are a cross-sectional view of transistor cell areas of a semiconductor body at successive stages in the manufacture of a trench-gate semiconductor device by one example of a method in accordance with the present invention.
• Figures 10 and 11 are a cross-sectional view of the transistor cell areas of Figures 7 to 9 at successive stages in a modified manufacturing method which is also in accordance with the invention.
• Figure 12 is a cross-sectional view of the transistor cell areas of an accumulation-mode device which can also be manufactured by a modified manufacturing method in accordance with the invention. It should be noted that all the Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in different stages of manufacture and in modified and different embodiments.
• Figure 9 illustrates an exemplary embodiment of a power semiconductor device having a trench-gate 11.
• source and drain regions 13 and 14, respectively, of a first conductivity type (n-type in this example) are separated by a channel-accommodating region 15a of the opposite second conductivity type (i.e. p-type in this example).
• the gate 11 is present in a trench 20 which extends through the regions 13 and 15 into an underlying portion of the drain region 14.
• the application of a voltage signal to the gate 11 in the on-state of the device serves in known manner for inducing a conduction channel 12 in the region 15a and for controlling current flow in this conduction channel 12 between the source and drain regions 13 and 14.
• FIG. 9 shows a vertical device structure in which the region 14 may be a drain-drift region formed by an epitaxial layer of high resistivity on a substrate region 14a of high conductivity.
• This substrate region 14a may be of the same conductivity type (n-type in this example) as the region 14 to provide a vertical MOSFET, or it may be of opposite conductivity type (p-type in this example) to provide a vertical IGBT.
• the substrate region 14a is contacted at the bottom major surface 10b of the device body by an electrode 24, called the drain electrode in the case of a MOSFET and called the anode electrode in the case of an IGBT.
• the device of Figure 9 is manufactured by a method which, in overview of Figures 4 to 8, includes the steps of:
• a complementary masking technique is used to form the first mask 51 , so further reducing the requirement for separate mask alignments.
• a previous mask 53 of complementary window pattern to the first mask 51 is formed at the surface 10a of the body 10 before the step (a), and dopant 62 of the second conductivity type (acceptor dopant in this example) is introduced into an area of the body 10 via the complementary window 53a in the mask 53 before the first mask 51 is formed at this complementary window 53a in the step (a).
• the embodiment of Figures 1 to 9 is so designed that all the subsequent masking steps in the cell areas shown in Figures 1 to 9 can be determined in a self- aligned manner from the mask 53. This self-alignment permits a reproduceable close spacing of the transistor cells, for example with a cell pitch of less than 5 ⁇ m, i.e. with a spacing of 5 ⁇ m (or less) between the centres of the neighbouring trenches 20.
• FIG. 9 No plan view of the cellular layout geometry is shown in the drawings, because the method of Figures 1 to 9 may be used for quite different, known cell geometries.
• the cells may have a square geometry as illustrated in Figure 14 of US-A-5,378,655, or they may have a close-packed hexagonal geometry or an elongate stripe geometry.
• the trench 20 (with its gate 11) extends around the boundary of each cell.
• Figure 9 shows only a few cells, but typically the device comprises many hundreds of these parallel cells between the electrodes 23 and 24.
• the active cellular area of the device may be bounded around the periphery of the body 10 by various known peripheral termination schemes (also not shown).
• Such schemes normally include the formation of a thick field-oxide layer at the peripheral area of the body surface 10a, before the transistor cell fabrication steps.
• various known circuits such as gate-control circuits
• circuits may be integrated with the device in an area of the body 10, between the active cellular area and the peripheral termination scheme.
• their circuit elements may be fabricated with their own layout in this circuit area using some of the same masking and doping steps as are used for the transistor cells.
• Figure 1 illustrates the stage in which a p-type region 15 is formed in the low-doped n-type region 14 by implantation of acceptor dopant ions 61 , for example of boron.
• the implantation is carried out in the active cellular area defined by a window in the thick field-oxide layer (not shown).
• a thin layer 16 of silicon dioxide may be grown on the silicon body surface 10a, before implanting the ions 61.
• a heating step may be carried out to diffuse subsequently the implanted dopant to the desired depth for the region 15 in the body 10. This heating step may be delayed until after the ion implantation illustrated in Figure 2.
• the mask 53 is now provided at the body surface 10a.
• This mask 53 can be formed by depositing silicon dioxide material, and by subsequently opening the windows 53a using known photolithographic and etching techniques. In this way, a well defined window-edge can be formed for the mask 53.
• the thickness of the oxide mask 53 may be, for example, in the range of 1 ⁇ m to 1.5 ⁇ m.
• the mask 53 has an hexagonal grid pattern if an hexgonal geometry device is being manufactured.
• the windows 53a are narrow, for example 0.5 ⁇ m to 1 ⁇ m in width.
• a second ion implantation of, for example, boron ions 62 is now carried out.
• the oxide mask 53 is of sufficient thickness to mask the underlying silicon body 10 against this implantation, except at the windows 53a.
• the implanted dopant forms localised, highly-doped p-type regions 15b. These localised regions 15b can be formed from the surface 10a to a greater depth in the body 10 than the previously-implanted body region 15.
• a heating step may now be carried out to anneal and diffuse the implanted dopant 62 (and 61) to the desired depth.
• a thick layer 51' of silicon nitride is then deposited, for example using a known plasma enhanced chemical vapour deposition (PECVD) technique. As illustrated in Figure 3, the silicon nitride is deposited in a thickness sufficient to fill the narrow windows 53a in the oxide mask 53 and to have a substantially flat upper surface.
• the silicon nitride layer 51 is then subjected to a known planarizing etch treatment, which etches back the layer 51' to re-expose the oxide mask 53 and to leave narrow silicon nitride pillars in the windows 53a.
• the structure of Figure 4 is obtained by etching away the oxide mask 53, using a known selective etching treatment for silicon dioxide.
• the narrow silicon nitride pillars then remain at the body surface 10a as the mask 51.
• n-type regions 13 has, for example, an hexagonal dot pattern in the case of hexagonal geometry cells.
• An implantation of donor ions 63 (for example of phosphorous or arsenic) is now carried out to form the n-type regions 13 at the windows 51a.
• the silicon nitride mask 51 is of sufficient thickness to mask the underlying surface areas against this implantation of the donor ions 63.
• a heating treatment for annealing this donor implant may be carried out either now or later.
• the n-type regions 13 are self-aligned in complementary manner with the deep p-type regions 15b.
• a second silicon nitride layer 52' is now deposited over the layer structure at the surface 10a.
• the thickness of the layer 52' may be, for example, about
• the upper surface of the layer 52' is not flat but has a contour determined by the upstanding pillars forming the mask 51 at the surface 10a.
• the silicon nitride layer 52' is now uniformly etched back until central areas of the original windows 51a are once again opened. Due to the contoured upper surface of the layer 52', this general etch-back leaves side wall extensions 52b on the first silicon nitride mask 51.
• the resulting second silicon nitride mask 52 comprises the first mask 51 together with self-aligned spacers formed by these side wall extensions 52b.
• the resulting smaller window 52a of the mask 52 is therefore self-aligned with the wide windows 51a of the mask 51.
• This composite structure of the mask 52 is illustrated in Figure 6.
• an etching treatment is now carried out at the smaller windows 52a of the mask 52.
• this oxide layer 16 is first etched away at the windows 52a.
• a silicon-etching treatment is then carried out in known manner, using the silicon nitride mask 52 as an etchant mask, to etch the trench 20 into the silicon body 10 at the windows 52a.
• the resulting structure is illustrated in Figure 6.
• the layout pattern of the trench 20 is an hexagonal grid when an hexgonal geometry device is being manufactured.
• the silicon body 10 is now subjected to an oxidation treatment to form a thin silicon dioxide layer 17 on the exposed faces of the trench 20, while using the silicon nitride mask 52 to mask the silicon surface 10a against oxidation.
• the gate 11 may now be formed in known manner, by depositing doped polycrystalline silicon and then etching back the deposited polycrystalline silicon until it is left only in the trench 20.
• the resulting structure is illustrated in Figure 7.
• a further oxidation treatment is now carried out to form an insulating overiayer 18 of silicon dioxide over the gate 11 in the trench 20.
• the silicon nitride mask 52 protects against oxidation the silicon body areas between the trenches 20.
• the insulating overiayer 18 is formed by oxidation of the upper part of the deposited silicon material in the trench 20. The resulting structure is illustrated in Figure 8.
• the silicon nitride mask 52 is now removed by etching, and the silicon surface 10a is exposed between the insulating overlayers 18 on the trench- gates 11.
• an oxide etching treatment is carried out to remove the layer 16. This oxide etching treatment also thins slightly the insulating overlayers 18.
• Electrode material for example aluminium is now deposited to provide the source electrode 23 in contact with the exposed silicon surface 10a of the regions 13 and 15.
• the lateral extent of the source electrode 23 is determined in known manner by photolithographic definition and etching of the deposited electrode material.
• the source electrode 23 can also extend on the insulating overiayer 18 over the trench-gate 11.
• the higher doping of the region 15b as provided by the implanted dopant 62 forms a good contact region at the silicon body surface 10a.
• this contact region 15b extends to a greater depth in the body 10 than does the channel- accommodating region 15a, so improving the blocking characteristics of the pn junction between regions 14 and 15.
• this region 15b extends slightly deeper in the body 10 than does the trench 20. It will be evident that many variations and modifications are possible within the scope of the present invention.
• the insulating overiayer 18 is formed by oxidising the upper part of the deposited silicon material in the trench 20. However, an insulating overiayer 18 over the trench-gate 11 may be formed by deposition of an insulating material which is differentially etchable with respect to the material of the mask 52. In the process described for Figures 2 to 7, the mask 53 was of silicon dioxide, whereas the masks 51 and 52 were of silicon nitride.
• the mask 53 is of silicon nitride
• one or more of the subsequently deposited layers 51' and/or 52' is of silicon dioxide.
• other differently-etchable materials may be used for the masks 51 , 52 and 53.
• the mask 51 and the sidewall extensions 52b are of the same material, and both 51 and 52b are removed together after the Figure 8 stage.
• the source region 13 is formed in Figure 4, and the trench is etched in Figure 6. This process sequence is particularly convenient.
• modifications are possible.
• Figures 10 and 11 illustrate a modification in which the mask 51 and the sidewall extensions 52 are of differently-etchable materials, and the source region 13 is formed later.
• no implantation with ions 63 is carried out at the Figure 4 stage, and so the structure of Figure 10 (without any source region 13) is obtained at the Figure 7 stage.
• the sidewall extensions 52 are etched away to leave the mask 51 at the surface 10a, and the Figure 11 implantation of dopant ions 63 is then carried out to form the source region 13.
• Figure 11 shows the insulating overiayer 18 present during this dopant ion implantation.
• This overiayer 18 may be formed by depositing a differently- etchable insulating material at the windows 52a, and then etching away the sidewall extensions 52. If it is desired to form the insulating overiayer 18 of Figure 11 by oxidation of the gate material, then the sidewall extensions 52 may be of silicon nitride, and the mask 51 may comprise, for example, a multiple layer of silicon dioxide and silicon nitride.
• the conductive gate 11 is formed of doped polycrystalline silicon as described above. However, other known gate technologies may be used in particular devices. Thus, for example, other materials may be used for the gate, such as a thin metal layer which forms a suicide with the polycrystalline silicon material.
• the whole gate 11 may be of a metal instead of polycrystalline silicon.
• Figure 9 illustrates the preferred situation of an insulated gate structure, in which the conductive gate 11 is capacitively coupled to the channel-accommodating region 15a by a dielectric layer 17.
• so-called Schottky gate technologies may alternatively be used in which a gate dielectric layer 17 is absent and the conductive gate 11 is of a metal that forms a Schottky barrier with the low-doped channel-accommodating region 15a.
• the Schottky gate 11 is capacitively coupled to the channel-accommodating region 15a by the depletion layer present at the Schottky barrier.
• Figure 1 illustrates the provision of the doping profile for the channel- accommodating region 15a (by implantation of dopant ions 61) before forming the deep localised region 15b.
• the doping profile for the channel- accommodating region 15a may be provided later, for example by implantation of dopant ions 61 at the window 51a in the mask 51 of Figure 4. This implantation of the dopant ions 61 at the window 51a in the mask 51 may be carried out before implanting the source dopant ions 63 of Figure 4.
• the use of separate doses of ions 61 and 62 is advantageous to optimise the doping profiles for the channel-accommodating region 15a and the deep localised region 15b.
• modified processes may be acceptable for some devices in which, for example, a doped epitaxial layer is deposited to form the body region 15 in Figure 1.
• the doping profile for the channel-accommodating region 15a may even be formed by implantation of the ions 62 through a thinner mask 53, while the deeper region 15b is formed simultaneously by the ions 62 implanted at the windows 53a.
• the device of Figure 9 has localised, highly-doped (P+) p-type regions 15b which extend to a greater depth than the p-type channel-accommodating region 15a.
• This P+ deep localised region 15b in each cell improves the blocking/breakdown characteristics of the device.
• devices may be manufactured in accordance with the invention, without requiring the Figures 2 and 3 stages for providing a deep P+ region 15b. This can result in smaller cells, as well as a simplified process.
• the device may have only a shallow P+ region 15b which can be provided between the Figures 8 and 9 stages; a known example of the use of only a shallow P+ region in a known trench-gate MOSFET is given by US-A-5,665,619.
• the device manufactured in accordance with the invention may even have no P+ extra region 15b; US-A-5,378,655 provides a known example of the absence of an extra P+ region in a known trench-gate MOSFET.
• the particular example described above is an n-channel device, in which the regions 13 and 14 are of n-type conductivity, the regions 15a and 15b are of p-type, and an electron inversion channel 12 is induced in the region 15a by the gate 11.
• a p-channel device can be manufactured by a method in accordance with the invention, in which the regions 13 and 14 are of p-type conductivity, the regions 15a and 15b are of n-type, and a hole inversion channel 12 is induced in the region 15a by the gate 11.
• FIG. 12 illustrates a particular example of such a device of the p-channel type, having p-type source and drain regions 13 and 14a, a p-type channel-accommodating region 15a, and an n-type deep localised region 15b.
• the channel-accommodating region 15a may be provided by a low-doped (P-) p-type epitaxial layer which forms the body region 15 of the same conductivity type as the source and drain regions 13 and 14a.
• This epitaxial layer 15 may be grown on a slightly higher doped (P) p-type epitaxial layer 14' on a highly doped (P+) p-type substrate region 14a.
• the n-type deep localised region 15b is formed by implantation and thermal diffusion similar to Figures 2 and 3, but extending through the depth of the p-type layer 15 and into the p-type layer 14'.
• the p-type source regions 13 and trench-gates 11 are formed by similar stages to Figures 4 to 8.
• N-type polycrystalline silicon may be used for the gate 11. In operation, a hole accummulation channel 12 is induced in the region 15a by the gate 11 in the on-state.
• the low-doped p-type regions 15a may be wholly depleted in the off-state, by depletion layers from the deep n-type region 15b and from the insulated gate 11.
• the retention of the layer 14' between the high doped substrate region 14a and the bottom of the region 15b provides a high avalanche break-down voltage for the p-n junction formed by the region 15b.
• a simplier device structure and process is also possible in which a single low-doped p-type epitaxial layer replaces the two layers 14' and 15.

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• Insulated Gate Type Field-Effect Transistor (AREA)
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• 1998
  • 1998-04-17 GB GBGB9808234.0A patent/GB9808234D0/en not_active Ceased
• 1999
  • 1999-03-29 KR KR10-1999-7011981A patent/KR100538603B1/ko not_active IP Right Cessation
  • 1999-03-29 EP EP99907817A patent/EP0996969B1/de not_active Expired - Lifetime
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  • 1999-03-29 WO PCT/IB1999/000537 patent/WO1999054918A2/en active IP Right Grant
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