EP0986785B1 - Circuit de vote majoritaire et methode associee - Google Patents

Circuit de vote majoritaire et methode associee Download PDF

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Publication number
EP0986785B1
EP0986785B1 EP98928701A EP98928701A EP0986785B1 EP 0986785 B1 EP0986785 B1 EP 0986785B1 EP 98928701 A EP98928701 A EP 98928701A EP 98928701 A EP98928701 A EP 98928701A EP 0986785 B1 EP0986785 B1 EP 0986785B1
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Prior art keywords
signal
majority
logical
signals
logical input
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German (de)
English (en)
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EP0986785A2 (fr
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Stefan Hans Bertil Davidsson
Ola Per Martinsson
Carl Michael Carlsson
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Telefonaktiebolaget LM Ericsson AB
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Telefonaktiebolaget LM Ericsson AB
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/187—Voting techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware

Definitions

  • the present invention generally relates to majority voting of signals, and in particular to a majority voting circuit, and also to testing and maintenance of majority voting.
  • Majority voting is frequently utilized in a wide variety of technical applications in many technical fields. In particular, majority voting is of great importance in fault tolerant or redundant systems. Examples of such systems are clock generating systems and data processing systems.
  • a majority voting circuit accepts a plurality of logical input signals to generate a logical output signal that is representative of the majority vote of the input signals.
  • the majority vote is generally performed according to the following simple Boolean expression: (A AND B) OR (A AND C) OR (B AND C), where A, B and C represent the logical levels of the signals that are input to the majority voting circuit. If all three input signals are present, the majority voting circuit sets the majority voted output signal to a high level if a majority of the three incoming signals are at high level, otherwise the output signal will be set to a low level. In the case of a single faulty input signal, the majority voting circuit will still be able to generate a correct output signal.
  • U.S. Patent 4,583,224 issued to Ishii et al. on April 15, 1986 relates to redundancy control, and in particular to fault tolerable redundancy control using majority vote logic.
  • a redundant control system in which three control signals from three equivalent signal processors are subjected to a majority vote operation in order to generate a single majority voted control signal.
  • the majority voted control signal is used for controlling an apparatus or system such as an atomic power plant.
  • the control signals are compared to each other, and if one of the control signals differs from the other control signals, then the different control signal is considered as abnormal and an error detection signal, corresponding to the abnormal signal, is generated.
  • a switching device receives the control signals, the error detection signal and the set signal for forwarding the control signals that are not associated with the error detection signal to a majority logic circuit, and for forwarding the set signal to the majority logic circuit instead of the abnormal control signal.
  • control system in U.S. Patent 4,583,224 is customized for static signals, and fail-safe control operation can be continued after the occurrence of faults in two of the three control channels only by previously determining which logical level "0" or "1" that is to be substituted for the abnormal control signal.
  • the majority voting must work such that a well defined and correct output signal is generated no matter if one or more input signals are faulty. If, as an example, majority voting is performed on dynamic or periodic signals such as clock signals, and one or more of the clock signals have stopped, then a correct output clock should be generated no matter if the input clock signals have stopped at a high or low logical level.
  • a further object is to provide a clock generating system and a corresponding method based on the improved majority vote hardware design.
  • Still another object of the invention is to enable testing and maintenance of the improved majority voting functionality . For maintenance reasons, it is desirable to be able to check that the majority voting functionality is actually working, without causing disturbances in the system.
  • a telecommunication switch normally includes a clock generating system which provides the circuits in the switch with clock and synchronization signals.
  • the clock generating system is normally redundant. Redundancy in the clock generating system is ensured by using multiple clock generating units.
  • the clock generating unit is manifolded, usually duplicated or triplicated.
  • These clock generating units are also referred to as clock modules. Assume by way of example that there are three independent clock modules in a telecommunication switch. Each clock module generates a clock signal and a lower frequency synchronization signal. It is usually desirable to make a main clock signal and a main synchronization signal out of the three clock signals and the three synchronization signals. For this purpose it is appropriate to use majority vote logic.
  • a 4MHz clock signal when a 4MHz clock signal is mentioned, it actually means a clock signal of 4.096 MHz.
  • a 24 MHz clock signal means a clock signal of 24.576 MHz
  • a 48 MHz clock signal means a clock signal of 49.152 MHz.
  • flip-flop will designate a conventional data flip-flop.
  • SIGNAL [x:0] (where x is a positive integer) indicates a signal of x+1 bits.
  • a first aspect of the invention relates to an improved and robust hardware design for majority voting.
  • the clock signals coming from the clock modules are monitored individually by separate clock monitors, one clock monitor for each clock signal, to see if the clock signals are running normally or not.
  • Each clock monitor detects if its corresponding clock signal has stopped or not, and generates a control signal which is representative of the status of the monitored clock signal.
  • a control signal having the logical level of "1" represents a stopped or otherwise faulty clock signal
  • a control signal having the logical level of "0" represents a correct and well-defined clock signal.
  • the generated control signals are sent to a level control unit.
  • the level control unit control the input levels to a majority voter in accordance with the control signals. Instead of clock signals that have stopped toggling, the level control unit selects signals of specific logical levels to be forwarded to the majority logic. The specific logical levels of these so called replacement signals are selected such that the replacement signals do not interfere with the remaining correct clock signals. In this way, the majority vote will still function even if more than one clock signal stops.
  • the level control unit corrects for faulty clock signals before the actual majority vote operation is performed by the majority voter, and in this sense, the improved majority vote hardware design is pre-corrective.
  • a clear advantage of the improved majority voting circuit according to the invention is that it is capable of handling two stopped clock signals no matter if the clock signals have stopped at a high or low logical level.
  • the inventive majority voting circuit is customized for dynamic or periodic input signals, such as clock and synchronization signals.
  • Fig. 1 is a schematic circuit diagram illustrating pertinent parts of an overall redundant clock generating system in a switch integrated circuit according to an illustrative embodiment of the invention.
  • the system basically comprises three clock modules CLM0, CLM1, CLM2, three clock monitors 12A-C, a level control unit 13, a majority voter 14 performing a majority vote operation, a phase-locked loop (PLL) 15 and a majority vote clock monitor 18.
  • the clock modules CLM0, CLM1 and CLM2 generate the clock signals CP1_0, CP1_1 and CP1_2, respectively.
  • the clock monitors 12A-C are loss-of-signal detectors.
  • Each one of the clock monitors 12A-C detects if the corresponding incoming clock signal is present or not, and sets its output control signal CP1_xERR (x is 0, 1 or 2) accordingly.
  • CP1_xERR x is 0, 1 or 2
  • the corresponding control signal CP1_xERR is set to a high logical level
  • the control signal CP1_xERR is set to a low logical level.
  • the control signals CP1_0ERR, CP1_1 ERR and CP1_2ERR from the clock monitors 12A-C are sent to the level control unit 13 which also receives the clock signals CP1_0, CP1_1 and CP1_2.
  • the level control unit 13 controls the input levels to the majority voter 14, and the level control is performed in accordance with the control signals CP1_0ERR, CP1_1ERR and CP1_2ERR. If all the incoming clock signals CP1_0, CP1_1 and CP1_2 are correct and well-defined, the clock monitors 12A-C will set their control signals such that the level control unit 13 becomes transparent, and consequently the clock signals are distributed to the majority voter 14 without level adjustment.
  • the level control unit 13 will force the clock signal or signals in question to a low or high logical level depending upon the particular failure situation.
  • the level control unit 13 is set to lock these faulty clock signals to different logical levels such that they do not interfere with the remaining clock signal when doing the majority vote.
  • the majority voter 14 performs a conventional majority voting operation on the signals CP1_0L, CP1_1L, CP1_2L that are sent into the voter 14 from the level control unit 13. Accordingly, the voter 14 generates a single majority voted output clock signal CP1_MV.
  • the clock monitors 12A-C, the level control unit 13 and the majority voter 14 constitute the main core, designated by reference numeral 11 in Fig. 1, of the improved majority vote hardware design according to the invention.
  • the majority voting circuit is utilized in a clock generating system, and the majority voted clock signal CP1_MV is sent to a phase-locked loop (PLL) 15 which generates a higher frequency clock signal CLK_48.
  • the majority voted clock CP1_MV has a frequency of 4 MHz
  • the PLL output clock CLK_48 has a frequency of 48 MHz.
  • the CLK_48 clock signal is advantageously used as system clock signal for the circuits of the switch, and as such passed to a clock distribution circuit (not shown) which provides the circuits in the switch with a system clock signal.
  • the phase locked loop (PLL) 15 preferably comprises a PLL output signal generating unit 16, and a feedback loop with a PLL frequency divider 17.
  • the PLL output signal generating unit 16 includes a phase detector, a filter and a voltage controlled oscillator (VCO).
  • VCO voltage controlled oscillator
  • the resulting majority voted main clock signal CP1_MV from the majority voter 14 is sent to the phase locked-loop 15, and the phase of the resulting main clock signal CP1_MV is used as a reference in the phase-locked loop 15.
  • the clock signal paths from the clock modules (not shown) to the phase-locked loop 15 are preferably combinatorial, such that there are no flip-flops in the clock signal paths.
  • the PLL frequency divider 17 is required in the feedback loop in order to get a feedback signal CLK4_90 of the same frequency as the input reference signal CP1_MV.
  • the VCO generates a 48 MHz clock and this clock is divided by 12 in the frequency divider 17.
  • the phase relation between the majority voted clock signal CP1_MV and the feedback clock signal CLK4_90 is compared in the phase detector, and the filter generates a control voltage in response to this comparison. The generated control voltage is used for regulating the frequency of the VCO.
  • the PLL 15 is provided in the system for several reasons.
  • the VCO in the PLL 15 raises the frequency by a factor of 12.
  • the PLL 15 also makes sure that the CLK_48 clock is phase synchronous to the majority voted clock CP1_MV, and the PLL 15 will continue running properly for a short period of time even if all input clock signals stop toggling. Other advantages of the phase-locked loop 15 will be described below.
  • the majority vote clock monitor 18 is not considered necessary for explaining the majority vote hardware design aspect of the invention. However, we will return to the majority vote clock monitor 18 later in connection with the majority vote supervision function.
  • Fig. 2 is a schematic circuit diagram of an illustrative clock monitor according to the invention.
  • the clock monitor of Fig. 2 is designed to react if the monitored clock signal CP1_x does not toggle for a predetermined detection time. If a predetermined number, such as three for example, of consecutive clock pulses are absent in the monitored clock signal CP1_x, the corresponding CP1_xERR control bit is set high.
  • the monitor measures the period time of the incoming clock signal CP1_x in terms of 24 MHz clock pulses. If the period time is too short or too long, the monitor sets the control bit.
  • the clock monitor comprises a meta stability protection flip-flop, also referred to as META1 flip-flop 21, two other flip-flops 22, 23, an inverter 24, an AND-gate 25, a 3-bit period time counter 26, and a combinatorial network 27.
  • a 24 MHz clock signal CLK_24 is provided to the flip-flops 21, 22, 23, and the period time counter 26.
  • the incoming clock signal CP1_x is clocked into the META1 flip-flop 21, which protects against meta stability, as the relation between the CP1_x clock and the CLK_24 clock is asynchronous.
  • the clock is passed through two additional flip-flops 22, 23, which with the inverter 24 and the AND-gate 25 generates a positive pulse NEW_PERIOD every time the CP1_x clock signal goes high.
  • the NEW_PERIOD signal is utilized to clear the 3-bit counter 26.
  • the counter 26 generates a TIME_CNT counter value which represents the period time of the CP1_x signal in terms of 24 MHz clock pulses.
  • the combinatorial network 27 is implemented by using the known programming language VERILOG and the known synthesizing program SYNOPSYS.
  • the functionality of the combinatorial network 27 is defined in a program written in VERILOG, and the synthesizing program SYNOPSYS transforms the VERILOG program into a hardware network of gates and flip-flops.
  • the period time represented by the TIME_CNT signal is approved by the combinatorial logic if the counter value TIME_CNT of the counter 26 is 4, 5, or 6 when NEW_PERIOD is high. If the period time is approved, then the control signal CP1_xERR is set low. If however, the TIME_CNT counter value is less than 4 or greater than 6 when NEW_PERIOD goes high, the period time is faulty and the CP1_xERR signal is set high. If NEW_PERIOD has not become high before the counter 26 reaches the counter value of 7, the counter 26 stops at this value.
  • Fig. 3 is a schematic timing diagram of signals involved in the operation of the clock monitor of Fig. 2.
  • Fig. 4 is a schematic circuit diagram of a level control unit and a majority voter according to the invention.
  • the level control unit 13 (Fig. 1) basically comprises three signal selectors (switches) 31, 32, 33, each having two input terminals for receiving input signals, a control terminal for receiving a respective one of the control signals CP1_xERR (x is 0, 1 or 2) from the clock monitors 12A-C and an output terminal for outputting one of the two input signals as a selector output signal CP1_xL (x is 0, 1 or 2).
  • Each selector receives a respective one of the dock signals CP1_x (x is 0, 1 or 2) at one of its two input terminals, and a constant level signal at the other input terminal.
  • two of the constant level signals are set to opposite logical levels; "0" and "1".
  • the "0"-terminal is connected to ground, and the "1 "-terminal is connected to the positive logic supply rail.
  • the selector 31 that is responsive to the clock signal CP1_0 receives the constant level signal "1”
  • the selector 32 that is responsive to the clock signal CP1_1 receives the constant level signal "0”.
  • the selector 33 that is responsive to the CP1_2 clock signal, receives the CP1_1ERR control signal, at its other input terminal.
  • the control signal CP1_1ERR may have a low or a high level, but in each particular failure situation the CP1_1ERR signal is either low or high, thus acting as a constant level signal at that time.
  • the level control unit 13 receives information, in the form of the control signals CP1_0ERR, CP1_1ERR, CP1_2ERR from the clock monitors 12A-C concerning the status of the input clock signals. Which one of the two input signals that will be selected as selector output signal CP1_xL for each one of the selectors 31, 32, 33 is controlled by the corresponding control signal CP1_xERR.
  • the functional operation of the level control unit 13 can be summarized as follows:
  • the selector output signals CP1_0L, CP1_1L and CP1_2L of the level control unit 13 are sent to the majority voter 14.
  • the majority voter 14 is a conventional unit which performs a majority voting operation on its input signals by means of simple AND-gates 34, 35, 36 and an OR-gate 37, thus producing a majority voted output signal CP1_MV.
  • the combination of the individual clock monitors 12A-C, the level control unit 13 and the majority voter 14 means that if one of the incoming clocks stops, the level control unit 13 sets the majority voter input levels such that the remaining two clocks are generally AND:ed together. If one more clock stops, the level control unit 13 sets the input levels to the majority voter 14 such that the output signals of the selectors that are associated with the clock signals that have stopped toggling, do not interfere with the remaining clock signal. In this way the remaining clock signal will be put through as the majority voted output clock signal CP1_MV.
  • phase-locked loop 15 (Fig. 1) which is connected to receive the majority voted output clock CP1_MV will transform the phase jump into a smooth transient.
  • the above majority vote control circuitry basically ensures that the majority voting functionality will still work even if two out of three clock signals stop.
  • the whole clock system in the switch becomes less sensitive to disturbances or malfunctions, which in turn leads to higher reliability and service availability.
  • Fig. 5 is a schematic flow diagram of a method for majority voting according to the invention.
  • the method relates to majority voting of at least three logical input signals in order to produce a majority voted output signal.
  • the input signals are periodic signals such as clock signals.
  • the input signals are monitored individually to generate, for each one of the logical input signals, a corresponding control signal which is representative of the status of the logical input signal.
  • the input signals are monitored by continuously checking the signal period time. If, as an example, the absence of a predetermined number of pulses in an input signal is detected, the corresponding control signal is set to the predetermined level of "1". As a consequence, a control signal having the logical level of "0" will represent a correct and well-defined input signal.
  • step B there is generated a first constant level signal of a first predetermined logical level, and a second constant level signal of a second predetermined logical level.
  • step C a selection procedure is performed by:
  • Another aspect of the invention relates to maintenance, supervision and testing of the improved majority voting functionality.
  • U.S. Patent 5,305,325 issued to Roos on April 19, 1994 relates to a method and device for testing and supervising majority votes in a multiplane digital time selector with at least three identical planes of equipment. Each one of the planes delivers an outgoing datastream. These datastreams are received by a majority vote circuit and subjected to a majority vote operation therein. An error is deliberately introduced in accordance with a predetermined pattern into the data streams to be majority voted. The datastreams are then compared to the majority voted data stream, and an alarm is emitted as a result of this comparison if an error is found in any of the datastreams coming to the majority vote circuit. An expected alarm caused by a deliberately introduced error is identified in order to distinguish from alarms caused by other errors.
  • the maintenance strategy according to the invention is to use a mix of preventive and corrective maintenance to maintain a high degree of in-service performance. As a result of this maintenance strategy, as much functionality as possible should be supervised by the maintenance system.
  • the clock and synchronization signals in particular are extremely vital for the switch system as well as for the whole digital telephone network synchronization. Consequently, it must be possible to check that the majority vote logic and its associated control logic are working.
  • a disturbance in the form of a missing clock pulse in the resulting majority voted clock signal CP1_MV, is produced by stopping two of the clock signals CP1_x. Furthermore, there is provided a majority vote clock monitor 18 (Fig. 1) which receives the majority voted clock signal CP1_MV and the CLK4 signal from the PLL divider 17. The CP1_MV clock and the CLK4 clock are compared to each other, and an alarm is selectively generated in dependence on the result of the comparison. The majority vote clock monitor 18 should be able to detect the provoked disturbance so that a majority vote alarm, also referred to as CPMF alarm, is generated. This requirement is met by stopping the clocks, one at a time, according to a predetermined first procedure.
  • the majority vote clock monitor must be fast enough to catch the missing clock pulse, before the majority voter 14 and its associated control logic 12A-C, 13 restore the majority voted clock.
  • the majority vote clock monitor 18 has to react faster than the clock monitors 12A-C that control the level control unit 13.
  • the clock monitors 12A-C and the level control unit 13 have to be so fast that the output signal of the phase-locked loop 15 is not influenced by the produced disturbance.
  • the disturbance must be removed by the filter of the phase-locked loop 15.
  • the PLL takes care of the missing clock pulse produced in testing the majority vote hardware, such that tests can be performed without causing disturbances. This is a clear advantage. Testing can be performed even on a routine basis without disturbing the system.
  • Fig. 6 is a schematic circuit diagram illustrating a monitor for the majority voted clock signal in detail.
  • the majority vote clock monitor 18 (Fig. 1) comprises multiplexers 41, 42, a first combinatorial network 43, a flip-flop 44, a second combinatorial network 45, and flip-flops 46, 47.
  • the flip-flops 44, 46 and 47 are all clocked by the 48 MHz CLK_48_M clock signal.
  • the majority vote clock monitor 18 compares the majority voted clock signal CP1_MV with the 4 MHz CLK4 clock signal produced by the PLL divider 17, and generates an alarm if there is a phase difference of 20 ns or more between the signals.
  • an alarm is generated if the PLL is 20 ns out of phase, compared to the normal 90 degrees phase relation to the CP1_MV clock signal when the PLL is locked.
  • the CLK4_90 signal also produced by PLL divider 17, is generated by the positive edge of the 48 MHz clock signal CLK_48, the majority voted clock signal CP1_MV will change level very close to the positive edge of this clock signal when the PLL 15 is in a locked state. For this reason, the CP1_MV clock is not checked when it is expected to change level, and the multiplexer 41 is utilized to set CP1_MV to a defined value (not active) during this 48 MHz clock period.
  • the output signal of the multiplexer 41 is referred to as CP1_MV_COMP.
  • CP1_MV_COMP The output signal of the multiplexer 41 is referred to as CP1_MV_COMP.
  • the CLK4 signal is sent to a multiplexer 42 to generate the signal CLK4_COMP.
  • the CLK4_COMP signal and the CP1_MV_COMP signal are sent to the first combinatorial network 43 which checks if these signals differ from each other. If everything is all right, then they are expected to be equal, otherwise the alarm should be set. If they differ from each other, a signal NOT_EQUAL is set high.
  • the alarm When set, the alarm may be asynchronous since the phase relation might change during certain conditions, e.g. when a clock signal stops, or when the PLL 15 is faulty and/or not locked.
  • the NOT_EQUAL signal is sent to the meta stability protection flip-flop 44 which takes care of possible meta stability, and produces the signal CP1_MV_ERR_ASYNC.
  • the second combinatorial network 45 receives the CP1_MV_ERR_ASYNC signal, a 4-bit PLL_DIV signal from the PLL divider 17, and an output signal HOLD_ALARM of the flip-flop 46.
  • the HOLD_ALARM signal from the flip-flop 46 is provided to the second combinatorial network 45 in a feedback loop.
  • the combinatorial network 45 generates two output signals, one of which is sent to the flip-flop 46, and one of which is sent to the flip-flop 47 to generate the stable alarm signal CP1_MV_ERR.
  • the first combinatorial network 43 and the second combinatorial network 45 are implemented by using the programming language VERILOG and the synthesizing program SYNOPSYS.
  • the CP1_1ERR control signal In order to be able to meet the requirement that two of the clock signals should be able to stop without getting a majority vote alarm, the CP1_1ERR control signal must be reclocked into the CLK_48 MHz clock system before it is utilized to control one of the selectors in the level control unit 13 (Fig. 1).
  • Figs. 7A-C are schematic timing diagrams of signals involved in the operation of the majority voted clock monitor of Fig. 6 when the majority voted clock signal is out of phase.
  • the CP1_MV(0) signal is 10 ns earlier than the CLK4 signal.
  • CP1_MV(1) is 10 ns later than CLK4, and in Fig. 7C, CP1_MV(2) is 30 ns later than CLK4.
  • the CP1_MV signal is referred to as CP1_MV(x) where x is 0, 1 or 2 to distinguish the different cases from each other.
  • the alarm CP1_MV_ERR also referred to as CPMF in Fig. 1, is generated by CP1_MV(2) as illustrated in Fig. 7C.
  • the minimum duration of the CP1_MV_ERR alarm is one 4 MHz cycle.
  • 'Pulse' indicates that the clock is working normally, whereas the terms 'Low' and 'High' indicate that the clock has stopped at a low level and a high level, respectively.
  • CSF_x (x is 0, 1 or 2) denotes the control signal CP1_xERR when it is acting as an alarm signal, and CPMF denotes the majority vote alarm.
  • the CSF_x (CP1_xERR) signals are generated by the clock monitors 12A-C.
  • Fig. 8 is a schematic flow diagram of a method for testing majority voting of a number of input signals.
  • step G the logical input signals are monitored individually to generate, for each one of the logical input signals, a corresponding control signal which is representative of the status of the logical input signal.
  • step H faulty input signals are corrected for by controlling the input levels to be majority voted in accordance with the monitored status.
  • step I a majority vote operation is performed on the controlled input levels to produce a majority voted output signal.
  • step J two of the input signals are stopped deliberately, one input signal at a time.
  • step K the status of the majority voted output signal is monitored.
  • step L an alarm is selectively generated in dependence on the monitored status of the majority voted output signal.
  • the step J of deliberately stopping the input signals is performed according to a first predetermined procedure, then an erroneous majority voted output signal caused by the deliberately stopped input signals is detected before the deliberately stopped input signals are corrected, and an alarm is generated in response to the detection. If, however, the step J of deliberately stopping the input signals is performed according to a second predetermined procedure, then an alarm is avoided.
  • the majority voted output signal is provided to a phase-locked loop (PLL) that generates a feedback signal, and the status of the majority voted output signal is monitored by comparing the majority voted signal to the feedback signal of the PLL.
  • PLL phase-locked loop
  • the method illustrated in the flow diagram of Fig. 8 is implemented by using the improved majority voting hardware design described above in connection with Figs. 1 to 4, and the majority vote clock monitor of Fig. 6.

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Claims (18)

  1. Circuit de vote majoritaire réagissant au moins à trois signaux logiques d'entrée pour produire un signal de sortie de vote majoritaire, ledit circuit comprenant :
    au moins trois moniteurs de signaux d'entrée (12), chacun d'entre eux pouvant être actionné pour surveiller un signal respectif parmi les signaux logiques d'entrée pour produire un signal de commande correspondant représentant l'état du signal logique d'entrée ;
    un générateur de signaux pour produire un premier signal de niveau constant d'un premier niveau logique prédéterminé et un second signal de niveau constant d'un second niveau logique prédéterminé ;
    un premier sélecteur de signal (31) comportant deux bornes d'entrée pour recevoir un premier des signaux logiques d'entrée sur l'une des bornes d'entrée et ledit premier signal de niveau constant sur l'autre borne d'entrée et une borne de commande pour recevoir le signal de commande qui correspond audit premier signal logique d'entrée, pour sélectionner un signal parmi ledit premier signal logique d'entrée et ledit premier signal de niveau constant, en tant que signal de sortie de sélecteur, en réponse au signal de commande correspondant ;
    un deuxième sélecteur (32) comportant deux bornes d'entrée pour recevoir un deuxième des signaux logiques d'entrée sur l'une des bornes d'entrée et ledit second signal de niveau constant sur l'autre borne d'entrée et une borne de commande pour recevoir le signal de commande qui correspond audit deuxième signal logique d'entrée, pour sélectionner un signal parmi ledit deuxième signal logique d'entrée et ledit second signal de niveau constant, en tant que signal de sortie de sélecteur, en réponse au signal de commande correspondant ; et
    un troisième sélecteur (33) comportant deux bornes d'entrée pour recevoir un troisième des signaux logiques d'entrée sur l'une des bornes d'entrée et un signal prédéterminé desdits signaux de commande sur l'autre borne d'entrée et une borne de commande pour recevoir le signal de commande qui correspond audit troisième signal logique d'entrée, pour sélectionner un signal parmi ledit troisième signal logique d'entrée et ledit signal de commande prédéterminé en tant que signal de sortie de sélecteur en réponse au signal de commande correspondant ; et
    un dispositif de vote majoritaire (14) réagissant auxdits signaux de sortie des sélecteurs pour produire le signal de sortie de vote majoritaire.
  2. Circuit de vote majoritaire selon la revendication 1, dans lequel les signaux logiques d'entrée sont des signaux périodiques et chacun desdits moniteurs de signaux d'entrée (12) comprend un moyen pour vérifier l'absence d'un nombre prédéterminé d'impulsions dans le signal logique d'entrée périodique et pour déterminer le niveau logique du signal de commande correspondant en fonction du résultat de ladite vérification.
  3. Circuit de vote majoritaire selon la revendication 2, dans lequel ledit moyen de vérification et de détermination comprend un moyen pour mesurer une période de temps du signal logique d'entrée et pour déterminer si ladite période de temps se trouve ou non à l'intérieur d'un intervalle prédéterminé.
  4. Circuit de vote majoritaire selon la revendication 1, comprenant en outre une boucle à verrouillage de phase (PLL, 15) réagissant au signal de sortie de vote majoritaire pour produire un autre signal logique de sortie.
  5. Circuit de vote majoritaire selon la revendication 4, dans lequel ladite PLL (15) comporte une boucle de réinjection avec un signal de réinjection, ledit circuit de vote majoritaire comprenant en outre un moniteur de signal de sortie de vote majoritaire (18) réagissant au signal de sortie de vote majoritaire et audit signal de réinjection pour produire un signal d'alarme de vote majoritaire, si le signal de sortie de vote majoritaire et ledit signal de réinjection ont un décalage l'un par rapport à l'autre qui dépasse une valeur prédéterminée.
  6. Circuit de vote majoritaire selon la revendication 1, comprenant en outre :
    un moyen pour arrêter délibérément deux des signaux logiques d'entrée, un signal d'entrée à la fois, selon une première procédure prédéterminée ; et
    un circuit moniteur pour surveiller l'état du signal de sortie de vote majoritaire et pour détecter un signal de sortie de vote majoritaire erroné provoqué par lesdits signaux d'entrée arrêtés délibérément, avant que lesdits signaux d'entrée arrêtés délibérément ne soient éliminés et remplacés par ledit premier signal de niveau constant, ledit second signal de niveau constant ou ledit signal de commande prédéterminé par les sélecteurs correspondants, de façon à produire une alarme en réponse à celui-ci.
  7. Circuit de vote majoritaire selon la revendication 1, comprenant en outre :
    un moyen pour arrêter deux des signaux logiques d'entrée, un signal d'entrée à la fois,
    des circuits pour surveiller l'état du signal de sortie de vote majoritaire et pour produire de façon sélective une alarme dépendant de l'état surveillé du signal de sortie de vote majoritaire, de façon que :
    si les deux signaux d'entrée sont arrêtés selon une première procédure prédéterminée, alors un signal de sortie de vote majoritaire erroné provoqué par lesdits signaux d'entrée arrêtés est détecté avant que lesdits signaux d'entrée arrêtés ne soient éliminés et remplacés et ladite alarme est produite en réponse à ladite détection ; et
    si les deux signaux d'entrée sont arrêtés selon une seconde procédure prédéterminée, alors ladite alarme est évitée.
  8. Circuit de vote majoritaire selon la revendication 1, dans lequel lesdits signaux logiques d'entrée sont des signaux d'horloge et le signal de sortie de vote majoritaire est un signal d'horloge principale.
  9. Procédé de vote majoritaire d'au moins trois signaux logiques d'entrée pour produire un signal de sortie de vote majoritaire, ledit procédé comprenant les étapes consistant à :
    surveiller (A) individuellement les signaux d'entrée pour produire, pour chacun des signaux logiques d'entrée, un signal de commande correspondant représentant l'état du signal logique d'entrée ;
    produire (B) un premier signal de niveau constant d'un premier niveau logique prédéterminé et un second signal de niveau constant d'un second niveau logique prédéterminé ;
    sélectionner (C) un signal parmi un premier signal logique d'entrée et ledit premier signal de niveau constant, en tant que premier signal sélectionné, en fonction du signal de commande correspondant ;
    sélectionner (C) un signal parmi un deuxième signal logique d'entrée et ledit deuxième signal de niveau constant, en tant que deuxième signal sélectionné, en fonction du signal de commande correspondant ;
    sélectionner (C) un signal parmi un troisième signal logique d'entrée et un signal prédéterminé desdits signaux de commande, en tant que troisième signal sélectionné, en fonction du signal de commande correspondant ; et
    effectuer (D) une opération de vote majoritaire sur ledit premier signal sélectionné, ledit deuxième signal sélectionné et ledit troisième signal sélectionné, pour produire le signal de sortie de vote majoritaire.
  10. Procédé de vote majoritaire, selon la revendication 9 dans lequel les signaux logiques d'entrée sont des signaux périodiques et ladite étape de surveillance comprend, pour chacun des signaux logiques d'entrée, les étapes consistant à :
    vérifier l'absence d'un nombre prédéterminé d'impulsions dans le signal logique d'entrée périodique ; et
    positionner le niveau logique du signal de commande correspondant en fonction du résultat de ladite vérification.
  11. Procédé de vote majoritaire selon la revendication 9, comprenant en outre l'étape (E) consistant à fournir le signal de sortie de vote majoritaire à une boucle à verrouillage de phase (PLL) pour produire un autre signal logique de sortie.
  12. Procédé de vote majoritaire selon la revendication 11, dans lequel la PLL comporte une boucle de réinjection avec un signal de réinjection, ledit procédé comprenant en outre les étapes consistant à :
    comparer le signal de sortie de vote majoritaire audit signal de réinjection ; et
    produire de façon sélective un signal d'alarme de vote majoritaire en fonction de ladite comparaison.
  13. Procédé de vote majoritaire selon la revendication 12, dans lequel l'alarme de vote majoritaire est produite si le signal de sortie de vote majoritaire et ledit signal de réinjection ont un décalage l'un par rapport à l'autre qui dépasse une valeur prédéterminée.
  14. Procédé de vote majoritaire selon la revendication 9, comprenant en outre les étapes consistant à :
    arrêter délibérément (J) deux des signaux logiques d'entrée, un signal d'entrée à la fois, selon une première procédure prédéterminée ;
    surveiller (K, L) l'état du signal de sortie de vote majoritaire de façon à produire une alarme de vote majoritaire, en conséquence desdits signaux d'entrée arrêtés délibérément.
  15. Procédé selon la revendication 14, dans lequel ledit premier signal de niveau constant est à l'état haut et ledit second signal de niveau constant est à l'état bas et ledit signal de commande prédéterminé utilisé à ladite étape de sélection dudit troisième signal sélectionné est le signal de commande qui correspond au deuxième signal logique d'entrée et dans lequel ladite première procédure prédéterminée d'arrêt délibéré des signaux d'entrée logique comprend les étapes consistant à :
    arrêter d'abord l'un quelconque des signaux logiques d'entrée ; et
    arrêter ensuite le signal logique d'entrée suivant à l'état haut si le premier signal logique d'entrée a été précédemment arrêté, sinon, si le deuxième ou le troisième signal logique d'entrée a été arrêté, arrêter le signal logique d'entrée suivant à l'état bas.
  16. Procédé de vote majoritaire selon la revendication 9, comprenant en outre les étapes consistant à :
    surveiller (K) l'état du signal de sortie de vote majoritaire ;
    produire de façon sélective (L) une alarme en fonction de l'état surveillé du signal de sortie de vote majoritaire ; et
    arrêter (J) deux des signaux logiques d'entrée, un signal d'entrée à la fois, selon une seconde procédure prédéterminée, de façon que ladite alarme soit évitée.
  17. Procédé selon la revendication 16, dans lequel ledit premier signal de niveau constant est à l'état haut et ledit second signal de niveau constant est à l'état bas, et ledit signal de commande prédéterminé utilisé à ladite étape de sélection dudit troisième signal sélectionné est le signal de commande qui correspond au deuxième signal logique d'entrée et dans lequel ladite seconde procédure prédéterminée d'arrêt des signaux logiques d'entrée comprend les étapes consistant à :
    arrêter d'abord l'un quelconque des signaux logiques d'entrée ; et
    arrêter ensuite le signal logique d'entrée suivant à l'état bas si le premier signal logique d'entrée a été précédemment arrêté, sinon, si le deuxième ou le troisième signal logique d'entrée a été arrêté, arrêter le signal logique d'entrée suivant à l'état haut.
  18. Procédé selon la revendication 9, dans lequel lesdits signaux logiques d'entrée sont des signaux d'horloge et le signal de sortie de vote majoritaire est un signal d'horloge principale.
EP98928701A 1997-06-06 1998-05-20 Circuit de vote majoritaire et methode associee Expired - Lifetime EP0986785B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9702176 1997-06-06
SE9702176A SE9702176L (sv) 1997-06-06 1997-06-06 En maskinvarukonstruktion för majoritetsval, samt test och underhåll av majoritetsval
PCT/SE1998/000955 WO1998055923A2 (fr) 1997-06-06 1998-05-20 Logique majoritaire

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EP0986785A2 EP0986785A2 (fr) 2000-03-22
EP0986785B1 true EP0986785B1 (fr) 2003-07-30

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JP (1) JP2002503371A (fr)
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AU (1) AU8043698A (fr)
BR (1) BR9809962A (fr)
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SE9702176D0 (sv) 1997-06-06
US6247160B1 (en) 2001-06-12
AU8043698A (en) 1998-12-21
JP2002503371A (ja) 2002-01-29
DE69816818D1 (de) 2003-09-04
WO1998055923A2 (fr) 1998-12-10
KR20010013491A (ko) 2001-02-26
DE69816818T2 (de) 2004-02-26
SE9702176L (sv) 1998-12-07
CN1259213A (zh) 2000-07-05
US6253348B1 (en) 2001-06-26
EP0986785A2 (fr) 2000-03-22
WO1998055923A3 (fr) 1999-03-04
BR9809962A (pt) 2000-08-01
CN1097775C (zh) 2003-01-01

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