EP0983555A1 - Adressierungsschema zur verdoppelung der übertragungsleistung einer mastergesteuerten slave-to-slave-kommunikation in einem beliebigen bussystem - Google Patents
Adressierungsschema zur verdoppelung der übertragungsleistung einer mastergesteuerten slave-to-slave-kommunikation in einem beliebigen bussystemInfo
- Publication number
- EP0983555A1 EP0983555A1 EP98917033A EP98917033A EP0983555A1 EP 0983555 A1 EP0983555 A1 EP 0983555A1 EP 98917033 A EP98917033 A EP 98917033A EP 98917033 A EP98917033 A EP 98917033A EP 0983555 A1 EP0983555 A1 EP 0983555A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- slave
- indirect
- bus
- index
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Definitions
- the data transfer of a value between two non-master-capable slaves (e.g. memory, 10 interface) on a bus system usually requires two bus cycles.
- the bus master reads the date from the source (slave 1). This data is then transferred to the destination (slave 2) in the second bus cycle.
- the addressing scheme according to the invention enables master-controlled data transmission between two slaves in only one bus cycle.
- Areas of application are systems of digital measurement technology, digital signal processing as well as all systems that require high transmission rates between two non-master capable bus users.
- the addresses of a bus system are usually represented by m address bits (A 0 ... A m y. Of these m address bits, x 0 address bits (A n0 ... A nQ .,., ⁇ ) Are used for each of n slaves on the bus Selection of this slave. These address bits are called “slave index” in the following. Additional y address bits (A m0 ... A m0 + y . 1 ) are used to select a register or a memory cell in which the "slave index" selected slave. These y address bits are called “internal address” in the following.
- the object of the invention was to transmit data between two non-master-capable bus users, so-called slaves, within one bus cycle.
- DMA controllers can be used, even if the description basically speaks of a master. This means the current bus master of the bus. It can also be used if, in addition to the slaves a and b used in the following description, further slaves are connected to the bus. It can also be used for any pair of slave a and slave b on the same bus system.
- Indirect read access enables direct data transmission from one slave a to another slave b (see FIG. 1).
- the source (slave a) is selected as in a normal read access by the "slave index”.
- the target (slave b) is selected by the "Indirect Index”.
- the source of the requested date within slave a is defined by the "Internal Address”, while the destination of the date within slave b is given implicitly by the selection of slave b with the "Indirect Index”.
- the bus master is taken over by the bus master.
- Indirect read access is largely identical to normal read access.
- a master reads the date addressed with the "Internal Address" from a slave a selected by the "slave index”. This read access becomes an indirect read access if a further slave b is activated by the "Indirect Index”. The slave b can thus take over the data requested by the master from slave a.
- the addressing of the date within slave b is implicitly given by the "Indirect Index”.
- An example of the application of indirect read access is the output of data from the working memory to an output unit, e.g. B. a parallel port on the bus system.
- Indirect write access enables direct data transmission from one slave b to another slave a (see FIG. 2).
- the destination (slave a) is selected as in a normal write access by the "slave index”.
- the source (slave b) is selected using the "Indirect Index”.
- the source of the requested date within slave b is implicitly given by the selection of slave b with the "Indirect Index”, while the destination of the date within slave a is defined by the "Internal Address”.
- bus control is taken over by the bus master.
- An indirect write access is largely identical to a normal write access.
- a master transmits a date to a slave a selected by the "slave index", the destination of which is explicitly defined within slave a by the "Internal Address”.
- This write access becomes an indirect write access if another slave b is activated by the "indirect index”.
- Slave b then, instead of the master, sets the date to be transmitted for slave a on the bus ready.
- the addressing of the date within slave b is implicitly given by the "Indirect Index”.
- An example of the application of indirect write access is the reading in of data from an input unit on the bus system, e.g. B. a parallel port in the RAM.
- An inverse indirect read access like the indirect read access, enables direct data transmission between two slaves within the scope of a read cycle by the bus master (cf. FIG. 3).
- the source (slave b) is selected using the "Indirect Index”.
- the target (slave a) is selected by the "slave index”.
- the source of the requested date within slave b is implicitly given by the "Indirect Index”, while its destination within slave a is defined by the "Internal Address”.
- bus control is taken over by the bus master.
- An inverse indirect read access is largely identical to an indirect read access. However, the direction of data transmission is opposite.
- the slave b selected by the "Indirect Index” serves as the source and the slave a selected by the “Slave Index” serves as the destination.
- the "Internal Address” therefore defines the destination address in the receiving slave a.
- the "Indirect Index” defines the source address of the date in the sending slave.
- the functionality of the inverse indirect read access is therefore identical to the indirect write access.
- the master is able to insert and process the date transmitted from slave b to slave a.
- the inverse indirect read access is functionally identical to the indirect write access.
- a date implicitly addressed in the source is transferred to an explicitly addressed destination.
- the master can read in the transferred data for inverse indirect read access and process it if necessary.
- the reading of data from an input unit on the bus system e.g. B. a parallel port, called the RAM.
- Bus nodes that do not serve as a destination for an indirect read access or as a source for an indirect write access can be used without modification on a bus that supports indirect access with the addressing scheme described. They can even serve as a source for indirect read access or as a target for indirect write access without special adaptation. This applies in particular to working memory (RAM).
- RAM working memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
Description
Claims
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP1998/001644 WO1999049397A1 (de) | 1998-03-20 | 1998-03-20 | Adressierungsschema zur verdoppelung der übertragungsleistung einer mastergesteuerten slave-to-slave-kommunikation in einem beliebigen bussystem |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0983555A1 true EP0983555A1 (de) | 2000-03-08 |
Family
ID=8166912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98917033A Ceased EP0983555A1 (de) | 1998-03-20 | 1998-03-20 | Adressierungsschema zur verdoppelung der übertragungsleistung einer mastergesteuerten slave-to-slave-kommunikation in einem beliebigen bussystem |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0983555A1 (de) |
AU (1) | AU7039398A (de) |
WO (1) | WO1999049397A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19733906C2 (de) * | 1997-08-05 | 1999-09-30 | Siemens Ag | Verfahren zur automatischen Adreßvergabe, Bussystem zur automatischen Adreßvergabe und Kommunikationsteilnehmer, die im Bussystem bzw. im Rahmen des Verfahrens einsetzbar sind |
US7809873B2 (en) | 2008-04-11 | 2010-10-05 | Sandisk Il Ltd. | Direct data transfer between slave devices |
US9892077B2 (en) * | 2013-10-07 | 2018-02-13 | Qualcomm Incorporated | Camera control interface slave device to slave device communication |
TWI827561B (zh) * | 2017-11-03 | 2024-01-01 | 美商高通公司 | 具有遮罩寫入之無線電頻率前端裝置及其方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4001790A (en) * | 1975-06-30 | 1977-01-04 | Honeywell Information Systems, Inc. | Modularly addressable units coupled in a data processing system over a common bus |
DE3240141A1 (de) * | 1982-10-29 | 1984-05-03 | Loewe Opta Gmbh, 8640 Kronach | Verfahren und schaltungsanordnung zur bildlichen darstellung von texten, grafiken und symbolen auf bildschirmen von monitoren und/oder mittels punktgesteuerter drucker |
US5649142A (en) * | 1991-10-24 | 1997-07-15 | Intel Corporation | Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault |
-
1998
- 1998-03-20 AU AU70393/98A patent/AU7039398A/en not_active Abandoned
- 1998-03-20 WO PCT/EP1998/001644 patent/WO1999049397A1/de not_active Application Discontinuation
- 1998-03-20 EP EP98917033A patent/EP0983555A1/de not_active Ceased
Non-Patent Citations (1)
Title |
---|
See references of WO9949397A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU7039398A (en) | 1999-10-18 |
WO1999049397A1 (de) | 1999-09-30 |
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Legal Events
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Inventor name: DSPECIALISTS GESELLSCHAFT FUER INNOVATIVE SIGNALVE |
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17Q | First examination report despatched |
Effective date: 20040223 |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: DSPECIALISTS DIGITALE AUDIO- UND MESSSYSTEME GMBH |
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Inventor name: DSPECIALISTS DIGITALE AUDIO- UND MESSSYSTEME GMBH |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
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Effective date: 20040719 |