EP0967588A1 - Anzeigesteuergerät mit Animationsschaltung - Google Patents

Anzeigesteuergerät mit Animationsschaltung Download PDF

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Publication number
EP0967588A1
EP0967588A1 EP99201879A EP99201879A EP0967588A1 EP 0967588 A1 EP0967588 A1 EP 0967588A1 EP 99201879 A EP99201879 A EP 99201879A EP 99201879 A EP99201879 A EP 99201879A EP 0967588 A1 EP0967588 A1 EP 0967588A1
Authority
EP
European Patent Office
Prior art keywords
data
screen
memory
circuit
screen controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99201879A
Other languages
English (en)
French (fr)
Inventor
Alain Boursier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP0967588A1 publication Critical patent/EP0967588A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area

Definitions

  • the invention relates to electronic equipment comprising a microprocessor, a liquid crystal display and a screen controller with memory. It relates to also a screen controller having a screen memory for storing data to be displayed on a liquid crystal display.
  • the invention in particular has applications for electronic equipment portable, for example for telephones.
  • LCD matrix screen controllers for example the PCF8549 controller sold by Philips Semiconductors, include in particular a screen memory in which a microprocessor of the equipment comes enter the data to be displayed on the screen via an external bus. The content of this memory must be modified by the microprocessor each time that one wishes modify the data to be displayed.
  • the invention aims to remedy these drawbacks, and in particular to allow to make screen animations at a lower cost in terms of charge of the microprocessor and energy consumption.
  • equipment and a screen controller according to the invention and such as described in the introductory paragraph are characterized in that said microprocessor includes means for transmitting commands to said screen controller, said screens commands indicating an operation to be performed on data stored in a source location of said memory, and said screen controller comprises means for processing to perform said operation.
  • the data exchanges that result from the screen animation have basically take place inside the screen controller integrated circuit.
  • the capacity of a internal link to an integrated circuit being much lower than that of an external link between integrated circuits, the consumption caused by the screen animation is therefore much lower.
  • the remote functions in the screen controller have been limited to the actual screen animation, which optimizes the size of the integrated circuit screen controller.
  • the cost price of an integrated circuit being proportional to its surface, this optimizes the manufacturing costs of the equipment. This is particularly important in the field of consumer electronics.
  • the optimization of the surface of the printed circuit is fundamental for the miniaturization of equipment.
  • the screen controller is provided with a buffer memory.
  • a buffer memory is for example used by the microprocessor for store specific data, for example fonts or icons.
  • the display of these shapes is then performed directly by the screen controller without microprocessor intervention.
  • these fonts or icons are stored in compressed form in the buffer memory, especially when two gray levels are sufficient to define them (a level for the bottom of the screen, and a level for the shape to display).
  • processing means make it possible to modify the data read before copying them to the destination memory location.
  • these processing means make it possible to perform video inversions, block filling, decompressing data read from the buffer.
  • FIG 1 there is shown by way of example a diagram of a mobile phone according to the invention.
  • This mobile telephone 1 notably comprises a matrix crystal screen liquids 2 which is connected to a screen controller 3.
  • the screen controller 3 receives controls of a microprocessor assembly 4 to which it is connected by a bus 5.
  • the assembly microprocessor 4 also ensures the conventional operation of the telephone which is symbolically represented in Figure 1 by dotted lines to an antenna 10 via a radio circuit 11, to a keyboard 12, and to an earpiece 13 and a microphone 14 via an audio circuit 15.
  • the foundations relating to the display on the screen are distributed between the microprocessor 4 of the telephone and the screen controller 3.
  • the microprocessor 4 essentially performs processing relating to addressing, and it provides to the screen controller 3 commands and addresses relating to the data to be processed.
  • the screen controller 3 performs the indicated commands.
  • FIG. 2 shows an example of a block diagram of a controller classic screen.
  • This screen controller notably includes a circuit 20 for interfacing with the bus 5.
  • This interface circuit 20 is connected on the one hand to a circuit 30 for decoding the commands received and secondly to a voltage generator circuit 32 which is intended for power the liquid crystal screen 2.
  • the circuit 30 manages access to a screen memory 34 in which the data to be displayed are stored. And he controls a video sequencer 36 which manages the display on the screen via an amplified shift register 37 and a output amplifier 38.
  • the display is made line by line: on order of the video sequencer 36, each line to be displayed is read from the screen memory 34, stored in a register latch 39, then transmitted to the output amplifier 38 which controls the columns of the screen.
  • the shift register 37 controls the lines of the screen. Circuits 37 and 38 as well that the video sequencer 36 receive clock pulses from a circuit 40 time generator which is itself connected to an oscillator 41.
  • FIG. 3 there is shown a screen controller according to the invention.
  • This controller screen 3 comprises, in addition to the controller of FIG. 2, an animation circuit 50 which make changes and move blocks of points on the screen to allow to realize various animations.
  • This animation circuit 50 receives commands in from the command decoding circuit 30, and it has access to the screen memory 34 to read the data it has to process and enter the data to be displayed on the screen after treatment.
  • the screen controller 3 according to the invention also includes a memory buffer 52 which is used for storing intermediate data, and a device 54 for access management to memories 34 and 52.
  • This access management device 54 comprises a multiplexer 56 which is controlled by the control decoding circuit 30 to give access to memories either to the equipment microprocessor (via bus 5), either to the entertainment circuit 50.
  • It also includes a dual access circuit 58 which manages the interface between the multiplexer 56 or the register 39 on the one hand and the two memories 34 and 52 on the other hand.
  • This dual access circuit also receives clock pulses in from the time generator circuit 40 in order to control the writes in the register 39.
  • FIG. 4 shows a block diagram of the animation circuit 50. From a generally, this circuit makes it possible to carry out different modes of copies of a block of points (an icon or a character for example) from a source memory location to a destination memory location.
  • a block of points an icon or a character for example
  • the animation circuit 50 includes a source address generator circuit 61, a circuit 62 destination address generator, a circuit 63 for processing data which reads and writes data to screen memory 34 or buffer 52, a multiplexer 64 which makes it possible to address these two memories 34 and 52 from an address supplied either by the source address generator 61 or by the address generator destination 62, and a sequencer circuit 65 which controls the operation of circuits 61 and 62 for address generation and circuit 63 for data processing.
  • the source and destination address generator circuits 61 and 62 have the function of successively generate all memory addresses (source and destination respectively) which correspond to the block to be processed, starting from the first source address and the first destination address respectively.
  • the buffer memory and the screen memory correspond to two different areas of a RAM memory, called buffer area and screen area in the following from the description. These two areas are organized differently.
  • the buffer zone is a so-called adjacent area in which the data is stored adjacent to each other, i.e. that the data lines which constitute a block are stored one after the other other.
  • the screen area is a so-called fragmented area which is a screen representation. This means that the different lines of a block are not stored one after the other, but at the memory address corresponding to their location on the screen. To move from one line to another, it suffices to increment the memory address of a unit when the block is read in an adjacent memory.
  • FIG. 5 shows a block diagram of such a generation circuit address. It includes a multiplexer circuit 71 which is controlled by the sequencer 65, a register 72 for storing the current line start address, an address counter 73 which is also controlled by the sequencer 65, and an adder 74.
  • the multiplexer 71 has a first entry which receives the first source address S or destination D stored in registers 66, and a second entry which receives the address delivered by the adder 74.
  • the sequencer first sends an order to the multiplexer 71 so that the first source address S or destination D is copied to register 72.
  • the address stored in the register 72 is read by the address counter 73 which increments it by one.
  • the incremented address is then delivered at the output of the circuit address generator.
  • the adder 74 adds to the address read from the register 72 the value necessary to move to the next line of the block to be processed when the processed block is stored or must be stored in segmented memory.
  • the sequencer sends an order to multiplexer 71 so that the address provided by the adder 74 is stored in the register 72. The operation continues thus line after line until the end of the block.
  • incrementation by the address counter 73 continues until the last is reached block address.
  • the sequencer 65 reads parameters L, H, S and D from registers 66.
  • the circuit 63 includes three multiplexers 82, 84, 86, a register 88 intended to store the input data 80, two programmable registers 90 and 92 for store two gray levels coded on 2 bits each, two logic gates 94 and 96 which carry out the exclusive OR function, a logic gate 98 which performs the AND logic function.
  • the multiplexer 82 delivers the output data 81. This data is made up by the data present either on a first entry 100 or a second entry 102 of the multiplexer 82, depending on the high or low level respectively of a control signal C1 carried on a third input 104 of the multiplexer 82.
  • the first input 100 is constituted by an output 106 from gate 94 (OR exclusive).
  • This door 94 has a first input 107 which receives a signal command C2 and a second input 109 which receives the input data 80 stored in register 88.
  • Command C2 indicates whether the reverse video function is active. In that case (high level of signal C2) the data available on input 100 of multiplexer 82 correspond to the logical complement of the input data. Otherwise (level signal C2), they are identical to the input data.
  • the second input 102 of the multiplexer 82 is connected to an output 110 of the multiplexer 84.
  • This output 110 copies the data present on a first input 112 or on a second input 114 of the multiplexer 84, depending on the high or low level respectively of a control signal 116 carried on a third input 118 of the multiplexer 84.
  • the first and second inputs 112 and 114 of multiplexer 84 are respectively connected to the outputs of registers 90 and 92.
  • the third input 118 of the multiplexer 84 is connected to an output 120 of the gate 98 (AND gate).
  • Gate 98 has a first input 121 which receives a signal command C3, and a second input which is connected to an output 124 of door 96 (OR exclusive).
  • the door 96 is itself provided with a first input 126 which receives the signal C2 command, and a second input 127 which is connected to an output 128 of the multiplexer 86.
  • the multiplexer 86 is controlled by a control signal C4 which is carried on its first input 131. It copies on its output 128 one of the two bits carried on its input 132 depending on the high or low level of the control signal C4. Entrance 132 is connected to the exit from register 88.
  • control signal C1 When the control signal C1 is high, the selection mode is therefore selected. “simple copy without inverting data” operation (C2 control signal low), or “simple copy with data inversion” (C2 high control signal).
  • control signals C3 and C4 are used as follows.
  • the circuit operates in filling mode: the output of door 98 (door ET) is low so that the multiplexer 84 outputs the color, called color background (for example 00 or 01), stored in the programmable register 92.
  • the command C1 is low, the data 81 output is equal to the content of register 92 whatever the data 80 supplied as input. So there is filling of the block with the background color stored in register 92.
  • the circuit operates in conversion mode encoding format.
  • This operating mode has two stages. The first step is takes place when the control signal C4 is low and it consists of copying at the output of the multiplexer 86 the first of the 2 bits read in register 88. This bit is copied (after inversion if the C2 control signal indicates that one is in inversion mode) on the third input of multiplexer 84. If it is equal to 0, it is the background color contained in register 92 (for example 00 or 01) which is copied at the output of multiplexer 84. If it is equal to 1, it is the color, called shape color (for example 10 or 11), contained in the programmable register 90 which is copied at the output of the multiplexer 84.
  • the 2 bits thus obtained are delivered at the output of circuit 63.
  • the second step takes place when the control signal C4 is high, and it consists of copying at output from multiplexer 86 the second of the 2 bits read from register 88.
  • This step which is identical to the previous one, performs a format conversion from the second bit contained in the register 88.
  • the "encoding format conversion" function allows the microprocessor to store data in the buffer memory in a format of 1 bit per pixel to save space. For example it can be typefaces or icons whose points all have the same gray level. To be displayed on the screen, such data must be copied into the screen memory with a 2-bit format per pixel.
  • the microprocessor can store in the buffer memory a series of clock dials corresponding to different positions of the second hand.
  • a screen animation can then consist of successively displaying every second a series dial to give the impression that the needle is moving.
  • the controller must therefore read the corresponding icons (coded on 1 bit per pixel) in the buffer memory, decompress them, and write the data results (coded on 2 bits per pixel) in the screen memory.
  • the embodiment described does not allow the four to be dissociated screen points whose code is stored in the same location in the RAM memory. But in another embodiment it would be possible to do so, at the cost of complexity increased entertainment circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
EP99201879A 1998-06-23 1999-06-14 Anzeigesteuergerät mit Animationsschaltung Withdrawn EP0967588A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9807915 1998-06-23
FR9807915 1998-06-23

Publications (1)

Publication Number Publication Date
EP0967588A1 true EP0967588A1 (de) 1999-12-29

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EP99201879A Withdrawn EP0967588A1 (de) 1998-06-23 1999-06-14 Anzeigesteuergerät mit Animationsschaltung

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US (1) US6795062B1 (de)
EP (1) EP0967588A1 (de)
JP (1) JP2000029443A (de)
KR (1) KR20000006349A (de)
CN (1) CN1203455C (de)

Cited By (2)

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Publication number Priority date Publication date Assignee Title
EP1253578A1 (de) * 2000-10-26 2002-10-30 Matsushita Electric Industrial Co., Ltd. Bildanzeigegerät
WO2005083672A2 (en) * 2004-02-24 2005-09-09 Qualcomm Incorporated Display processor for a wireless device

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JP2003066938A (ja) * 2001-08-24 2003-03-05 Sharp Corp 表示コントローラ、表示制御方法、および画像表示システム
US20100318656A1 (en) * 2009-06-16 2010-12-16 Intel Corporation Multiple-channel, short-range networking between wireless devices
US8776177B2 (en) * 2009-06-16 2014-07-08 Intel Corporation Dynamic content preference and behavior sharing between computing devices
US8446398B2 (en) * 2009-06-16 2013-05-21 Intel Corporation Power conservation for mobile device displays
US9092069B2 (en) * 2009-06-16 2015-07-28 Intel Corporation Customizable and predictive dictionary

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US5650955A (en) * 1994-06-20 1997-07-22 Neomagic Corporation Graphics controller integrated circuit without memory interface

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WO1996041252A1 (en) * 1995-06-07 1996-12-19 Seiko Epson Corporation Computer system with video display controller having power saving modes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1253578A1 (de) * 2000-10-26 2002-10-30 Matsushita Electric Industrial Co., Ltd. Bildanzeigegerät
EP1253578A4 (de) * 2000-10-26 2004-03-31 Matsushita Electric Ind Co Ltd Bildanzeigegerät
WO2005083672A2 (en) * 2004-02-24 2005-09-09 Qualcomm Incorporated Display processor for a wireless device
WO2005083672A3 (en) * 2004-02-24 2005-12-08 Qualcomm Inc Display processor for a wireless device

Also Published As

Publication number Publication date
KR20000006349A (ko) 2000-01-25
CN1245948A (zh) 2000-03-01
US6795062B1 (en) 2004-09-21
CN1203455C (zh) 2005-05-25
JP2000029443A (ja) 2000-01-28

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