EP0967588A1 - Display controller with animation circuit - Google Patents

Abstract

The screen controller includes an animation circuit (50) which receives commands from a decoder (30) and modifies and moves blocks of points in the screen memory (34). Access to the screen memory (34) and a buffer memory (52) is controlled by an access manager (54) directed from the decoder (30). A double access circuit (58) controls traffic between a multiplexer (56), the memories (34,52) and a latch register (39)

Description

The invention relates to electronic equipment comprising a microprocessor, a liquid crystal display and a screen controller with memory. It relates to also a screen controller having a screen memory for storing data to be displayed on a liquid crystal display.

The invention in particular has applications for electronic equipment portable, for example for telephones.

Conventional LCD matrix screen controllers, for example the PCF8549 controller sold by Philips Semiconductors, include in particular a screen memory in which a microprocessor of the equipment comes enter the data to be displayed on the screen via an external bus. The content of this memory must be modified by the microprocessor each time that one wishes modify the data to be displayed.

When making screen animations (modification and / or movement of data displayed on the screen, progressive replacement of a screen or part of a screen, display rapid succession of images from a series ...), the load on the microprocessor increases therefore considerably. In addition, the number of exchanges on the external bus which connects the microprocessor to the screen controller also increases, resulting in increase in the energy consumed by the equipment.

Consumption problems are particularly important in the field portable electronics, since we are always looking to increase the autonomy of equipment. In addition, in the case of portable telephone equipment, microprocessors have a limited power which does not allow them to manage animations screen during the communication phase.

The invention aims to remedy these drawbacks, and in particular to allow to make screen animations at a lower cost in terms of charge of the microprocessor and energy consumption.

For this, equipment and a screen controller according to the invention and such as described in the introductory paragraph are characterized in that said microprocessor includes means for transmitting commands to said screen controller, said screens commands indicating an operation to be performed on data stored in a source location of said memory, and said screen controller comprises means for processing to perform said operation.

Thus, the actual movement operations are carried out by the screen controller which frees the microprocessor from the corresponding load.

In addition, the data exchanges that result from the screen animation have basically take place inside the screen controller integrated circuit. The capacity of a internal link to an integrated circuit being much lower than that of an external link between integrated circuits, the consumption caused by the screen animation is therefore much lower.

Finally, the remote functions in the screen controller have been limited to the actual screen animation, which optimizes the size of the integrated circuit screen controller. The cost price of an integrated circuit being proportional to its surface, this optimizes the manufacturing costs of the equipment. This is particularly important in the field of consumer electronics. Finally, the optimization of the surface of the printed circuit is fundamental for the miniaturization of equipment.

Note that the solution proposed here is particularly well suited to equipment with small screens and graphical functionality relatively small.

In an advantageous embodiment, the screen controller is provided with a buffer memory. Such a memory is for example used by the microprocessor for store specific data, for example fonts or icons. The display of these shapes is then performed directly by the screen controller without microprocessor intervention. Advantageously, these fonts or icons are stored in compressed form in the buffer memory, especially when two gray levels are sufficient to define them (a level for the bottom of the screen, and a level for the shape to display).

In an advantageous embodiment, processing means make it possible to modify the data read before copying them to the destination memory location. As for example, these processing means make it possible to perform video inversions, block filling, decompressing data read from the buffer.

• la figure 1 représente schématiquement un exemple d'équipement selon l'invention,
• la figure 2 est un schéma en blocs d'un contrôleur d'écran classique,
• la figure 3 est un schéma en blocs d'un contrôleur d'écran selon l'invention qui comporte notamment un circuit, dit circuit d'animation, pour modifier et déplacer des blocs à l'écran,
• la figure 4 un schéma en bloc du circuit d'animation de la figure 3,
• les figures 5 et 6 sont des schémas plus détaillés de certains blocs du circuit d'animation de la figure 4.

The invention will be better understood and other details will appear in the description which follows with reference to the appended drawings which are given by way of nonlimiting examples and in which:

• FIG. 1 schematically represents an example of equipment according to the invention,
• FIG. 2 is a block diagram of a conventional screen controller,
• FIG. 3 is a block diagram of a screen controller according to the invention which comprises in particular a circuit, called the animation circuit, for modifying and moving blocks on the screen,
• FIG. 4 a block diagram of the animation circuit of FIG. 3,
• FIGS. 5 and 6 are more detailed diagrams of certain blocks of the animation circuit of FIG. 4.

In Figure 1 there is shown by way of example a diagram of a mobile phone according to the invention. This mobile telephone 1 notably comprises a matrix crystal screen liquids 2 which is connected to a screen controller 3. The screen controller 3 receives controls of a microprocessor assembly 4 to which it is connected by a bus 5. The assembly microprocessor 4 also ensures the conventional operation of the telephone which is symbolically represented in Figure 1 by dotted lines to an antenna 10 via a radio circuit 11, to a keyboard 12, and to an earpiece 13 and a microphone 14 via an audio circuit 15.

According to the invention, the foundations relating to the display on the screen are distributed between the microprocessor 4 of the telephone and the screen controller 3. The microprocessor 4 essentially performs processing relating to addressing, and it provides to the screen controller 3 commands and addresses relating to the data to be processed. The screen controller 3 performs the indicated commands.

FIG. 2 shows an example of a block diagram of a controller classic screen. This screen controller notably includes a circuit 20 for interfacing with the bus 5. This interface circuit 20 is connected on the one hand to a circuit 30 for decoding the commands received and secondly to a voltage generator circuit 32 which is intended for power the liquid crystal screen 2. The circuit 30 manages access to a screen memory 34 in which the data to be displayed are stored. And he controls a video sequencer 36 which manages the display on the screen via an amplified shift register 37 and a output amplifier 38. The display is made line by line: on order of the video sequencer 36, each line to be displayed is read from the screen memory 34, stored in a register latch 39, then transmitted to the output amplifier 38 which controls the columns of the screen. In parallel, the shift register 37 controls the lines of the screen. Circuits 37 and 38 as well that the video sequencer 36 receive clock pulses from a circuit 40 time generator which is itself connected to an oscillator 41.

In Figure 3 there is shown a screen controller according to the invention. This controller screen 3 comprises, in addition to the controller of FIG. 2, an animation circuit 50 which make changes and move blocks of points on the screen to allow to realize various animations. This animation circuit 50 receives commands in from the command decoding circuit 30, and it has access to the screen memory 34 to read the data it has to process and enter the data to be displayed on the screen after treatment. The screen controller 3 according to the invention also includes a memory buffer 52 which is used for storing intermediate data, and a device 54 for access management to memories 34 and 52. This access management device 54 comprises a multiplexer 56 which is controlled by the control decoding circuit 30 to give access to memories either to the equipment microprocessor (via bus 5), either to the entertainment circuit 50. It also includes a dual access circuit 58 which manages the interface between the multiplexer 56 or the register 39 on the one hand and the two memories 34 and 52 on the other hand. This dual access circuit also receives clock pulses in from the time generator circuit 40 in order to control the writes in the register 39.

FIG. 4 shows a block diagram of the animation circuit 50. From a generally, this circuit makes it possible to carry out different modes of copies of a block of points (an icon or a character for example) from a source memory location to a destination memory location.

The animation circuit 50 includes a source address generator circuit 61, a circuit 62 destination address generator, a circuit 63 for processing data which reads and writes data to screen memory 34 or buffer 52, a multiplexer 64 which makes it possible to address these two memories 34 and 52 from an address supplied either by the source address generator 61 or by the address generator destination 62, and a sequencer circuit 65 which controls the operation of circuits 61 and 62 for address generation and circuit 63 for data processing.

• S: première adresse source (c'est-à-dire adresse source du premier point du bloc à traiter),
• D: première adresse destination (c'est-à-dire adresse destination du premier point du bloc à traiter),
• L: largeur du bloc à traiter,
• H: hauteur du bloc à traiter,
• C1, C2, C3 et C4: commandes de sélection du mode de fonctionnement du circuit de traitement 63 (on verra par la suite que le circuit 63 est doté de plusieurs modes de fonctionnement).

The parameters which are supplied to the animation circuit 50 by the equipment microprocessor are as follows:

• S: first source address (i.e. source address of the first point of the block to be processed),
• D: first destination address (i.e. destination address of the first point of the block to be processed),
• L: width of the block to be treated,
• H: height of the block to be treated,
• C1, C2, C3 and C4: commands for selecting the operating mode of the processing circuit 63 (we will see later that the circuit 63 has several operating modes).

These parameters are stored in registers 66 for use by the circuits 61, 62, 63 and 65 of the animation circuit 50.

The source and destination address generator circuits 61 and 62 have the function of successively generate all memory addresses (source and destination respectively) which correspond to the block to be processed, starting from the first source address and the first destination address respectively.

In practice, the buffer memory and the screen memory correspond to two different areas of a RAM memory, called buffer area and screen area in the following from the description. These two areas are organized differently. The buffer zone is a so-called adjacent area in which the data is stored adjacent to each other, i.e. that the data lines which constitute a block are stored one after the other other. On the contrary, the screen area is a so-called fragmented area which is a screen representation. This means that the different lines of a block are not stored one after the other, but at the memory address corresponding to their location on the screen. To move from one line to another, it suffices to increment the memory address of a unit when the block is read in an adjacent memory. When he is read in a segmented memory, add to the address at the start of the line the number of memory locations required to store an entire row. For example, when the RAM memory contains 8-bit words, that each point of the screen is coded on 2 bits (which allows to have 4 gray levels), and that the lines of the screen contain 104 points, it takes 26 memory locations to store a screen line. In the area segmented, so add 26 to a line start address to jump to the address start of next line in the same block.

FIG. 5 shows a block diagram of such a generation circuit address. It includes a multiplexer circuit 71 which is controlled by the sequencer 65, a register 72 for storing the current line start address, an address counter 73 which is also controlled by the sequencer 65, and an adder 74. The multiplexer 71 has a first entry which receives the first source address S or destination D stored in registers 66, and a second entry which receives the address delivered by the adder 74.

The sequencer first sends an order to the multiplexer 71 so that the first source address S or destination D is copied to register 72. By order of the sequencer 65, the address stored in the register 72 is read by the address counter 73 which increments it by one. The incremented address is then delivered at the output of the circuit address generator. The adder 74 adds to the address read from the register 72 the value necessary to move to the next line of the block to be processed when the processed block is stored or must be stored in segmented memory.

When, increment by increment, the entire line has been traversed, and the block processed is or must be stored in segmented memory, the sequencer sends an order to multiplexer 71 so that the address provided by the adder 74 is stored in the register 72. The operation continues thus line after line until the end of the block.

When the processed block is stored or must be stored in adjacent memory, incrementation by the address counter 73 continues until the last is reached block address.

The instants at which the sequencer 65 sends its orders to the multiplexer 71 and to the address counter 73 depend on the width L and the height H of the block to be treated, thus than the adjacent or segmented nature of the source or destination memory area. The sequencer 65 reads parameters L, H, S and D from registers 66.

• la copie simple dans laquelle les données de sortie 81 sont identiques aux données d'entrée 80,
• l'inversion vidéo qui consiste à complémenter les données 80 reçues en entrée,
• le remplissage du bloc,
• la conversion d'un codage des points de l'écran sur 1 bit à un codage sur 2 bits, avec éventuellement inversion vidéo.

FIG. 6 shows an example of a circuit 63 for processing data which makes it possible to perform, as a function of commands received C1, C2, C3 and C4, various processing operations on data 80 read in memory at the address indicated by the source address generator. The data 81 supplied at the output of circuit 63 are copied into memory at the address indicated by the destination address generator. In the embodiment described here, the different possible treatments are as follows:

• the simple copy in which the output data 81 is identical to the input data 80,
• video inversion which consists in supplementing the data 80 received as input,
• filling the block,
• the conversion of a coding of the points of the screen on 1 bit to a coding on 2 bits, with possibly video inversion.

For this, the circuit 63 includes three multiplexers 82, 84, 86, a register 88 intended to store the input data 80, two programmable registers 90 and 92 for store two gray levels coded on 2 bits each, two logic gates 94 and 96 which carry out the exclusive OR function, a logic gate 98 which performs the AND logic function.

The multiplexer 82 delivers the output data 81. This data is made up by the data present either on a first entry 100 or a second entry 102 of the multiplexer 82, depending on the high or low level respectively of a control signal C1 carried on a third input 104 of the multiplexer 82.

The first input 100 is constituted by an output 106 from gate 94 (OR exclusive). This door 94 has a first input 107 which receives a signal command C2 and a second input 109 which receives the input data 80 stored in register 88. Command C2 indicates whether the reverse video function is active. In that case (high level of signal C2) the data available on input 100 of multiplexer 82 correspond to the logical complement of the input data. Otherwise (level signal C2), they are identical to the input data.

The second input 102 of the multiplexer 82 is connected to an output 110 of the multiplexer 84. This output 110 copies the data present on a first input 112 or on a second input 114 of the multiplexer 84, depending on the high or low level respectively of a control signal 116 carried on a third input 118 of the multiplexer 84. The first and second inputs 112 and 114 of multiplexer 84 are respectively connected to the outputs of registers 90 and 92.

The third input 118 of the multiplexer 84 is connected to an output 120 of the gate 98 (AND gate). Gate 98 has a first input 121 which receives a signal command C3, and a second input which is connected to an output 124 of door 96 (OR exclusive). The door 96 is itself provided with a first input 126 which receives the signal C2 command, and a second input 127 which is connected to an output 128 of the multiplexer 86. The multiplexer 86 is controlled by a control signal C4 which is carried on its first input 131. It copies on its output 128 one of the two bits carried on its input 132 depending on the high or low level of the control signal C4. Entrance 132 is connected to the exit from register 88.

When the control signal C1 is high, the selection mode is therefore selected. "simple copy without inverting data" operation (C2 control signal low), or "simple copy with data inversion" (C2 high control signal).

The control signals C3 and C4 are used as follows. When the signal C3 is low, the circuit operates in filling mode: the output of door 98 (door ET) is low so that the multiplexer 84 outputs the color, called color background (for example 00 or 01), stored in the programmable register 92. If the command C1 is low, the data 81 output is equal to the content of register 92 whatever the data 80 supplied as input. So there is filling of the block with the background color stored in register 92.

If the C3 control signal is high, the circuit operates in conversion mode encoding format. This operating mode has two stages. The first step is takes place when the control signal C4 is low and it consists of copying at the output of the multiplexer 86 the first of the 2 bits read in register 88. This bit is copied (after inversion if the C2 control signal indicates that one is in inversion mode) on the third input of multiplexer 84. If it is equal to 0, it is the background color contained in register 92 (for example 00 or 01) which is copied at the output of multiplexer 84. If it is equal to 1, it is the color, called shape color (for example 10 or 11), contained in the programmable register 90 which is copied at the output of the multiplexer 84. If the command C1 is low, the 2 bits thus obtained are delivered at the output of circuit 63. We therefore performed a format conversion from the first bit contained in register 88. The second step takes place when the control signal C4 is high, and it consists of copying at output from multiplexer 86 the second of the 2 bits read from register 88. This step, which is identical to the previous one, performs a format conversion from the second bit contained in the register 88.

The commands to be applied to circuit 63 depending on the desired operating mode are summarized below (x indicates that the state of the command is indifferent for the function considered): C3 C1 C2 C4 simple copy with inversion x 1 1 x simple copy without inversion x 1 0 x coding format conversion with inversion: 1 ^st step 1 0 1 0 2 ^nd step 1 0 1 1 coding format conversion without inversion: 1 ^st step 1 0 0 0 2 ^nd step 1 0 0 1 filling 0 0 x x

Note that the "encoding format conversion" function allows the microprocessor to store data in the buffer memory in a format of 1 bit per pixel to save space. For example it can be typefaces or icons whose points all have the same gray level. To be displayed on the screen, such data must be copied into the screen memory with a 2-bit format per pixel.

For example, the microprocessor can store in the buffer memory a series of clock dials corresponding to different positions of the second hand. A screen animation can then consist of successively displaying every second a series dial to give the impression that the needle is moving. In this case, it is clearly advantageous to store the series of dials in compressed form in the buffer memory. For the display, the controller must therefore read the corresponding icons (coded on 1 bit per pixel) in the buffer memory, decompress them, and write the data results (coded on 2 bits per pixel) in the screen memory.

The invention is not limited to the embodiment which has just been described by way of example.

In particular, the embodiment described does not allow the four to be dissociated screen points whose code is stored in the same location in the RAM memory. But in another embodiment it would be possible to do so, at the cost of complexity increased entertainment circuit.

In addition, other operating modes or operating modes different can be provided for the processing circuit 63.

Claims (10)

Electronic equipment comprising a microprocessor (4), a liquid crystal screen (2) and a screen controller (3) provided with a memory (34), characterized in that: said microprocessor comprises means for transmitting commands to said screen controller, said commands indicating an operation (C1, C2, C3, C4) to be performed on data (L, H) stored in a source location (S) of said memory , and said screen controller includes processing means (50) for performing said operation. Equipment according to claim 1, characterized in that said processing means have means for moving data (61, 62, 63) to a location destination (D) of said memory, said destination location being indicated in said ordered. Equipment according to claim 1, characterized in that said memory (34) has a screen area (34) for storing the data to be displayed and a buffer area (52) for storing intermediate data or specific data. Equipment according to claim 1, characterized in that said processing means include means (84, 86, 90, 92) for converting the format of the data read in the source location. Equipment according to claim 1, characterized in that said processing means include means (94, 96) for video inversion of the data read in said location source. Screen controller (3) having a memory (34) for storing data at display on a liquid crystal screen (2), characterized in that it comprises means for processing (50) for executing commands received from an external processor, said processor commands indicating an operation (C1, C2, C3, C4) to be performed on stored data in a source location (S) of said memory. Screen controller according to claim 6, characterized in that said means for processing comprise means (61, 62, 63) for moving data to a destination location (D) of said memory, said destination location being indicated in said order. Screen controller according to claim 6, characterized in that said memory has a screen area (34) for storing the data to be displayed and a buffer area (52) for storing intermediate data or specific data. Screen controller according to claim 1, characterized in that said means for processing include means (84, 86, 90, 92) for converting data format read in the source location. Screen controller according to claim 7, characterized in that said means for processing comprise means (94, 96) for video inversion of the data read in said source location.

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