JPH11119744A - Controller for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller for expressing sure gradation in a liquid crystal display device in which gradation is expressed by frame control. SOLUTION: This controller is for a liquid crystal display device, in which gradation is expressed by frame control, and the controller is provided with a circuit 1 for conserving display data from a host computer, an expansion circuit 6 for analyzing the display data and developing it, a circuit 5 for conserving developed data, a control timing generating circuit 4 for taking timing for development from the expansion circuit 6 and timing for display, a frame counter 3 for recognizing a present frame, and a transmission circuit 7 for sending the developed data to the liquid crystal display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a liquid crystal display device used in a small information device such as a personal computer, a word processor, an electronic organizer, and a portable information device.

[0002]

2. Description of the Related Art A liquid crystal display (hereinafter abbreviated as LCD) is
Normally white is a display system in which the pixels lit on the background are black. "1" for display data
Will be displayed in black. When "0" is written in the display data, white is displayed. The number of pixels of the LCD is 32
If the number of pixels is 0 and the number of vertical pixels is 240, the total number of pixels is 76,800.
One frame means that all pixels are scanned once. Normally, all pixels are sequentially rewritten 60 to 120 times per second.

[0003] Human vision loses visual response when scanned at frequencies faster than 30 Hz. Therefore, if the display is rewritten at a fast frequency even if the display changes from black to white, the gray level is changed by using the afterimage effect that even if the display changes to white, it looks like there is black before the change. Can be expressed.

Therefore, when several frames are combined and the display is changed to black or white for each frame, the number of frames is increased by one.
Can be expressed. Specifically, a gradation expression method by the three-frame method will be described with reference to FIG. By controlling three frames collectively, four gradations can be expressed.
The data of four gradations is usually represented by two bits in a binary system, and there are four types of data, 11B, 10B, 01B, and 00B.

[0005] When data is 11B, the black appears dark and becomes black by drawing black in the first, second and third frames out of three frames. When the data is 10B, black is drawn in the first and second frames of the three frames, and white is drawn in the third frame, so that black appears light and gray. The operation when the data is 01B is to draw black in the first frame out of three frames,
Since white is drawn in the second and third frames, black looks thinner and becomes thinner. The operation when the data is 00B is white because the first, second, and third frames draw white.

[0006] The display flow of the LCD will be described with reference to FIG. In order to display the data on the LCD, display data is sent from the host computer 20 to the display data storage circuit 1 of the control device 30 of the LCD. The control device of the LCD creates display timing required by the LCD 50, and displays display data in accordance with the timing.
By sending it to 0, display is performed on the LCD 50.

[0007] Referring to FIG.
A description will be given using a three-frame method for expressing gradation. LC
D control device 30 is a display data storage circuit 1
, An analysis / transmission circuit 2, a frame counter 3, and a control timing generation circuit 4. The control timing generation circuit 4 generates a frame signal, a latch signal, and a clock signal to control the LCD.

The frame signal is a synchronizing signal once for one screen. The latch signal is a synchronization signal once per line. The clock signal is a synchronization signal for receiving data. The frame counter 3 counts each time a frame signal is input, and outputs “1”, “2”, “3”, “1”,
"2" and "3" are repeatedly generated.

The analysis / transmission circuit 2 takes out data from the display data storage circuit 1 and outputs data 11B, 10B, 01B, 0B.
The analysis of 0B is performed. If the data is 11B, "1" data is sent out in synchronization with the clock signal generated by the control timing generation circuit 4 regardless of the value of the frame counter 3.

If the data is 10B, the value of the frame counter 3 is checked, and if it is "1" or "2", the data of "1" is sent out in synchronization with the clock signal generated by the control timing generation circuit 4. . Frame counter 3
If the value is "3", data "0" is sent out in synchronization with the clock signal generated by the control timing generation circuit 4.

If the data is 01B, the value of the frame counter 3 is checked, and if it is "1", the data of "1" is sent out in synchronization with the clock signal generated by the control timing generation circuit 4. Looking at the value of the frame counter 3, if it is “2” or “3”, “0” is synchronized with the clock signal generated by the control timing generation circuit 4.
Send out the data. If the data is 00B, data of "0" is sent out in synchronization with the clock signal generated by the control timing generation circuit 4 regardless of the value of the frame counter 3. As described above, in the conventional structure, display is performed by looking only at the current frame counter value and the current display data value regardless of the previous and next frames.

[0012]

In order to display a moving picture of about 30 frames per second, the display data is rewritten 30 times per second. When gradation is displayed by the three-frame method, if the frame frequency of the LCD is not three times the rewriting frequency of the data, a phenomenon occurs in which the display data is always updated halfway before completing three frames.

In this case, the gradation expression is not completely established, and the display becomes incomplete. This will be specifically described with reference to the drawings showing the conventional technique of FIG. FIG. 5 shows a case where the frame frequency of the LCD is 60 Hz and the display data is rewritten at 30 Hz.

(A) Assuming that the display data to be displayed at the time of 0 second is 11B, the data is set to "1" in the first, second and third frames. Then, since the frame counter value is “1”, the data value 1 is output.

(A) If the display data to be displayed at the time of 1/60 second is 11B, the data is set to "1" in the first, second and third frames. Then, looking at the frame counter value, it is "2", so the data value is "1".
Is output.

(C) If the display data to be displayed at the time of 2/60 seconds is 00B, the data is set to "0" in the first, second and third frames. Then, looking at the frame counter value, it is "3", so the data value is "0".
Is output. At 0 seconds, “1” was displayed in the first frame, “1” in the second frame, and “1” in the third frame, but “0” is displayed in the third frame. Then, the gradation data is not completed. If the display is performed at such timing, the display will always be misaligned.

This occurs because the host computer 20 rewrites data in the display data storage circuit 1 in the control device 30 of the liquid crystal display device asynchronously with the frame frequency. This is because the host computer 20 operates with the first priority and the host computer 2
It is inevitable to avoid waiting for 0 and not playing.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a control device for a liquid crystal display device for expressing a certain gradation in a liquid crystal display device for expressing a gradation by frame control. It is to provide.

[0019]

In order to achieve the above object, a control device for a liquid crystal display device according to the present invention employs the following configuration.

According to the present invention, there is provided a control device of a liquid crystal display device for expressing gradation by frame control, a display data storage circuit for storing display data from a host computer, and a development for analyzing the display data and developing the data. A circuit, a development data storage circuit for storing the developed data, a control timing generation circuit that takes the development timing and display timing of the development circuit, a frame counter for recognizing the current frame, and a liquid crystal display for the developed data. It has a transmitting circuit for sending out to a display device.

(Function) The present invention provides a one-frame, two-dimensional image for gradation expression by providing a developed data storage circuit.
All the frame data of a frame and three frames can be stored, and the gradation data can be displayed without change in the gradation data.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments for implementing a control device for a liquid crystal display device according to the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram illustrating a control device of a liquid crystal display device according to an embodiment of the present invention. The display means of the present invention will be described with reference to FIG. 1 using a three-frame method for expressing four gradations.

(Structure description: FIG. 1) The control device 40 of the liquid crystal display device comprises a display data storage circuit 1 and a development circuit 6.
, A frame counter 3, a control timing generation circuit 4, a developed data storage circuit 5, and a transmission circuit 7. The control timing generation circuit 4 includes an LCD
Create a frame signal, a latch signal, and a clock signal to control The frame signal is a synchronization signal once for one screen. Latch signal is 1 per line
It is a synchronization signal of the time. The clock signal is a synchronization signal for receiving data.

The frame counter 3 counts every time a frame signal is input, and counts “1”, “2”, “3”,
"1", "2", and "3" are repeatedly generated. When a frame signal comes from the control timing generation circuit 4, the expansion circuit 2 looks at the frame counter 3.

If the value of the frame counter is "1", the data is taken out from the display data storage circuit 1 and
The analysis of 1B, 10B, 01B, and 00B is performed. If the data is 11B, “1” is stored in the expanded data storage circuit 5 as the data for the first frame.

"1" is stored as data for the second frame. “1” is stored as the data for the third frame.
If the data is 10B, the expanded data storage circuit 5 stores the first
“1” is stored as frame data. “1” is stored as data for the second frame.

"0" is stored as data for the third frame. If the data is 01B, the expanded data storage circuit 5
Is stored as data for the first frame. Second
“0” is stored as frame data. “0” is stored as the data for the third frame. If the data is 00B, “0” is stored in the expanded data storage circuit 5 as the data for the first frame. “0” is stored as the data for the second frame. "0" as data for the third frame
Save.

When the value of the frame counter is "2" or "3"
If so, do nothing. The transmission circuit 7 reads data from the expanded data storage circuit 5 in synchronization with the clock signal generated by the control timing
Send to CD.

By generating data for three frames for displaying the gradation at a time and storing the data in the expanded data storage circuit 5, the three frames can be displayed stably, and the gradation of good quality can be obtained. The display will be performed.

(Explanation of Operation: FIG. 5) FIG. 5 is a view showing that display data is different even if the original data is the same in the present invention. FIG. 5 shows that the frame frequency of the LCD is 60 Hz,
The case where the display data is rewritten at 30 Hz is described.

(A) When the time is 0 seconds, the data of the display data storage circuit is 11B and the frame counter value is "1".
The data value is stored as "1" for all three frames. The transmission circuit 7 transmits the data value “1” of the first frame to the LCD in synchronization with the clock. In the conventional example, since the data of the display data storage circuit is 11B, the data is set to "1" in the first, second and third frames. And the transmission circuit 7
Is "1" when looking at the frame counter value, so the data value "1" of the first frame is transmitted to the LCD in synchronization with the clock.

(A) When the time is 1/60 seconds, regardless of the data in the display data storage circuit 1, in the present invention, the data value "already stored in the expanded data storage circuit 5 as the data of the second frame""1" is transmitted to the LCD in synchronization with the clock. In the conventional example, since the data of the display data storage circuit is 11B, the data is set to "1" in the first, second and third frames. Then, the transmission circuit 7 transmits the data value "1" of the second frame to the LCD in synchronization with the clock since the frame counter value is "2" because it is "2".

(C) When the time is 2/60 seconds, regardless of the data in the display data storage circuit 1, in the present invention, the data value ""1" is transmitted to the LCD in synchronization with the clock. In the conventional example, since the data of the display data storage circuit is 00B, the data is set to “0” in the first, second and third frames. Then, the transmission circuit 7 transmits the data value “0” of the third frame to the LCD in synchronization with the clock since the frame counter value is “3” because it is “3”.

(D) Since the data of the display data storage circuit is 00B and the frame counter value is "1" at the time of 3/60 seconds, the expanded data storage circuit 1 stores the data in the first, second and third frames in the present invention. Save the value as “0”. The transmission circuit 7 transmits the data value “0” of the first frame to the LCD in synchronization with the clock. In the conventional example, since the data of the display data storage circuit is 00B, the data is set to "1" in the first, second and third frames. Then, since the transmission circuit 7 sees the frame counter value as “1”, the data value “0” of the first frame is synchronized with the clock to
Send to D.

(E) When the time is 4/60 seconds, regardless of the data in the display data storage circuit 1, the data value "0" already stored as the data of the second frame in the expanded data storage circuit 5 is clocked. Is transmitted to the LCD in synchronization with. In the conventional example, since the data of the display data storage circuit is 10B, the data is set to 1 for both the first and second frames, and the data is set to "0" for the third frame. Then, since the transmission circuit 7 sees the frame counter value as “2”, the data value “1” of the second frame is synchronized with the clock to
Send to D.

(F) When the time is 5/60 seconds, regardless of the data in the display data storage circuit 1, the data value "0" already stored as the data of the third frame in the expanded data storage circuit 5 is clocked. Is transmitted to the LCD in synchronization with. In the conventional example, since the data of the display data storage circuit is 10B,
The data is set to "1" for both the first and second frames, and the data is set to "0" for the third frame. Then, since the transmission circuit 7 sees the frame counter value as “3”, the data value “0” of the third frame is synchronized with the clock to
Send to D. It can be seen that the difference between the present invention and the conventional example appears at a time of 2/60 seconds and a time of 4/60 seconds.

(Structure description: FIG. 6) Next, a control device of a liquid crystal display device in a different embodiment will be described.
The control device 40 includes an integrated storage circuit 8 and a development circuit 6
, A frame counter 3, a control timing generation circuit 4, and a transmission circuit 7. Integrated storage circuit 8
Has an area for storing the display data including the gradation data from the host computer 20 and an area for storing the data which develops the gradation data and is purely sent to the display device.

By integrating the display data storage circuit 1 and the expanded data storage circuit 5 into one integrated storage circuit 8, the circuit can be simplified and space can be saved.

(Structure description: FIG. 7) Next, a control device of a liquid crystal display device according to a different embodiment will be described.
In FIG. 7, the expanded data storage circuit 5 is divided for each address. The separated addresses are numerical values determined by the number of pixels of the display device.

When the number of pixels of the display device is 320 horizontally and 240 vertically, the following settings are made. The data area 10 for the first frame has addresses 0000H to 257FH. The data area 11 for the second frame ranges from 3000H to 557FH. Third frame data area 12
Is from 6000H to 857FH. The area is divided for each frame, and the data is successively arranged from the upper left pixel data to the right and sequentially to the next row from 0000H. As a result, the transmission circuit 7 can continuously read data, so that the data reading speed can be increased. Also, the start address of each frame is set to 0 in order to simplify address decoding.
00H.

[0041]

As is apparent from the above description, the control device for a liquid crystal display device of the present invention has a development circuit and a development data storage circuit, thereby greatly improving the quality of gradation display. The control device of the device can be supplied to a small information device such as a personal computer, a word processor, an electronic organizer, and a portable information device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a control device of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an entire liquid crystal display system according to an embodiment of the present invention and a conventional technique.

FIG. 3 is a block diagram illustrating a control device of a liquid crystal display device according to the related art.

FIG. 4 is a diagram illustrating a gradation expression method of a liquid crystal display device.

FIG. 5 is a diagram showing a difference between display data according to the embodiment of the present invention and conventional technology.

FIG. 6 is a block diagram showing an integrated storage circuit of the control device of the liquid crystal display device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an internal division state of the expanded data storage circuit according to the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 display data storage circuit 2 data analysis / transmission circuit 3 frame counter 4 control timing generation circuit 5 expanded data storage circuit 6 expansion circuit 7 transmission circuit 8 integrated storage circuit 9 data area for first frame 10 data area for second frame 11 Data area for 3 frames 20 Host computer 30 Control device for liquid crystal display device 40 Control device for liquid crystal display device 50 Liquid crystal display device

Claims (3)

[Claims] 1. A control device of a liquid crystal display device for expressing gradation by frame control, comprising: a display data storage circuit for storing display data from a host computer; and a display data storage circuit for analyzing the display data and expanding the data. A decompression circuit, a decompression data storage circuit for storing the decompressed data, a control timing generation circuit for taking the decompression timing and display timing of the decompression circuit, a frame counter for recognizing the current frame, and a decompression data. A control device for a liquid crystal display device, comprising a transmission circuit for sending the signal to the liquid crystal display device. 2. A control device for a liquid crystal display device, wherein the display data storage circuit and the expansion data storage circuit according to claim 1 are constituted by one integrated storage circuit. 3. The expanded data storage circuit according to claim 1,
A control device for a liquid crystal display device, wherein areas are separated for each frame, such as a first frame data area, a second frame data area, and a third frame data area.