EP0957420B1 - Circuit de verrouillage - Google Patents

Circuit de verrouillage Download PDF

Info

Publication number
EP0957420B1
EP0957420B1 EP99109644A EP99109644A EP0957420B1 EP 0957420 B1 EP0957420 B1 EP 0957420B1 EP 99109644 A EP99109644 A EP 99109644A EP 99109644 A EP99109644 A EP 99109644A EP 0957420 B1 EP0957420 B1 EP 0957420B1
Authority
EP
European Patent Office
Prior art keywords
transistor
clamping
voltage
diode
clamping circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99109644A
Other languages
German (de)
English (en)
Other versions
EP0957420A3 (fr
EP0957420A2 (fr
Inventor
Martin Feldtkeller
Harald Koffler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0957420A2 publication Critical patent/EP0957420A2/fr
Publication of EP0957420A3 publication Critical patent/EP0957420A3/fr
Application granted granted Critical
Publication of EP0957420B1 publication Critical patent/EP0957420B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/227—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology

Definitions

  • the invention relates to a clamping circuit for generating a predetermined minimum voltage with cross-coupled first and second transistors according to the preamble of claim 1, which switches from normal operation to terminal operation, when the voltage of one supplied via an input path Signal drops below a predetermined clamping voltage.
  • Clamping circuits generally serve to level one to keep the signal present at a certain minimum value. Such clamping circuits are of great importance found the application of integrated circuits. A sinking of input signals in the range of a diode voltage below the ground potential and below that would namely cause that over in any integrated circuit existing parasitic device currents flow to neighboring ones Components or even the entire function of the Disrupt circuit. This danger is special, for example great if in electronic circuitry with multiple supply voltages and ground connections Error in the form of an open ground connection. Especially in safety-critical applications (for example in electronic systems in automotive electronics) It must be ensured that the error is not circuit parts directly affected are not influenced.
  • the circuit shown in FIG. 5a with four npn transistors T1, T2, T5, T6 and a current source I bias is known, for example.
  • the first and second transistors T1 and T2, which each have a very steep output characteristic, are cross-connected.
  • the emitter of the first transistor T1 (output transistor) is connected to an input path Vp. the one to be monitored Input signal is present. With such a circuit a good protective effect can be achieved in clamping operation, the desired clamping voltage being observed very precisely becomes.
  • this known circuit has the disadvantage that not for operation with high input voltages (for Example 40V or more) is suitable. This is because the first transistor T1, which is an NPN transistor acts due to its relatively low emitter base breakdown voltage only little strength against has such positive input voltages.
  • DE 25 49 575 is a circuit arrangement with cross-coupled Transistor described for connection to a special current or voltage source is provided. This generates one that is independent of the current or voltage source Signal.
  • the invention has for its object a clamping circuit of the type mentioned at the beginning to create a high dielectric strength with exact adherence to the clamping voltage and at the same time has a low current consumption in normal operation.
  • This solution combines two main advantages. As a result of that in clamp operation the current over the low-resistance channel and does not flow through the reverse diode RD of the transistor on the one hand, the protective function of the clamping circuit is not disturbed. On the other hand, the third transistor protects in normal operation M3 the first transistor T1 before too high voltages of the input signal, so that the desired dielectric strength the clamping circuit can be achieved.
  • the third transistor M3 is preferably a D-MOS field effect transistor, the gate connection of which is connected to a supply voltage V DD for switching on the field effect transistor.
  • a fourth D-MOS field effect transistor M4 is provided, the one in the emitter of a fifth, through a third diode D3 connected to the supply voltage transistor T5 is, the gate terminal of the third transistor M3 connected to the collector of the fifth transistor T5 is.
  • all transistors and the third diode can be used be replaced by field effect transistors.
  • the clamp circuit is particularly suitable for use in connection provided with integrated circuits, the Clamp voltage in this case is 0 volts.
  • the clamp circuit is also particularly in the BICDMOS (Bipolar, C and D-MOS) technology realizable.
  • Figure 1 shows a first embodiment of the invention, which has a third transistor M3 in the form of a self-blocking n-channel insulating layer field-effect transistor (D-MOS-FET), which is connected in the input path Vp of the clamping circuit, and the gate of which with a positive supply voltage V DD is connected, which is sufficient to switch it on completely (for example 5V).
  • D-MOS-FET self-blocking n-channel insulating layer field-effect transistor
  • ZD Zener diode ZD between the emitter of the first transistor T1 and ground.
  • the Zener diode ZD prevents an impermissible charging of the emitter of the first transistor T1 through the blocked through the field effect transistor M3 flowing reverse current.
  • the input voltage applied to the input path Vp drops to ground potential, the field effect transistor M3 goes in the reverse conducting state, and the circuit arrives in the clamp mode, in which the input signal over the first and second transistor T1, T2 connected to ground and thus preventing a further drop in the input voltage becomes.
  • the current flows through the low-impedance Channel of the field effect transistor M3 and not via the reverse diode RD, so that the clamping voltage is not as in the beginning is distorted with reference to the circuit explained in FIG. 5b, but remains unaffected. Consequently, the protective function the clamping circuit is not affected.
  • Figure 2 shows a second embodiment of the invention, the compared to the first embodiment, a fourth transistor in the form of a D-MOS field effect transistor M4 and a third Has diode D3.
  • the fourth transistor M4 is in the Emitter of the fifth transistor T5 switched while on the third diode D3 in the collector circuit of the fifth transistor T5 is located.
  • the influence of the on-resistance can of the third transistor M3 (field effect transistor) partially or fully compensated.
  • the fourth transistor M4 must face one the third transistor M3 smaller or the same on resistance exhibit.
  • This mating property can in particular can be produced in that the two field effect transistors M3 and M4 operated under the same conditions become.
  • This is switched into the collector circuit third diode D3, by an inverse operation of the fourth transistor M4 and in that the gate terminal of the third transistor M3 between the third Diode D3 and the collector of the fifth transistor T5.
  • This second embodiment also has the advantage that the input voltage present at the input path Vp is more precisely limited than in the first embodiment according to FIG Figure 1.
  • Figure 3 shows a third embodiment of the invention. This differs from the second shown in Figure 2 Embodiment in that the transistors T1, T2, T5 and T6 and the third diode D3 each through n-channel insulating layer field-effect transistors (MOS) M1, M2, M5, M6 or M7 are replaced.
  • MOS n-channel insulating layer field-effect transistors
  • Figure 4 finally shows output characteristics 1, 2 and 3 of the first, second and third embodiment, respectively vertical axis the output voltage and on the horizontal Axis of the output current is plotted.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Claims (6)

  1. Circuit de verrouillage pour obtenir une tension minimale prédéfinie au moyen d'un premier et d'un second transistor (T1, T2) connectés en croix, ce circuit en fonctionnement normal passant en fonctionnement de verrouillage quand la tension d'un signal amené par un chemin d'entrée (Vp) tombe en dessous d'une tension de verrouillage prédéfinie,
    caractérisé en ce que
    un troisième transistor (M3) est monté sur le chemin d'entrée (Vp) de manière à être en état conducteur vers l'arrière quand le circuit est en fonctionnement de verrouillage, et en état de blocage vers l'avant quand le circuit est en fonctionnement normal.
  2. Circuit de verrouillage selon la revendication 1,
    caractérisé en ce que
    le troisième transistor est un transistor (M3) à effet de champ D-MOS dont le raccord de grille est relié à une tension d'alimentation (VDD) pour raccorder le transistor à effet de champ.
  3. Circuit de verrouillage selon la revendication 2,
    caractérisé en ce que
    il est prévu une diode Zener (ZD) sur l'émetteur du premier transistor (T1) pour empêcher une charge inadmissible de cet émetteur par le courant d'arrêt passant à travers le troisième transistor bloqué (M3).
  4. Circuit de verrouillage selon la revendication 2 ou 3,
    caractérisé en ce que
    il est prévu un quatrième transistor (M4) à effet de champ D-MOS qui, pour compenser au moins en partie la résistance de mise en action du troisième transistor (M3) à effet de champ D-MOS, est monté dans l'émetteur d'un cinquième transistor (T5) relié par une troisième diode (D3) à la tension d'alimentation (VDD), le raccord de grille du troisième transistor (M3) étant relié au collecteur du cinquième transistor (T5).
  5. Circuit de verrouillage selon l'une des revendications précédentes,
    caractérisé en ce que
    les premier, deuxième, quatrième et cinquième transistors (T1, T2, T4, T5) ainsi que la troisième diode (D3) sont remplacés respectivement par des transistors MOS à effet de champ (M1, M2, M4, M5, M7).
  6. Circuit de verrouillage selon l'une des revendications précédentes, en particulier pour utilisation en liaison avec des circuits intégrés,
    caractérisé en ce que
    la tension de verrouillage est de 0 volt.
EP99109644A 1998-05-15 1999-05-14 Circuit de verrouillage Expired - Lifetime EP0957420B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19821906 1998-05-15
DE19821906A DE19821906C1 (de) 1998-05-15 1998-05-15 Klemmschaltung

Publications (3)

Publication Number Publication Date
EP0957420A2 EP0957420A2 (fr) 1999-11-17
EP0957420A3 EP0957420A3 (fr) 2000-03-29
EP0957420B1 true EP0957420B1 (fr) 2003-04-16

Family

ID=7867934

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99109644A Expired - Lifetime EP0957420B1 (fr) 1998-05-15 1999-05-14 Circuit de verrouillage

Country Status (3)

Country Link
US (1) US6137278A (fr)
EP (1) EP0957420B1 (fr)
DE (2) DE19821906C1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7242240B2 (en) * 2005-05-05 2007-07-10 Agere Systems, Inc. Low noise bandgap circuit
US20090121770A1 (en) 2007-03-29 2009-05-14 Linear Technology Corporation Method for clamping a semiconductor region at or near ground
JP4553395B2 (ja) * 2007-06-15 2010-09-29 シャープ株式会社 オシロスコープおよびそれを用いた半導体評価装置
WO2011135094A1 (fr) * 2010-04-30 2011-11-03 Katholieke Universiteit Leuven Circuit d'écrêtage de tension et son utilisation
US20130027117A1 (en) * 2011-07-28 2013-01-31 Anadyne, Inc. Precision voltage clamp with very low temperature drift
CN109474246B (zh) * 2018-10-31 2022-06-28 西安微电子技术研究所 电压箝位保护结构及运算放大器输入级结构
CN111208401B (zh) * 2018-11-22 2023-01-31 宁波飞芯电子科技有限公司 一种钳位光电二极管的测试方法以及装置
CN112152189B (zh) * 2020-09-15 2023-01-31 广东省大湾区集成电路与系统应用研究院 一种钳位电路和电子设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3703711A (en) * 1971-01-04 1972-11-21 Honeywell Inf Systems Memory cell with voltage limiting at transistor control terminals
US3930172A (en) * 1974-11-06 1975-12-30 Nat Semiconductor Corp Input supply independent circuit
JPH0746506B2 (ja) * 1985-09-30 1995-05-17 株式会社東芝 半導体メモリ装置
GB2189954B (en) * 1986-04-30 1989-12-20 Plessey Co Plc Improvements relating to memory cell devices
US4926073A (en) * 1989-05-01 1990-05-15 Motorola Inc. Negative voltage clamp
JPH06104672A (ja) * 1992-09-22 1994-04-15 Mitsubishi Electric Corp クランプ回路
KR950005577B1 (ko) * 1992-12-30 1995-05-25 현대전자산업주식회사 비트 라인 부하 회로
FR2718259A1 (fr) * 1994-03-30 1995-10-06 Philips Composants Circuit régulateur fournissant une tension indépendante de l'alimentation et de la température.
US5519341A (en) * 1994-12-02 1996-05-21 Texas Instruments Incorporated Cross coupled quad comparator for current sensing independent of temperature
US5614850A (en) * 1994-12-09 1997-03-25 Texas Instruments Incorporated Current sensing circuit and method

Also Published As

Publication number Publication date
DE59905031D1 (de) 2003-05-22
DE19821906C1 (de) 2000-03-02
EP0957420A3 (fr) 2000-03-29
EP0957420A2 (fr) 1999-11-17
US6137278A (en) 2000-10-24

Similar Documents

Publication Publication Date Title
EP0496018B1 (fr) Circuit intégré servant à générer un signal de remise à zéro
EP0587938A1 (fr) Circuit tampon intégré
EP0591561B1 (fr) Circuit intégré pour générer un signal de remise à l'état initial
DE4334513C1 (de) CMOS-Schaltung mit erhöhter Spannungsfestigkeit
EP0957420B1 (fr) Circuit de verrouillage
DE3736380A1 (de) Schaltungsanordnung zur kontrolle der drain-source-spannung eines mos-transistors
DE2610177A1 (de) Fuehlerverstaerker mit drei moeglichen betriebszustaenden zum anschluss an datenvielfachleitungen
DE2518078B2 (de) Logische MOS-Schaltungsanordnung
DE3323446A1 (de) Eingangssignalpegelwandler fuer eine mos-digitalschaltung
DE102019207770A1 (de) Integrierter Halbleiterschaltkreis
DE3343700C2 (fr)
DE2925008A1 (de) Integrierte strom-treiberschaltung
EP0135075A1 (fr) Circuit inverseur à MOS
DE10053374C2 (de) Bipolarer Komparator
EP1099308B1 (fr) Circuit d'attaque
DE19838109B4 (de) Ansteuerschaltung für induktive Lasten
DE3110355A1 (de) "vorspannungsgenerator"
EP0748047A1 (fr) Circuit tampon intégré
EP1078460A1 (fr) Procede et dispositif pour commuter un transistor a effet de champ
DE4223274A1 (de) Treiberschaltung fuer induktive lasten
EP0676846B1 (fr) Commutateur réalisé avec transistor bipolaire comme premier élément de commutation
DE19719448A1 (de) Inverterschaltung
DE102021111003B4 (de) Dual-mode-versorgungsschaltung und verfahren
DE3615513A1 (de) Digital-analog-wandler fuer niedrige spannungswerte
DE10060842A1 (de) Stromspiegelschaltung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIC1 Information provided on ipc code assigned before grant

Free format text: 7G 05F 3/22 A, 7G 11C 5/14 B

17P Request for examination filed

Effective date: 20000503

AKX Designation fees paid

Free format text: DE FR GB IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20030416

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REF Corresponds to:

Ref document number: 59905031

Country of ref document: DE

Date of ref document: 20030522

Kind code of ref document: P

GBV Gb: ep patent (uk) treated as always having been void in accordance with gb section 77(7)/1977 [no translation filed]

Effective date: 20030416

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20040119

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 18

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20170523

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20170526

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20170718

Year of fee payment: 19

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 59905031

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20181201

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180514

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180531