Classifications

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Definitions

• This invention relates to an electronic package having a ground ring and a method for the manufacture of that ground ring. More particularly, an annular channel is mechanically milled into a metallic substrate such that the annular channel both circumscribes and abuts a cavity.
• Metallic substrates are widely used as components for packages that encase one or more integrated circuit devices, such as silicon based semiconductor chips.
• the metallic substrate is coated with a dielectric layer and a pattern of circuit traces are formed on the dielectric layer.
• the inner ends of these circuit traces define a die attach region that contain one or more semiconductor devices.
• the devices are electrically interconnected to the circuit traces such as by thin bonding wires .
• the substrate is an aluminum alloy coated with a dielectric anodic film.
• the substrate is formed from a copper alloy and coated with a layer of a dielectric polymer.
• portions of the dielectric layer are removed from the metallic substrate. Dielectric free regions can be formed by chemically etching the dielectric, or by masking the substrate prior to applying the dielectric. In a commonly owned U.S. Patent Application portions of the dielectric layer are removed by ablation with an exci er laser.
• the dielectric free regions are small, typically with a depth only slightly more than the thickness of the dielectric layer, on the order of 0.051 mm (0.002 inch) thick, and a minimal width, on the order of 0.25 mm (0.010 inch) .
• Mechanical abrasion has been thought to be impossible for providing the dielectric free regions .
• a mechanical tool having a diameter effective to provide the necessary limited width would be very fragile and subject to frequent fracture. The radius of the tip of the tool would be so large that dielectric free region would be sloped and unsuitable for wire bonding.
• an electrically conductive annular channel both circumscribes and abuts a centrally disposed cavity in a metallic substrate.
• this annular channel is formed at low cost by mechanical milling and has a generally planar base surface suitable for wire bonding.
• a component for an electronic package has a metallic substrate with first and second surfaces that are separated by first sidewalls.
• the first surface of the metallic substrate has a centrally disposed cavity.
• This cavity has a base and second sidewalls.
• the depth of the base is designated D 1#
• An annular channel recessed into the metallic substrate to a depth, D 2 both circumscribes and abuts the second sidewalls.
• a dielectric coating overlies a peripheral portion of the first surface and terminates at the annular channel .
• a metallic substrate that has opposing first and second surfaces separated by first sidewalls.
• a dielectric layer overlies at least this first surface.
• a precursor annular channel is mechanically milled into the first surface.
• the precursor annular channel has a depth, D 2 , and an outer wall that is spaced from the first sidewalls by a length ' 1 .
• the annular channel further has an inner wall that is spaced from the sidewalls by a length L 2 .
• a cavity is then mechanically milled to be circumscribed by the outer wall. This cavity has a depth D x that is greater than D 2 .
• the cavity has second sidewalls that are spaced from the first sidewalls by a length L 3 that is greater than L 2 , but less than L ⁇ .
• a metallic substrate having opposing first and second surfaces separated by first sidewalls and a dielectric layer overlying at least the first surface.
• a cavity having a depth, D 2 is mechanically milled into a central portion of this first surface.
• This cavity has second sidewalls that are spaced from the first sidewalls by a length L 3 .
• An annular channel is then mechanically milled into the first surface. This channel both circumscribes and abuts the second sidewalls and has a depth O 1 that is less than D 2 .
• Figure 1 shows in cross-sectional representation a ball grid array electronic package in accordance with the invention.
• Figure 2 shows in cross-sectional representation a magnified view of an annular channel in accordance with the invention.
• Figure 3 shows a milling tool as utilized by the prior art .
• Figure 4 shows a milling tool as utilized in accordance with the method of the invention.
• Figure 5 shows in top planar view an annular channel formed in accordance with a method of the invention.
• Figure 6 shows in top planar view a cavity formed in abutting relationship with the annular channel formed in accordance with a method of the invention.
• Figure 7 shows in top planar view a mechanically milled cavity formed in accordance with another method of the invention.
• FIG. 1 illustrates in cross-sectional representation an electronic package 10 for encasing one or more semiconductor devices 12.
• One component of the electronic package 10 is a metallic substrate 14.
• This metallic substrate 14 has opposing first 16 and second 18, generally coplanar, surfaces that are separated by first sidewalls 20.
• a cavity 22 is disposed in a central portion of the first surface 16. This cavity has a base 24 and second sidewalls 26. The base 24 is generally coplanar with both the first surface 16 and the second surface 18.
• the cavity 22 has a depth, D 1( effective to provide a top surface 28 of the semiconductor device 12 at approximately the same height as the first surface 16. Typically, D 1 is in the range of from about 0.30 mm to about 0.97 mm (0.012 inch to about 0.038 inch) .
• annular channel 30 both circumscribes and abuts the second sidewalls 26. As best shown in Figure 2 , that is an enhanced view of the portion of the electronic package 10 identified by the broken circle of Figure 1, the annular channel 30 is recessed by a depth D 2 below the first surface 16. The depth of D 2 is less than the depth of D 1 .
• a dielectric coating 32 coats a peripheral portion of the first surface 16 and terminates adjacent to the annular channel 30.
• the dielectric coating 32 typically coats the first sidewalls 20, a peripheral portion of the first surface 16 and a substantial, if not all, of the second surface 18.
• the metallic substrate 14 is selected to be copper, aluminum or an alloy thereof.
• the dielectric coating 32 is typically a polymer such as an epoxy.
• the dielectric coating is an aluminum oxide such as an anodic film.
• the electronic package 10 further includes conductive circuit traces 34. These circuit traces have a first end 36 that terminates adjacent to the annular channel 30. The circuit traces 34 have an opposing second end 38 that terminates adjacent to the perimeter of the electronic package 10.
• the circuit traces 34 may be formed from any electrically conductive material such as a laminated copper foil, a vacuum deposited copper or other metal or a metallized paste bonded to the dielectric coating 32.
• a second dielectric coating 40 coats selected portions of the circuit traces 34, leaving the first ends 36 and a portion 42 of the second ends 38 exposed.
• a first electrical interconnect 44 contacts the circuit trace 34 through the exposed portion 42.
• This first electrical interconnect 44 may be any conductive bonding medium such as an electrically conductive epoxy or a low melting temperature solder.
• the first electrical interconnect may take the form of balls, columns or any desirable shape.
• a plurality of second electrical interconnects 46 such as thin diameter, on the order of 0.025 mm (0.001 inch) , gold, aluminum or copper wires, or thin copper foil as utilized in tape automated bonding electrically interconnects input/output pads on the first surface 28 of the semiconductor device 12 to the first ends 36 of circuit traces 34. At least one of the second electrical interconnects 46 electrically interconnects the input/output pads to the annular channel 30.
• the surface of the annular channel that is approximately coplanar with the first surface 16 and with the base 24 is as smooth as possible.
• D 2 is at most 0.18 mm (0.007 inch) .
• D 2 is from about 0.051 mm (0.002 inch) to about 0.13 mm (0.005 inch) .
• a cover 48 then encapsulates a semiconductor device 12 and first ends 36 of circuit traces 34.
• the cover may be a polymeric encapsulant or a discrete metal, polymer or ceramic component bonded to the second dielectric 40.
• the width W : of the annular channel 30 is at most 0.38 mm (0.015 inch) and preferably from about 0.18 mm to about 0.25 mm (0.007 inch to about 0.010 inch) .
• Figure 3 illustrates a tool 50 as known from the prior art capable of machining an annular channel 30 of the desired width.
• This tool may constitute a drill bit or end mill bit and has a nominal diameter of 0.25 mm (0.010 inch) .
• the long length of the tool relative to the diameter makes the tool 50 very fragile and prone to breakage.
• the tip radius 52 imparts a radius into a substantial portion of the annular channel 30 making wire bonding difficult or impossible.
• a superior approach that results in a smooth surface for wire bonding is to use the tool 54 illustrated in Figure 4.
• the tool 54 has a diameter from about 6 times to about 15 times greater than the desired diameter, Vt l r of the annular channel.
• the tool 54 has a diameter from about 8 times to about 12 times greater than the desired width of the annular channel. Because the diameter is large relative to the length of the tool 54, the tool 54 is robust and not subject to breakage. In addition, the large diameter facilitates a very sharp radius 56 at the tip of the tool 54.
• the metallic substrate 14 illustrated in Figure 5 has a first surface coated with first dielectric coating 32.
• a precursor annular channel 58 is mechanically milled into the fir ⁇ t surface of the metallic substrate 14 to a depth, D 2 , that at a minimum, exceeds the thickness of the first dielectric coating 32 to expose the underlying metallic material.
• the depth D 2 is from about 0.051 mm to about 0.13 mm (0.002 inch to about 0.005 inch) .
• An outer wall 60 of the precursor annular channel 58 is spaced from the first sidewalls 20 by a length L x .
• An inner wall 62 of the precursor annular channel 58 is spaced from the first sidewall 20 by a distance L 2 .
• a cavity 22 having a depth O x that is greater than the depth D 2 of the precursor annular channel is then formed in a central portion of the first surface of the metallic substrate 14.
• the cavity may be formed by any desired process such as mechanical milling or coining.
• the second sidewalls 26 are spaced from the first sidewalls 20 by a length L 3 that is greater than the length L 2 , but less than the length L x .
• L 3 is at most 0.015 inch less than L x and preferably from about 0.20 mm to about 0.30 mm (0.008 inch to about 0.012 inch) less than L x .
• the precursor annular channel is cut back from the inner wall to a point equivalent to the desired width of the annular channel 30. Since both the precursor annular channel 58 and the cavity 20 can be formed using a large diameter, sharp radius tool, the annular channel 30 has the desired narrow width and also a smooth surface satisfactory for wire bonding.
• the use of the large diameter milling tool in accordance with the invention produces chips less than 0.076 mm (0.003 inch) in both the X and the Y direction. Chips of this size are within the tolerances for any anticipated electronic package design.
• FIG. 7 An alternative method of manufacture is illustrated with reference to Figure 7.
• the cavity 22 spaced from the first sidewalls 20 by a desired length L 3 is initially formed in the metallic substrate 14 by any desired process and extends through the first dielectric coating 32 to the desired cavity depth Dj .
• the annular channel 30, illustrated in Figure 6 is mechanically milled to abut and circumscribe the second sidewalls 26 of the cavity 20.
• the large diameter, sharp radius tool is employed, penetrating the first surface to a depth Di that is less than the depth of the cavity 22. All of the tool, except for that portion necessary to form the annular channel 30 to a desired width, overlies the cavity 20 and does not contact the metallic substrate.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

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• 1996
  • 1996-11-18 KR KR1019980703735A patent/KR19990071466A/ko not_active Withdrawn
  • 1996-11-18 WO PCT/US1996/018479 patent/WO1997019470A1/en not_active Application Discontinuation
  • 1996-11-18 EP EP96941385A patent/EP0956589A1/en not_active Withdrawn
  • 1996-11-18 JP JP9519824A patent/JP2000500619A/ja active Pending
• 1997
  • 1997-02-20 TW TW086102000A patent/TW434870B/zh not_active IP Right Cessation

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