TW434870B - Ground ring for metal electronic package - Google Patents

Ground ring for metal electronic package Download PDF

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Publication number
TW434870B
TW434870B TW086102000A TW86102000A TW434870B TW 434870 B TW434870 B TW 434870B TW 086102000 A TW086102000 A TW 086102000A TW 86102000 A TW86102000 A TW 86102000A TW 434870 B TW434870 B TW 434870B
Authority
TW
Taiwan
Prior art keywords
annular channel
side wall
depth
groove
separated
Prior art date
Application number
TW086102000A
Other languages
English (en)
Chinese (zh)
Inventor
Paul R Hoffman
Markus K Liebhard
Original Assignee
Exactech In
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/749,259 external-priority patent/US5764484A/en
Application filed by Exactech In filed Critical Exactech In
Application granted granted Critical
Publication of TW434870B publication Critical patent/TW434870B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01ELECTRIC ELEMENTS
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321Disposition
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    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
TW086102000A 1995-11-20 1997-02-20 Ground ring for metal electronic package TW434870B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US737495P 1995-11-20 1995-11-20
US08/749,259 US5764484A (en) 1996-11-15 1996-11-15 Ground ring for a metal electronic package

Publications (1)

Publication Number Publication Date
TW434870B true TW434870B (en) 2001-05-16

Family

ID=26676905

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086102000A TW434870B (en) 1995-11-20 1997-02-20 Ground ring for metal electronic package

Country Status (5)

Country Link
EP (1) EP0956589A1 (enrdf_load_stackoverflow)
JP (1) JP2000500619A (enrdf_load_stackoverflow)
KR (1) KR19990071466A (enrdf_load_stackoverflow)
TW (1) TW434870B (enrdf_load_stackoverflow)
WO (1) WO1997019470A1 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6716363B2 (ja) * 2016-06-28 2020-07-01 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及びその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3819431A (en) * 1971-10-05 1974-06-25 Kulite Semiconductor Products Method of making transducers employing integral protective coatings and supports
JPS58169943A (ja) * 1982-03-29 1983-10-06 Fujitsu Ltd 半導体装置
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US5023398A (en) * 1988-10-05 1991-06-11 Olin Corporation Aluminum alloy semiconductor packages
JP2598129B2 (ja) * 1989-05-18 1997-04-09 三菱電機株式会社 半導体装置
JPH0423441A (ja) * 1990-05-18 1992-01-27 Fujitsu Ltd セラミックパッケージ半導体装置およびその製造方法
US6262477B1 (en) * 1993-03-19 2001-07-17 Advanced Interconnect Technologies Ball grid array electronic package
US5353195A (en) * 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
EP0645953B1 (de) * 1993-09-29 1997-08-06 Siemens NV Verfahren zur Herstellung einer zwei- oder mehrlagigen Verdrahtung und danach hergestellte zwei- oder mehrlagige Verdrahtung
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity

Also Published As

Publication number Publication date
WO1997019470A1 (en) 1997-05-29
JP2000500619A (ja) 2000-01-18
KR19990071466A (ko) 1999-09-27
EP0956589A4 (enrdf_load_stackoverflow) 1999-11-17
EP0956589A1 (en) 1999-11-17

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