Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42324—Gate electrodes for transistors with a floating gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
  • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• the invention relates to floating gate memory cells with improved reliability and a method for improving the manufacture of floating gate memory cells. More specifically, the invention relates to salicide floating gate memory cells with reduced charge leakage.
• Control gate 27 is formed atop a gate oxide layer 20 over a p-type silicon substrate 13. Lightly doped n- source region 15b and lightly doped n- drain region 17b are self-aligned on either side of control gate 27. Oxide sidewall spacers 23 and 25 are then formed on both sides of control gate 27.
• Oxide sidewall spacers 23 and 25 serve two functions. First, they serve to self-align the formation of heavily doped n+ source region 15a and heavily doped n+ drain region 17a at a predetermined distance from control gate 27. This predetermined distance is defined by the desired length of the lightly doped n- regions 15b and 17b. The lengths of lightly doped n- regions 15b and 17b are selected such that short-channel effects are mitigated and transistor action of device 11 is enhanced while simultaneously raising the operating voltage of device 11. Secondly, oxide sidewall spacers 23 and 25 serve to define the formation of self-aligned silicide 29 on heavily doped n+ regions 15a and 17a and on control gate 27. Oxide sidewall spacers 23 and 25 also prevent silicide 29b on heavily doped n+ regions 15a and 17a from making contact with control gate 27 or with silicide 29a on control gate 27.
• source region 15 and drain region 17 are formed, a metal film used for the formation of silicide is deposited over the entire surface of transistor 11.
• the metal may be a refractory metal such as titanium or a group-VIII metal.
• the wafer in which transistor 11 is located is heated.
• the metal film reacts to the heat by annealing with any exposed silicon and polysilicon to form silicide, but the metal film will not react with exposed oxide. Therefore, a layer of silicide 29b is formed over silicon regions 15a and 17a, and another layer of silicide 29a is formed over polysilicon control gate 27.
• silicide is not formed over oxide sidewall spacers 23 and 25 or over the lightly doped n- source 15b and drain 17b regions, which are protected by oxide sidewall spacers 23 and 25. Any unreacted metal is then selectively removed by using an etchant that will not attack silicide 29, silicon substrate 13 or oxide sidewall spacers 23 and 25.
• Titanium silicide has some drawbacks.
• titanium metal may inhibit sidewall spacers 23 and 25 from properly isolating silicide 29a on control gate 27 from silicide 29b on source region 15a and drain region 17a.
• silicon from source 15, drain 17 and control gate 27 of an MOS transistor will diffuse into a titanium metal film covering sidewall spacers 23 and 25.
• the silicon diffused into the titanium metal film covering sidewall spacers 23 and 25 will form a lateral silicide layer 28 over sidewall spacers 23 and 25.
• Lateral silicide 28 may grow to electrically short control gate 27 with source region 15a or drain region 17a. This problem is termed bridging.
• the lightly doped n- regions 15b and 17b of the source and drain, respectively need to be reduced in length for proper scaling and optimum performance.
• the lengths of the lightly doped n- regions 15b and 17b are defined by the size of sidewall spacers 23 and 25, respectively, and the minimum size of sidewall spacers 23 and 25 is limited by the need to prevent bridging.
• the minimum size of sidewall spacer 23 and 25 needed to prevent bridging can be much larger than the desired reduced length of the lightly doped region 15b and 17b needed for proper scaling. This can result in transistor 11 having oversized lightly doped -n regions 15b and 17b and less than optimum performance.
• U.S. Pat. 5,208,472 to Su et al . teaches a method of addressing this problem.
• Su et al. teach forming oxide sidewall spacers 23 and 25 of transistor 11 in two process steps.
• a first process step a first part, 23a and 25b, of the oxide spacers is formed to a size determined by the optimal size of lightly doped regions 15b and 17b, respectively.
• a second process step a second part, 23b and 25b, of the oxide spacers is formed over the first parts 23a and 25a, respectively, to extend the final size of the combined oxide spacers 23 and 25 to an appropriate size required for preventing bridging.
• U.S. Pat. 5,322,809 to Moslehi teaches a different problem afflicting the use of salicide in the micro-miniaturization of conventional MOS transistors.
• Moslehi explains that as a typical MOS transistor is miniaturized, the source and drain regions of the transistor need to be made more shallow to maintain proper size scaling and performance.
• MOS transistors having channel lengths less than 0.8 ⁇ m require source and drain regions having a depth smaller than 0.25 ⁇ m, as explained in Silicon Processing for the VLSI Era, vol. 2 by S. Wolf, page 154.
• Moslehi who expounds upon some of the difficulties of forming silicide on shallow source/drain junctions.
• Moslehi states that because the source and drain regions are shallow, the formation of silicide over the source and drain may consume so much silicon in the source and drain regions as to be detrimental to the transistor.
• Moslehi also assserts that one cannot simply reduce the depth of the formed silicide with the reduction in the depth of the source and drain regions because the control gate still requires a large amount of silicide formation to reduce its ohmic resistance.
• Moslehi teaches a method of slowing down the formation of silicide over the source and drain regions without affecting the rate of silicide formation over the control gate. It is thereby still possible to form silicide on the source, drain and control gate simultaneously in a salicide process.
• Moslehi proposes that a thin silicide boundary, preferably a thin nitride layer, be laid over the source and drain regions after the formation of the sidewall spacers.
• the silicide boundary is not laid over the control gate.
• the silicide boundary is thin enough to slow the formation of silicide over the source and drain regions, but not thick enough to completely inhibit it.
• an oxide mask is placed over the control gate prior to formation of the sidewall spacers and therefore prior to the laying of the silicide boundary over the source and drain regions. After the silicide boundary has been formed on the source and drain regions, the oxide mask covering the gate is removed and the entire device is then covered with a refractory metal. Moslehi recommends making the sidewall spacers of the same material as the silicide boundary.
• a floating gate memory cell 31 typically has a control gate 37 stacked on top of a floating gate 35 with interpoly oxide 30 in between, and an additional gate oxide 31 under floating gate 35.
• Control gate 37 and interpoly oxide 30 typically have similar thicknesses as the control gate 27 and oxide layer 20 of the typical MOS transistor 11 of Figs. 1-5.
• the dual gate structure of a floating gate memory cell 31 is much larger than gate structure 27 of the conventional MOS transistors 11 discussed above.
• floating gate memory cell 31 having oxide sidewall spacers 39 and 38 which are taller and wider than the sidewall spacers 23 and 25 of conventional single gate MOS transistors. Therefore, any lateral silicide growth 33 will generally not extend far enough to make contact and cause bridging between the silicide 36b on the source 32 or silicide 36b on the drain 34 and the silicide 36a on the control gate 37.
• floating gate memory cell 31 since a floating gate memory cell 31 needs to withstand voltages of 2 to 4 times the main power supply, Vcc, during various phases of operation, they cannot use shallow source and drain junctions nor can they be miniaturized to the extent of conventional MOS transistors, which are designed to withstand at most a Vcc of typically 3V to 5V. As a result, floating gate memory cell 31 does not require a lightly doped drain structure. Therefore, floating gate memory cell 31 does not have the contradicting requirements of large sidewall spacers to prevent bridging and small sidewall spacers for sizing of a lightly doped region, as discussed by Su et al. and Wang et al.
• floating gate memory cell 31 does not have shallow source and drain regions and is not subject to the problems afflicting the use of salicide in a conventional micro-miniaturized transistor having shallow source and drain regions, as discussed by Moslehi.
• the sidewall spacer size typically has to be a compromise for both, or optimized only for the floating gate cells or for the microminiaturized transistors. If microminiaturized transistors and floating gate memory cells are indeed constructed using common process steps and the spacer size is indeed optimized for microminiature transistors, then the spacers on the floating gate cells would be smaller than those shown in Fig. 6, but would still generally be larger than those on the microminiature transistors. Additionally, the floating gate memory cells would still not be subject to the problems afflicting the use of silicide in shallow source and drain regions since they would still need to withstand voltage stresses of 2 ⁇ to 4 times Vcc.
• silicide tends to reduce the sheet resistance of silicon and polysilicon electrodes, but some circuits require electrodes with high resist- ances.
• Such devices include, for example, ESD and latch- up protection circuitry, resistors and I/O circuitry.
• the conventional method of selectively growing silicide on some circuits of an IC and not on others is to first deposit an oxide layer over the entire IC after all transistors have been constructed, but before starting any salicide processes.
• a photoresist pattern covering those circuits which should not receive silicide is placed over the IC, and the oxide layer is etched off of all exposed regions which are not covered by the photoresist pattern. The photoresist pattern is then removed, leaving an oxide layer boundary over only those circuits which should not receive silicide. Removal of the oxide layer, however, can impact the integrity of the oxide spacers and introduce structural abnormalities into a floating gate memory cell, which have been identified by the inventors as leading to a reduction in a memory cell's expected life span.
• the memory cell is not designated to receive silicide, then it remains covered by the oxide layer during the. salicide process steps. After the salicide process steps, the oxide layer is removed. Thus, all devices require that they be covered by an oxide mask and all require that the oxide mask be later removed, either before or after the salicide process steps. Removal of the oxide layer can thin out areas of an oxide re-growth, or re-oxide growth, surrounding the floating gate of a memory cell. The re-oxide growth has previously been made to protect the polysilicon from damage during subsequent ion implantations and other process steps. It has been found, however, that the re-oxide growth can develop regions thin enough for charge to leak out of the floating gate of a memory cell even if it is still thick enough to protect the polysilicon from the subsequent process steps.
• the memory cell is designated to receive silicide and therefore has prior art oxide sidewall spacers covering the re-oxide growth, then it has been found that when the layer of oxide is etched off the floating gate memory cell in preparation for the salicide process steps, the memory cell's prior art oxide sidewall spacers can develop areas which are partially etched down to the re-oxide growth, which encases the floating gate. Thus, the re-oxide growth surrounding the floating gate can experience thinning regardless of whether it is covered by prior art oxide sidewall spacers, or not.
• a control gate and floating gate stack typically have a re-oxide growth covering the sides of the gates.
• the re-oxide growth encapsulates the floating gate and provides a protective coating to all polysilicon gates during subsequent ion implantations and other process steps.
• the re- oxide growth is thinned down below a certain point of about 100 A, it can provide a path for slow charge leakage out of the floating gate even though it is still thick enough to protect the polysilicon gates from damage during subsequent process steps.
• the non-volatile memory cell is of the electrically erasable type, then it will typically have a thin oxide tunnel region under the floating gate between the source and drain through which charge is moved into and out of the floating gate.
• the disturbances on the re-oxide growth at the side walls of the floating gate effectively form additional, uncontrollable charge tunnel regions. Consequently, the memory cell can experience charge loss. This will result in a floating gate memory cell of reduced performance and lower reliability.
• a non-volatile, floating gate memory cell is susceptible to this previously unrecognized charge leakage problem regardless of whether is receives silicide or not.
• a memory cell's re-oxide growth may experience severe thinning around its floating gate.
• a memory array is typically given a projected cycling and speed rating based on results of initial speed tests on its memory cells under stressed conditions.
• the invention proposes a method and structure for a floating gate memory cell in an IC with selective salicide construction which maintains the integrity of the re-oxide growth surrounding the floating gate regardless of whether the memory cell receives silicide or not.
• an oxide- protective cover on the sides of the floating gate and over its re-oxide growth.
• the oxide-protective cover has the property of being resistant to the etchant which is used to remove the oxide mask layer prior to salicide process steps.
• the oxide-protective cover forms a barrier between the oxide mask layer and the re-oxide growth.
• the oxide protective cover over the re- oxide growth will not be affected by the etchant and thereby maintain the integrity of the re-oxide growth underneath it.
• the protective cover is a nitride structure made thick enough to prevent all silicide from penetrating it and reaching the re-oxide growth on the side wall of the floating gate.
• the oxide-protective nitride cover may be structured into sidewall spacers for the floating gate memory cell instead of using prior art sidewall spacers made of oxide.
• a hydrogen fluoride etchant is used to remove the oxide mask off the memory cell.
• the hydrogen fluoride etchant is highly selective of nitride and will remove the oxide mask without much attacking the nitride sidewall spacers.
• a titanium layer, or some other oppropriate metal film, is laid over the memory cell followed by a heat annealing step.
• the process of the present invention also prevents a degradation in the width of the nitride sidewall spacers, thereby also protecting the integrity of the lightly doped regions of an LDD MOS switch transistor.
• Fig. 1 is a prior art salicide MOS transistor.
• Fig. 2 is a prior art salicide MOS transistor showing bridging of silicide from the control gate to the source and drain regions.
• Fig. 3 is a prior art salicide MOS transistor having large oxide spacers to prevent silicide bridging.
• Fig. 4 is a prior art salicide MOS transistor with oxide spacers formed in two steps.
• Fig. 5 is a prior art salicide MOS transistor with a titanium nitride boundary layer.
• Fig. 6 is a prior art salicide floating memory device.
• Figs. 7-19 are process steps to form a floating gate memory device in accord with the present invention.
• Fig. 20 is an example of floating gate memory cells in accord with the present invention having a non- uniform gate structure.
• three devices will be constructed in a common substrate 48, which is part of a wafer, not shown.
• the three devices will be n-type devices, but this is for illustrative purposes only and it would be understood by a person versed in the art that the following process and structure can readily be extended to p-type and CMOS architecture.
• One device will be a salicide floating gate memory cell and the other two devices will be n-type enhancement mode, MOS switch transistors with one of the two being a salicide n-type MOS switch transistors and the other not receiving silicide.
• MOS switch transistors with one of the two being a salicide n-type MOS switch transistors and the other not receiving silicide.
• both of the n-type MOS switch transistors have an LDD structure, but if it were desired that some MOS switch transistors not have an LDD structure, then certain process steps may be omitted and additional masking steps may be necessary.
• the floating gate memory cell which would typically be part of a large array of memory cells, is constructed concurrently with the two n-type, enhancement mode MOS switch transistors.
• the memory cell array separately by taking appropriate masking steps to isolate a memory cell array region of an IC from all periphery regions of the IC. The periphery circuitry of the memory IC would then be constructed after completion of the memory array, or vise-versa.
• Reference characters 40 and 50 will identify the two n-type MOS transistors. Transistor 40 will be a salicide transistor and transistor 50 will not receive any silicide. Reference character 60 will identify the floating gate memory cell, which in the preferred embodiment receives silicide.
• construction of floating gate memory cell 60 is begun before initiating construction of transistors 40 and 50.
• a mask 70 is laid over areas where transistors 40 and 50 are to be constructed.
• a protective buffer oxide layer may optionally be grown on substrate 48 prior to laying mask 70.
• An oxide layer 72 is grown on the surface of substrate 48 in a region where non-volatile gate memory cell 60 is to be constructed. If non-volatile memory cell 60 is to be an EPROM cell, then oxide layer 72 would have a preferred thickness of 120 A to 250 A, but if non-volatile memory cell 60 is to be an EEPROM cell, then oxide layer 72 would have a preferred thickness of 50 A to 100 A.
• a first polysilicon layer 74 is laid over oxide layer 72. First polysilicon layer 74 will later be patterned to form the floating gate of memory cell 60 and oxide layer 72 will be patterned into the memory cell's gate oxide under the floating gate.
• mask 70 is removed and a thick oxide layer 76 is grown on top of the areas where devices 40-60 are to be constructed, including over first polysilicon layer 74.
• Thick oxide layer 76 is made thick enough to prevent charge tunneling, and has a preferred thickness of 120 A to 250 A.
• a second polysilicon layer 78 is then deposited over thick oxide layer 76.
• the etchant step configures thick oxide layer 76 and second polysilicon layer 78 to form thick gate oxides 49 and 59, as well as control gates 43 and 53 of transistors 40 and 50, respectively.
• Control gate 43 has a preferred channel length of 0.2 ⁇ m to 1.5 ⁇ m.
• Gate 53 has a similarly preferred channel length of 0.2 ⁇ m to 1.5 ⁇ m.
• the same etchant step also forms interpoly oxide 68, control gate 63, gate oxide 61 and floating gate 69 of memory cell 60.
• Memory cell 60 has a preferred channel length of 0.25 ⁇ m to 1.0 ⁇ m and control gate 63 forms a primary capacitive connection to floating gate 69.
• a re-oxidation step forms an oxide regrowth, or re-oxide layer, 73 over the surface of substrate 48 and over the gates of devices 40, 50 and 60, as shown in Fig. 10.
• oxide regrowth, or re-oxide layer, 73 is grown to protect the surfaces of silicon substrate 48 and polysilicon layers 43, 53, 63 and 69 from damage during subsequent process steps.
• the inventors have found that if the thickness of re-oxide 73 at the sidewalls of the floating gate 69 fall below a certain point, it can affect the integrity of floating gate 69 even if re-oxide 73 remains thick enough to still protect the surface of floating gate 69 from damage during subsequent process steps, as explained below.
• a mask layer 71 is then laid over memory cell 60. At this point, lightly doped -n regions 45b/47b and 55b/57b are self-aligned on either side of control gates 43 and 53, respectively. Mask 71 protects memory cell 60 during formation of the lightly doped -n regions.
• a first arsenic ion implantation "A" forms lightly doped n- regions 45b and 47b in transistor 40 and lightly doped regions 55b and 57b in transistor 50.
• Lightly doped regions 45b/47b and 55b/57b have a preferred ion concentration of I0 15 cm “2 to I0 19 cm "2 and a preferred depth of 0.15 ⁇ m to 0.3 ⁇ m.
• Mask 71 is then removed off floating gate memory cell 60.
• a new masking layer 75 is placed over transistors 40 and 50, and a second arsenic ion implantation "B" forms heavily doped n+ source 65 and drain 67 regions in floating gate memory cell 60 to a preferred ion concentration of 10 20 cm “2 to 10 21 cm “2 and a preferred depth of 0.3 ⁇ m to 0.6 ⁇ m.
• Fig. 12 shows transistors 40 and 50 with partially constructed source regions 45b and 55b, respectively, and partially constructed drain regions 47b and 57b, respectively.
• Re-oxide layer 73 still covers devices 40-60. Construction of sidewall spacers in preparation of salicide process steps is now initiated.
• a nitride layer 77 is laid over MOS transistors 40 and 50 and over floating gate memory cell 60 by mean of an LPCVD reactant or CVD reactant and etchant step.
• nitride in the construction of the sidewall spacer for floating gate, memory 60 prevents charge leakage off of floating gate 69 due to a previously unrecognized problem identified by the inventors of the present invention, as explained below.
• Nitride layer 77 is used to form an oxide- protecting cover, or coating, over re-oxide layers 73 of devices 40-60. If memory cell 60 was designated not to receive silicide, nitride layer 77 would still be used to form the oxide-protecting cover over re-oxide layer 73.
• nitride layer 77 is etched down to the substrate to form sidewall spacers 44/46 for transistor 40, sidewall spacers 54/56 for transistor 50 and sidewall spacers 64/66 for memory cell 60. Sidewall spacers serve as an oxide-protecting cover over re-oxide layer 73 at the sides of floating gate 69.
• nitride sidewall spacers results in the removal of the re-oxide off the tops of control gates 43, 53 and 63, but this causes no structural damage to the control gates since later passivation layers provide protection for the top of the control gates. Removal of re-oxide layer 73 from the tops of control gates 43, 53 and 63 also does not affect the reliability of devices 40-60 since the control gates do not store charge and thus are not subject to the charge leaking problem affecting floating gate 69.
• a resist mask 78 is placed over memory cell 60 followed by a third heavily doped +n arsenic ion implantation "C" applied to all device 40-60.
• sidewall spacers 44 and 46 define the length of lightly doped -n regions 45b and 47b, respectively. Ion implant "C" forms heavily doped +n source region 45a and heavily doped +n drain region 47a to finish the lightly doped drain, LDD, construction of transistor 40.
• sidewall spacers 54 and 56 define the length of lightly doped -n source region 55b and lightly doped -n drain region 57b, while allowing formation of self-aligned, heavily doped n+ source region 55a and heavily doped +n drain region 57a.
• Heavily doped regions 45a, 47a, 55a and 57a have a preferred ion concentration of 10 20 cm “2 to 10 21 cm "2 and a preferred depth of 0.2 ⁇ m to 0.4 ⁇ m.
• an oxide layer 79 is deposited over devices 40-60.
• Oxide layer 79 will be removed off of devices which need a silicide layer and remain on devices which do not need a silicide layer.
• devices 40 and 60 will undergo salicide processes while transistor 50 will receive no silicide. Therefore, a fifth mask 81 is laid over transistor 50 and not over devices 40 and 60.
• Oxide layer 79 is then etched away off of devices 40 and 60 using hydrogen fluoride, HF, an etchant which attacks oxide and is highly selective of nitride. If it were desired that memory cell not receive silicide, then mask layer 81 would also be placed over memory cell 60.
• FIGs. 16 and 17 illustrate some of the consequences of the removal of oxide layer 79 off of devices 40 and 60 if the sidewall spacers of the memory cell 60 and transistor 40 were constructed of oxide.
• Fig. 16 shows prior art transistors 40' and 50'
• Fig. 17 shows three examples of possible deformations of memory cell 60' which the inventors have identified as sources of charge leakage off of floating gate 69'.
• all elements in Figs. 16 and 17 similar to those of Fig. 15 are identified with similar reference characters plus the addition of a prime symbol.
• devices 40' and 50' are representative of devices 40 and 50 of Fig. 15, respectively. Since device 50' is not intended to receive salicide, protective oxide layer 79' is shown to remain on top of device 50' in Fig. 16a while titanium metal layer 83' is laid over all devices, including device 40' and 60'. Titanium metal layer 83' will form a self-aligned silicide layer on all exposed silicon and polysilicon areas following a heat annealing step, as explained above. Since all silicon surfaces of device 50' are protected under oxide mask 79', no silicide will form on its source 55 ' , drain 57 ' or control gate 53 ' . Device 40', however, is intended to receive silicide, and Fig. 16a shows that protective oxide mask 79' is etched off prior to the laying of titanium metal layer 83 ' .
• oxide sidewall spacers 44' and 46' are reduced in size during the removal of oxide layer 79, two problems may result. The first is the formation of lateral silicide bridging as explained above. But assuming that oxide sidewall spacers 44' and 46 are not reduced in height enough for lateral silicide bridging between gate 43' and source 45a' and drain 47a' regions, the inventors have identified an additional source of performance degradation not related to the height of oxide sidewall spacers 44' and 46', but rather due to a reduction in the width of oxide sidewall spacers 44' and 46'.
• oxide sidewall spacers 44' and 46' causes a degradation in the lightly doped drain structure of transistor 40'. If the width of oxide sidewall spacers 44' and 46' is reduced, they will pull away by an amount "L" from their respective boundary abutting the lightly doped -n drain region 47b' and the heavily doped +n drain region 47a' or the lightly doped -n source region 45b' and the heavily doped +n source region 45a'.
• the titanium metal film 40' reacts with the exposed silicon of source 45', drain 47' and control gate 43'. As explained above, some of the silicon from control gate 43', source 45' and drain 47 diffuse over oxide sidewall spacers 44' and 46' during the heat annealing treatment resulting in the formation of partial vertical silicide over oxide spacers 44' and 46'. After the formation of silicide, all excess titanium metal is removed resulting in the structure of Fig. 16b.
• prior art oxide sidewall spacers 44' and 46' are shown to be tall enough to prevent vertical silicide 95' from causing any bridging problems, and silicide 93b' on the source 45a' and drain 47a' regions is shown not to be deep enough to cause any problems, as discussed above in reference to the identified prior art.
• the width of the prior art sidewall spacers 44' and 46' has been reduced by an amount L.
• Silicide 93b' is formed on the exposed surface of the lightly doped n- drain 47b' and lightly doped n- source 45b' regions. This causes partial shunting of the lightly doped n- regions 45b' and 47b' with their respective heavily doped n+ regions 45a' and 47a'.
• the resistance, and therefore the effective length, of the lightly doped regions 45b' and 47b' is reduced. Since the lengths of the lightly doped n- regions 45b' and 47b' enhance the transistor action of device 40' as well as raise the operating source-to- drain, Vds, voltage of the device, a reduction in the effective length of lightly doped regions 45b' and 47b results in a transistor having a lower breakdown voltage, reduced performance and lower reliability.
• the inventors have also identified a source of charge loss on prior art floating gate memory cells due to a reduction in the width of prior art oxide sidewall spacers. Since single gate MOS switch transistors such as devices 40' and 50' of Fig. 16a are not required to store charge on their control gates 43' and 53', respectively, this charge loss problem does not afflict single gate switch transistors and was therefore not previously identified in the art of MOS switch transistor architecture.
• floating gate memory cells are generally more resistant to silicide bridging over sidewall spacers than single gate enhancement mode transistors due to their use of larger sidewall spacer, and floating gate memory cells are more resistant to the depth of silicide growth over source and drain region than single gate switch transistor due to the use of deeper source and drain regions to resist high voltages, which are not applied to signal gate enhancement mode transistors.
• floating gate transistors since floating gate transistors generally do not require a lightly doped drain structure, they do not suffer from the shunting of the lightly doped n- regions of a source or drain to its respective heavily doped n+ region. Thus, a floating gate memory cell will generally not experience the structural degradation associated with a single gate enhancement mode transistor in a salicide process.
• floating gate memory cells store information in the form of trapped charge in their floating gate.
• the inventors have identified a source of charge leakage off of a memory cell's floating gate, which can lead to premature cell failure and an overall degradation in a memory array's performance.
• the source of charge leakage is due to various memory cell deformations which can lead to a thinning of the re-oxide layer surrounding the floating gate.
• Single gate enhancement mode transistors do not require any such trapping of charge for proper operation. In fact, single gate enhancement mode transistors are designed to avoid charge trapping in their control gate since such trapping would alter their behavior characteristic and introduce structural defects into their gate oxide which would reduce their life expectancy.
• Figs. 17A-17C illustrate three examples of possible memory cell deformations which can lead to a thinning of re-oxide layer 73' surrounding floating gate 69 ' and to charge leakage due to the use of prior art oxide sidewall spacers 64' and 66'.
• the problem afflicting floating gate memory cells does not result from the use of silicide directly. Rather, the problem is a result of the process steps required to form silicide. Therefore, Figs. 17A-17C illustrate the source of charge leakage identified by the inventors without making any reference to the location of silicide itself.
• 60a' depicts a prior art floating gate memory cell at the process step last depicted in Fig.
• Prior art floating gate memory cell 60b' depicts the state of the memory cell after the removal of protective oxide layer 79 ' in preparation for the laying of a titanium metal film and the formation of silicide.
• a memory array comprises hundreds of thousands, or millions, of memory cells. It is difficult to create a memory array consisting of only perfectly formed memory cells. A percentage of the memory cells within the memory array will have structural abnormalities.
• Fig. 17a depicts memory cell 60a' with an abnormally shaped floating gate 69'.
• Re-oxide 73' is grown on exposed silicon areas. Since re-oxide 73' is formed before to the formation of the prior art oxide sidewall spacer 64 ' and 66 ' , re-oxide 73 ' is shown to surround control gate 63 ' , floating gate 69 ' and an area under prior art oxide sidewall spacers 64 ' and 66 ' .
• Cell 60b' depicts the condition of the prior art memory cell after the removal of protective oxide layer 79'. Since the prior art sidewall spacers 64' and 66' are likewise made of oxide, they get partially etched during removal of protective oxide layer 79'. Prior art oxide spacers 64 ' and 66 ' are shown to have much of their original height, but to have lost much of their width. Specifically, oxide spacer 66' has narrowed down to the point where it has eaten away part of the re-oxide layer 73' at the side of drain 67'. Arrow 80' identifies a charge leakage region of re-oxide layer 73 ' .
• Charge leakage region 80' is an area where re-oxide layer 73' is thinned down to a point where it is comparable or thinner than thin oxide tunneling region 61'. In effect, the thickness of re-oxide layer 73' in the area of charge leakage region 80' is reduced below 100 A. As a result, charge which may have been moved into floating gate 69 ' through thin oxide tunneling region 61' can now leak or tunnel out through charge leakage region 80'.
• memory cell 60' is an EEPROM and therefore has a gate oxide 61' of less than 100 A, but if memory cell 60' were an EPROM then gate oxide 61' would necessarily have a thickness greater than 120 A. Thus, if memory cell 60' were an EPROM, then the re-oxide layer 73' in the area of charge leakage region 80' would be thinner than gate oxide 61'.
• a user does not have control over charge escaping through charge leakage region 80'.
• memory cell 60b' develops a built-in potential due to the charge stored in floating gate 69'. This built-in potential drives memory cell 60b's charge loss mechanism. Charge loss through charge leakage region 80' is gradual and not immediately noticeable. Furthermore, charge which leaks out of memory cell 60b' is typically attracted to the substrate, which is coupled to ground. This charge leakage typically does not manifest itself in any detectable circuit logic errors, but does lead to premature loss of data. Thus, this memory cell failure is independent of the presence of silicide and due only to the extreme thinning of re-oxide layer 73', which leads to the formation of charge leakage regions 80'.
• floating gate memory cell 60b' may perform well during initial testing due to no silicide-related failures existing, but charge leakage region 80' will cause floating gate 69' to slowly leak charge during normal use and result in premature loss of data and a memory cell of lower endurance. Since a memory cell's endurance rating is based on initial test results and this charge leakage problem does not manifest itself during initial performance testing, a memory cell's initial performance may no longer be a reliable way of gauging its future performance.
• Fig. 17B illustrates a second structural deviation which can result in the formation of a charge leakage region.
• memory cell 60a' shows control gate 63' having a smaller length than floating gate 69'.
• re-oxide layer 73' surrounds both control gate 63 ' and floating gate 69 ' as well as a region under prior art oxide spacers 64 ' and 66 ' .
• protective oxide layer 79' part of oxide sidewall spacers 64' and 66' are also etched away resulting in the structure of 60b'.
• prior art oxide spacers 64 ' and 66 ' end up with a cascade structure illustrated by memory cell 60b'. It is possible for the prior art oxide sidewall spacers of some cells to be eaten more than others such that, for example, in memory cell 60b' oxide sidewall spacers 66' is eaten down to the point where it degrades re-oxide layer 73 ' . This forms a thinning of the re-oxide layer 73' adjacent floating gate 69' resulting in the formation of charge leakage region 80'. Charge can then leak out of floating gate 69 ' through charge leakage region 80'. With reference to Fig.
• Control gate 63' of memory cell 60a' is shown to have a base of length comparable to that of floating gate 69 ' , but control gate 63 ' is also shown to be tapered and have a smaller length at its top than at its base. Nonetheless, re-oxide layer 73' still surrounds control gate 63 ' and floating gate 69 ' , as well as regions under prior art oxide spacers 64' and 66'.
• control gate 63 ' due to the tapering of control gate 63 ' , even more of sidewall spacers 64 ' and 66 ' is etched away during removal of protective oxide layer 79 ' , as demonstrated by memory cell 60b'. In memory cell 60b', oxide sidewall spacer 64 ' is completely etched off control gate 63 ' and has eaten away at re-oxide layer 73' at a corner of floating gate 69 ' thus forming charge leakage region 80 ' .
• nitride in the formation of sidewall spacers in floating gate cells allows a higher control of protective oxide layer 79 and thus a better control of the re-oxide layer surrounding the floating gate.
• HF an etchant highly selective of nitride
• By avoiding the etching of the sidewall spacers one can avoid over thinning of the re-oxide layer surrounding the floating gate and thereby preventing this hereunto unrecognized charge leakage problem.
• nitride sidewall spacers are used, as proposed in the present invention, the problems highlighted in Figs. 16 and 17 are avoided, and following the removal of protective oxide layer 70 in Fig. 15 by using a hydrogen fluoride etchant, one would proceed to the process step illustrated in Fig. 18.
• a metal film 83 preferably titanium, for reacting with exposed silicon and polysilicon and forming silicide is deposited over all devices 40-60.
• Transistor 50 still has oxide layer 79 covering it, and therefore does not come in contact, or react with, titanium film 83 and does not form silicide.
• oxide layer 79 has been etched off of devices 40 and 60 and titanium film 83 is in direct contact with their respective source, drain and control gate regions.
• Sidewall spacers 44 and 46 of transistor 40 and sidewall spacers 64 and 66 of floating gate memory cell 60 show minimal reduction in size due to the use of nitride in their construction and the nitride selective etchant used in the removal of oxide layer 79.
• lightly doped -n regions 45b and 47b of transistor 40 likewise show no reduction in size.
• re- oxide layer 73 at the sides of floating gate 69 experiences no thinning and does not develop any charge leakage regions.
• a heat annealing step of preferably 600°C to 800 °C is applied for a period of 10 sec to 60 sec in a preferred nitrogen ambient. This causes titanium film 83 to react with the exposed silicon and polysilicon of devices 40 and 60, but oxide layer 79 prevent titanium film 83 from reacting with transistor 50. After annealing, any unreacted titanium 83 is removed. Oxide mask 79 is then removed by applying a hydrogen fluoride etchant to devices 40-60, and the surface of the wafer, i.e. substrate 48, is then cleaned using ammonium hydroxide resulting in the structure of Fig. 19.
• floating gate memory cell 60 is shown to have silicide growth 99 on its source 65, drain 67 and control gate 63.
• MOS Transistor 40 is shown to have silicide 97 on its source 45a, drain 47a and control gate 43.
• Fig. 19 also shows the formation of vertical silicide 103 on memory cell 60 over nitride sidewall spacers 64 and 66 in addition to the desired salicide 99.
• Vertical silicide 103 is caused by silicon from source region 65, drain region 67 and control gate 63 partially diffusing into titanium film 83 of Fig 18 over sidewall spacers 64 and 66. Vertical silicide 103 is too short to cause any bridging errors.
• nitride sidewall spacers 64 and 66 serve as oxide-protecting covers over re-oxide layer 73 which prevent thinning of re-oxide layer 73 and thereby prevent the creation of charge leakage regions.
• sidewall spacers 44 and 46 suffer minimal reductions in width, and thus lightly doped -n source region 45b and lightly-doped drain region 47b of transistor 40 suffered no reduction in effective length.
• Transistor 40 also shows some lateral silicide 101 over its nitride sidewall spacers, but sidewall spacers 44 and 46 are tall enough to prevent bridging.
• nitride sidewall spacers 54 of device 50 remain relatively unaffected by the etching away of oxide mask layer 79 in Fig. 18.
• Fig. 19 memory cell 60 is shown to receive silicide 99, and its gates 63 and 69 are not misshaped. But as explained above, it is not necessary for a memory cell to be subjected to silicide process steps in order for the above described charge leakage regions to form.
• Fig. 20 depicts three examples of memory cells with malformed gate stack structures and which do not receive silicide and thus remain covered by oxide mask layer 79 of Fig. 15 during all salicide process steps. The structural deviations shown in Fig. 20 are similar to those depicted in Fig. 17 above.
• memory cell 60 is shown to have a floating gate 69 with a protruding end.
• nitride layers 64 and 66 serve to protect re-oxide layer 73 and thus prevent the formation of charge leakage regions.
• Fig. 2OB shows control gate 63 having a smaller length than floating gate 69
• Fig. 20C shows that control gate 63 is tapered toward the top.
• an oxide-protective cover such as nitride
• a re-oxide layer at the sides of a floating gate prior to the laying of an oxide mask in preparation of salicide process steps can greatly reduce or prevent the formation of uncontrollable charge leakage regions adjacent the floating gate.
• This protection is further increased by using an oxide etchant which is highly selective of nitride, such as hydrogen fluoride. As a result, the memory cell will have a higher reliability.

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