EP0922331A1 - Procede et dispositif pour optimiser le processus d'interruption d'un sectionneur de puissance a semi-conducteur blocable non verrouillant - Google Patents

Procede et dispositif pour optimiser le processus d'interruption d'un sectionneur de puissance a semi-conducteur blocable non verrouillant

Info

Publication number
EP0922331A1
EP0922331A1 EP97918888A EP97918888A EP0922331A1 EP 0922331 A1 EP0922331 A1 EP 0922331A1 EP 97918888 A EP97918888 A EP 97918888A EP 97918888 A EP97918888 A EP 97918888A EP 0922331 A1 EP0922331 A1 EP 0922331A1
Authority
EP
European Patent Office
Prior art keywords
input
gate
power semiconductor
semiconductor switch
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97918888A
Other languages
German (de)
English (en)
Inventor
Manfred Bruckmann
Benno Weis
Ingolf Hoffmann
Stefan Sparger
Hans-Günter ECKEL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0922331A1 publication Critical patent/EP0922331A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
    • H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Definitions

  • the invention relates to a method for optimizing the switch-off process of a non-latching, switchable power semiconductor switch in a hard-switching converter and a device for carrying out the method.
  • Non-latching power semiconductor switches are semiconductor components in which a control signal must be constantly present at the control input so that they remain in the conductive state.
  • the non-latching, switchable power semiconductor switches include the bipolar power transistor (LTR) and the field-controlled, switchable semiconductor components.
  • the field-controlled, switchable semiconductor components include, for example, the self-blocking field effect transistor (MOS-FET), the insulated gate bipolar transistor (IGBT), the field-controlled thyristor, also referred to as MOS Controlled Thyristor (MCT), ...
  • the switching time is set via the respective level of the applied control voltage and an associated gate resistance.
  • the component properties couple the voltage rise and current drop times to one another when the power semiconductor switch is switched off.
  • the control of the transients also becomes important, since the current change speed (di / dt) increases with the current to be switched off and the voltage change speed (du / dt) increases with the increase in the intermediate circuit voltage .
  • the voltage change speed must not exceed the values specified by the manufacturer so that the power semiconductor switch does not snap into place when the device is switched off.
  • the overvoltage depends on the leakage inductance in the circuit and on the current change rate. By reducing the current change speed, the overvoltage can be reduced, particularly in the event of a short circuit.
  • EP 0 645 889 A1 discloses a method and a device for limiting the current drop rate when switching off power semiconductor switches with a MOS control input.
  • a counter voltage is generated when switching off, depending on an inductance, which is fed back to a gate-emitter voltage present at the power semiconductor switch.
  • This feedback increases the gate-emitter voltage, which means that the switching speed is effectively reduced without delay, without increasing the storage time of the power semiconductor switch or influencing the switch-on behavior.
  • This negative feedback is particularly effective when very high negative current steepness occurs, for example overcurrent or short-circuit current.
  • the value of the current change speed can be set independently of the nominal operation or short-circuit operation.
  • the value of the inductance can be changed to adjust the counter voltage and thus the value of the current change rate. The change in the value of the inductance can only be varied within very narrow limits in view of the low-inductance structure of a converter.
  • a protective circuit for a power semiconductor switch is known from EP 0 361 211 B1, which has a load current monitoring circuit having a collector-emitter and a base-emitter monitoring and an OR gate, and a first and second negative current source or one has first and second switchable gate discharge resistor.
  • the load current monitoring circuit is linked on the output side to a control element which is connected on the output side, inter alia, to the second negative current source or the second switchable gate discharge resistor.
  • the load current monitoring circuit determines whether the power semiconductor switch is in nominal or short-circuit operation. Depending on this, either the first or the second negative current source is activated in order to switch off the power semiconductor switch. This prevents the power semiconductor switch from being cleared hard in the event of a short circuit. This leads to single-line effects, as a result of which the power transistor loses its ability to be switched off. Because the power transistor can be switched off in the event of a short circuit with a smaller surge current, the maximum short circuit strength of the power transistor can also be used in the event of a short circuit.
  • the gate-emitter voltage with the high gate discharge resistance is lowered after a predeterminable delay time until the power semiconductor switch is blocked.
  • This two-stage gate control requires precise knowledge of the dynamic behavior of the IGBT. If this is not known If the first gate discharge resistor is to be as small as possible, the delay time should be long he ness of the collector-emitter voltage and the second gate discharge resistor can be chosen as large as possible as the AnTENsgeschwmd.
  • the gate-emitter voltage is lowered with a characteristic gate discharge resistance until the Miller plateau of the gate-emitter voltage is reached.
  • the collector-emitter voltage increases while the gate-emitter voltage is equal to the Miller plateau.
  • the gate-emitter voltage is compared with a reference value.
  • the Miller plateau is low, so the first gate discharge resistance throughout Shutdown is used.
  • the Miller plateau of the gate-emitter voltage is high. In this case, the first gate discharge resistor is switched off and a large gate discharge resistor is switched on after a predetermined delay time.
  • the invention is based on the object of specifying a method and a device for optimizing the disconnection process of a non-latching, disconnectable power semiconductor switch in a hard-switching converter, with a simple mode of operation as well as minimal and simple ascertainable measurement variables having priority.
  • the voltage gradient and the current gradient of the switch-off process of a non-latching, switchable power semiconductor switch can be influenced separately.
  • Different discharge currents are used for this, the dependency the state of the collector-emitter voltage of the power semiconductor switch can be selected.
  • the discharge current is set so that the maximum permissible voltage change speed of the power semiconductor switch can be set.
  • the collector-emitter voltage has reached a predetermined reference voltage value, the discharge current is reduced to a lower value.
  • the level of this reduced discharge current depends on the value of the overvoltage, which may occur as a maximum.
  • the reference voltage value is the same
  • the advantage of the method according to the invention lies in the fact that for switching from one discharge current to another, precise knowledge of the dynamic behavior of the power semiconductor switch is no longer necessary, since the switchover is only carried out when the collector-emitter voltage reaches a reference voltage value at which the collector current begins to commutate. To determine this switchover point, only the collector-emitter voltage has to be compared with a corresponding reference voltage value. By decoupling the voltage rise and current drop time, it is possible to make the switching times of non-latching, switchable power semiconductor switches in hard-switching converters as short as possible, with small switching losses being achieved.
  • the gate-emitter voltage of the power semiconductor switch is lowered at the beginning of the switch-off process with the aid of a constantly reduced discharge current until the collector-emitter voltage of the power semiconductor switch increases.
  • This Slow switch-off at the beginning of the switch-off process is particularly advantageous in the event of a short circuit.
  • a device for carrying out the method according to the invention uses a conventional control device for a non-latching, switchable power semiconductor switch, which is expanded by a device for detecting the condition of the collector-emitter voltage of the power semiconductor switch, a logic circuit and two switchable devices for generating two different discharge currents is, these switchable devices are controlled by the logic circuit depending on the state of the collector-emitter voltage during the switch-off process.
  • the switchable device for generating a high discharge current is usually superfluous, since a conventional control device already has a switchable device for generating a high discharge current.
  • a conventional drive device can be modified such that the switch-off process for a non-locking, switchable power -Semiconductor switch is optimized.
  • a ramp generator is provided which can be linked to the gate connection of the power semiconductor switch by means of a switch, the switch being provided with a sequence control. This results in a particularly simple modification of a conventional control device with which the switch-off process can be optimized.
  • FIG. 1 shows in a diagram the time profiles of the collector-emitter voltage, the collector current and the gate-emitter voltage of an IGBT during a switch-off process.
  • FIG. 2 is a block diagram of a first embodiment of the device for performing the method according to the invention shown the
  • FIG. 3 shows a block diagram of a device for detecting the condition of the collector-emitter voltage of the device according to FIG. 2
  • FIG. 4 shows an exemplary embodiment of the device for detecting the condition of the collector-emitter voltage
  • FIG. 5 shows a block diagram of the logic circuit of the device according to FIG. 2
  • in 6 shows a block diagram of a further device for state detection of the collector-emitter voltage of the device according to FIG. 2
  • FIG. 7 shows a block diagram of an evaluation device of the further device for state detection of the collector-emitter voltage according to FIG. 6
  • FIG. 8 shows a block diagram of a Second embodiment of the device for performing the method according to the invention is shown
  • FIG 9 shows a block diagram of a third embodiment of the device for performing the method according to the invention.
  • the method and the device for optimizing the disconnection process of a non-latching, disconnectable power semiconductor switch is explained in the figures mentioned using the example of an IGBT high-current module 2 with a conventional control device 4, the IGBT high-current module 2 being provided with a wider line for better identification. strength is drawn.
  • the IGBT high-current module 2 is connected with its collector connection C to a positive intermediate circuit rail 6, which carries a positive intermediate circuit voltage + U Z.
  • the emitter connection E is connected on the one hand to an AC connection 8 and on the other hand to a collector connection C of a further IGBT high-current module with a control device, which are not shown in more detail for reasons of clarity.
  • the control device 4 is connected with its two outputs 10 and 12 to the gate connection G and to the emitter control input E s of the IGBT high-current module 2.
  • the device for performing the method according to the invention is independent of the design of the control device.
  • the potential of the gate G In order to be able to switch off an IGBT high-current module 2, the potential of the gate G must be discharged to the emitter potential. As a rule, the gate potential is applied to (opposite to the emitter) negative potential in order to counter interference.
  • the gate G is discharged via a gate discharge resistor R G ⁇ ff, which can also be the gate charge resistor R ⁇ on.
  • the discharge process begins at time t 0 and initially falls to the Miller plateau U (time ti), which depends on the load current ⁇ . is, from.
  • the parasitic capacities are first reloaded here.
  • the collector-emitter voltage U CE rises at the time t- (Miller plateau).
  • the collector-emitter voltage U CF reaches the value of the intermediate circuit voltage + U Z (time t,). a freewheeling diode can take over the current from the IGBT high-current module 2 and the collector current I c drops.
  • the gate voltage U Gt drops - the current drop time can be influenced by a type of control (low or high discharge current of the control capacity) and ends at time t3. From this time t 3 , only a tail current flows through the IGBT high-current module 2, which results from the stored charge of the component. In contrast to the previous phases, the control 4 has no influence on the tail current.
  • the collector-emitter voltage U CE at the IGBT high-current module 2 exceeds the intermediate circuit voltage + U Z due to the stray inductance in the supply lines.
  • the shutdown process can be changed by changing the
  • a small resistance value means a large current flow out of the gate G of the IGBT high-current module 2, thus a faster recharging, a higher voltage rise rate and a higher current drop rate in the individual switching processes.
  • FIG. 2 shows a block diagram of a first embodiment of a device for carrying out the method according to the invention.
  • This device has a conventional control device 4, a device 14 for state detection of the collector-emitter voltage U CE of the IGBT high-current module 2, a logic circuit 16 and two switchable devices 18 and 20 for generating two different ones
  • the input 22 of the device 14 is connected to a collector terminal C of the power semiconductor switch 2 and its output 24 to a first input 26 of the logic circuit 16.
  • the output 30 or 32 of the logic circuit 16 is connected to a control input 34 or 36 of the devices 18 or 20.
  • the output of the device 18 or 20 is linked to the gate connection G of the power semiconductor switch 2 and the input thereof is connected to a signal output 38 or 40 of the control device 4.
  • the apparatus of the gate terminal G is the power semiconductor switch 2 to a second input 42 of the means 14 of the collector-emitter voltage U C F of the power semiconductor switch 2 is connected to the state detecting means of a broken line in this species.
  • the connection of the potential profile of the gate-emitter voltage U GE depends on the embodiment of the device 14.
  • This em- direction 14 to the state detection of the collector-emitter voltage U CE of the IGBT high-current module 2 comprises a voltage divider 44, a fast comparator 46, an adjustable Re ⁇ erenznapssttle 48 and a monostable multivibrator 50.
  • the voltage divider 44 is connected on the input side to the input 22 of the device 14 and on the output side to the non-inverting input of the comparator 46.
  • the reference voltage source 48 is connected to the inverting input of this comparator 46.
  • the comparator 46 is connected to the output 24 of the device 14 via the monostable tilting stage 50.
  • the output signal y of the fast comparator 46 changes from low to high as soon as the collector-emitter voltage U ct is equal to the reference voltage U Eret .
  • the monostable multivibrator 50 is started, so that the output signal S Pu ⁇ s of the device 14 changes from low to high.
  • the output signal S Pu ⁇ s of the device 14 changes back to low.
  • the time of this monostable multivibrator 50 is set, for example, to a time which elapses if the maximum fall time were realized.
  • the voltage value of the intermediate circuit voltage + U Z is selected as the reference voltage U C Eret.
  • the value can also be above or below an operational DC link voltage + U-.
  • FIG 4 is an exemplary embodiment of the device 14 for the state detection of the collector-emitter voltage O C ⁇ des
  • This illustrated embodiment of the device 14 is designed as an analog circuit. As long as the collector-emitter voltage U CE at the input 22 of the device 14 is less than the reference voltage U CEr et ⁇ , the voltage from the Zener diode Dl added. Exceeds the collector-emitter voltage
  • U CE is the reference voltage U C Eref so a current flows through the
  • Emitter voltage change rate is greater than zero.
  • capacitor C2 is quickly charged via diode D2.
  • this transistor T conducts and at the output 24 the device 14 changes the output signal S Pu ⁇ B from 5 V to, for example, 0 V.
  • the rise is Collector-emitter voltage U CE over, no more current flows through the capacitor Cl.
  • the capacitor C2 is slowly discharged through the resistors R1 and R2. With the choice of the resistor R2, this discharge time constant and thus the pulse duration of the output signal S Pu ⁇ s at the output 24 of the device 14 can be set.
  • the capacitor C1 can quickly discharge again when the power semiconductor switch 2 is switched on again.
  • the output signal S Pu ⁇ R must be inverted for further use or the outputs 30 and 32 of the logic circuit 16 must be interchanged.
  • FIG. 5 shows a block diagram of the logic circuit 16 of the device according to FIG. 2.
  • This logic circuit 16 has first and second AND gates 52 and 54 and first and second inverters 56 and 58.
  • the output of the first inverter 56 is connected to an input of the first and second AND gates 52 and 54, respectively.
  • the second input of the first AND gate 52 is linked to the first input 26 of the logic circuit 16, the output of this AND gate 52 being connected to the second output 32 of the logic circuit 16.
  • the input of the second inverter 58 is also connected to the first input 26 of the logic circuit 16 connected and on the output side to a second input of the second AND gate 54, which is connected on the output side to the first output 30 of the logic circuit 16.
  • the first inverter 56 is connected on the input side to the second input 28 of the logic circuit 16.
  • the control signal S ⁇ , F for the first switchable device 18 changes from low to high as soon as the control signal S AUS changes from high to low and the status signal S Pu ⁇ E is low.
  • the control signal S T for the second switchable device 20 changes from low to high when the state signal S P ui alternates from low to high and the switch-off signal S SAU is low. With this level change of the state signal S [uls , the control signal S ⁇ LF changes from high to low.
  • FIG. 6 shows a block diagram of a further embodiment of the device 14 for state detection of the collector-emitter voltage UCE of the power semiconductor switch 2.
  • This embodiment of the device 14 differs from the embodiment of the device 14 according to FIG. 3 in that an evaluation device 60 is used instead of the monostable multivibrator 50.
  • the first input 62 of this evaluation device 60 is connected to the output of the comparator 46 and the second input 64 connected to the second input 42 of the device 14, at which the gate emitter voltage U GE is present.
  • the gate-emitter voltage U GE and the collector-emitter voltage U CE are queried by means of this evaluation device 60.
  • FIG. 7 shows a block diagram of the evaluation device 60 in more detail.
  • This evaluation device 60 has a comparator 66, a reference voltage source 68 and an AND gate 70.
  • One input of the AND gate 70 is connected to the first input 62 of the evaluation device 60, at which the comparator signal y of the comparator 46 is connected Device 14 is pending.
  • the second input of the AND gate 70 is connected to the output of the comparator 66, the non-inverting input of which is linked to the second input 64 of the evaluation device 60 and the reference voltage source 68 is connected to the inverting input.
  • the evaluation device 60 only delivers a signal when the collector-emitter voltage U CE is greater than / equal to the reference voltage Ucref and the gate-emitter voltage U GE is also greater than / equal to a reference voltage U GEr p f .
  • the reference voltage UcEref indicates the reference value for the Miller plateau, which is known to be dependent on the collector current I c .
  • the reference voltage U GF r e f can also be below the Miller plateau (i.e. below the threshold voltage of the IGBT / type ⁇ 5 V).
  • the gate potential is only reduced with a reduced discharge current if, as a function of the gate-emitter voltage U GE, it has been determined that there is an overload or short circuit. If the gate-emitter voltage UG E remains below the reference voltage U G ret, there is no overload or short circuit, so that the gate potential can be further reduced with an increased discharge current.
  • the switch-off process is thus optimized in such a way that the current drop speed is reduced only in the event of an overload or short circuit, so that the overvoltage is limited to acceptable values.
  • the switchable device 18 or 20 for generating a discharge current can be implemented in different ways.
  • the simplest implementation is em switching off by means of a gate discharge resistor Rcoffi or R Go tt2.
  • the value of the gate discharge resistor Rc o can be selected as the value of the switch-off resistance during conventional switching off.
  • the value of the gate discharge resistor Rcoft is chosen so large that the shutdown process is continued only in a slow manner.
  • These gate discharge resistors R G offi and R GO ft2 are each connected to a negative potential of the control device 4 by means of a switch, in particular a transistor.
  • switchable gate discharge resistors R Got n and R Go £ f2 two switchable voltage sources with the voltages U 0 f- ⁇ and U 0 ff2 can also be used, which are connected to the gate connection G of the IGBT high-current module 2 via a gate discharge resistor are.
  • the voltage U 0tf ⁇ has a small or negative value, so that the voltage drop across the gate discharge current U R is large.
  • the voltage U 0ff2 has a higher value, so that the voltage U R becomes small.
  • the voltage U 0 ff 2 may only be so high that the voltage U R remains positive even at the lowest level of the Miller plateau, in order to prevent the gate G of the power semiconductor switch 2 from being recharged.
  • the different voltage sources can be realized by different supply potentials.
  • switchable current sources can also be used, with one current source supplying a discharge current for a quick shutdown and the other current source delivering a discharge current for a slow shutdown.
  • a switch-off signal SAUS is applied to the control device 4 of the IGBT high-current module 2 from a control set (not shown in more detail). This switch-off signal S ⁇ U £ is thus with also on the logic circuit 16. This switch-off signal
  • the collector-emitter voltage U CE is equal to a saturation voltage which is dependent on the power semiconductor switch 2 and which is approximately zero in comparison to the intermediate circuit voltage + U 7 of the converter.
  • the output signal Sp u i s of the device 14 for state detection of the collector-emitter voltage U CE is in the low state.
  • the control signal S th which represents the fast shutdown mode
  • the control signal SstsL which represents the slow shutdown mode
  • the gate-emitter potential U Gi of the IGBT high-current module 2 is thus lowered with the aid of a constant maximum permissible discharge current.
  • the collector-emitter voltage U CE increases . From the signal curve of the collector-emitter voltage U CE according to FIG. 1 it can be seen that this collector-emitter voltage U CE begins to rise precisely when the gate-emitter voltage U GE is equal to the Miller plateau. As long as the collector-emitter voltage U E is not equal to the reference voltage Uc Er et, the device 18 for generating a discharge current for the fast shutdown mode remains switched on.
  • the output signal S ⁇ ui ⁇ changes after the time set in the monostable multivibrator 50 (> t 4 max) from the high state to the low state, so that the device 18 for the fast shutdown mode is switched on again. If these devices 18 and 20 are realized by means of gate discharge resistors R GoEU and R Go ⁇ z, then the gate connection G of the IGBT high-current module 2 is connected to a negative potential with a low resistance after the time of the monostable multivibrator 50.
  • the device 14 for status detection of the collector-emitter voltage U CE is also supplied with the gate-emitter voltage U GE , it is possible to prevent the switchover from the fast switch-off mode to the slow switch-off mode. That means that this switchover is only carried out if the gate-emitter voltage U CE is greater than / equal to a reference voltage U GEr e £ which specifies a threshold value for the Miller plateau. Since the height of the Miller plateau depends on the collector current I c , the height of the Miller plateau is an indication of normal operation or overload or short-circuit operation of the power semiconductor switch 2. Only when the overload or short-circuit operation is recognized is switched from the fast shutdown mode without delay to the slow shutdown mode.
  • a switch-off process can be optimized with little effort to the effect that when non-latching, switchable power semiconductor switches 2 are used in hard-switching converters, whose switching times should be as short as possible, regardless of the operating state of this power semiconductor switch 2, the Verkuppelung of voltage increase and current is llezeit separately and independently depending on the operating state of the power semiconductor switch 2 is controlled from each other ⁇ the.
  • FIG. 8 shows a second embodiment of the device for carrying out the method according to the invention.
  • This embodiment of the device differs from the embodiment of the device according to FIG. 2 in that instead of the device 14, the logic circuit 16 and the switchable devices 18 and 20, a ramp generator 72, a changeover switch 74 and a sequence control 76 are provided.
  • the ramp generator 72 has its output side connected to an input of the change-over switch 74, whose other input is connected to a first output '10 of the driving device. 4
  • the output of this switch 74 is linked to the gate connection G of the IGBT high-current module 2.
  • the second output 12 of the control device 4 is connected to the emitter control gear E st of the IGBT high-current module 2.
  • the switch 78 of this switch 74 is controlled by the sequence controller 76.
  • This sequence control 76 is connected on the input side to the collector connection C of the IGBT high-current module 2.
  • this sequence control 76 is supplied with the switch-off signal S Aus .
  • Control signal Sum generates that the switch 78 of the switch 74 controls during the shutdown process.
  • the gate discharge resistor R G ci ⁇ is connected in the control device 4 by means of a transistor of the push-pull stage to the negative potential of -5 V and on the other hand the switch 78 of the changeover switch 74 is controlled by the sequence control 76 such that the ramp generator 72 is connected to the gate connection G of the IGBT high-current module 2. As a result, the gate G is discharged by means of the ramp generator 72.
  • the control signal S changes to the state control 76, whereby the switch 78 of the switch 74 is flipped, so that the gate G of the IGBT high-current module 2 with the Gate discharge resistor R ⁇ ( f is connected. This is stopped by switching off the ramp generator 72 from the gate terminal G.
  • the gate G of the IGBT high-current module 2 is now rapidly discharged via the gate discharge resistor R Co tt. During this rapid discharge The gate-emitter voltage Ui rises in the gate G.
  • the control signal Su "of the sequence controller 76 changes its state again, as a result of which the switch 78 of the changeover switch 74 is switched over again so that the gate G is again discharged with a set steepness in a controlled manner via the ramp generator 72.
  • the control signal S Ur changes its state again and now connects the gate G to the gate discharge resistor Rcott, so that the gate G of the power semiconductor switch 2 is connected with low resistance to the negative potential.
  • This embodiment of the device also referred to as a memory circuit, has the advantage over the embodiment of the device according to FIG. 2 that at the beginning of the switch-off process the gate G of the power semiconductor switch 2 is discharged with the same steepness as in the period t 4 - t 2 , m which is the collector-emitter voltage U CE greater than / equal to the reference voltage U Cir , r. This measure is particularly noticeable in the event of a short circuit.
  • FIG. 9 shows a third embodiment of the device for carrying out the method according to the invention.
  • three em / off switches 80, 82 and 84 are provided instead of the switch 74.
  • the actuation events of these on / off switches 80, 82 and 84 are each connected to a control output of the sequence control 76.
  • the on / off switch 80 connects the output 10 of the control device 4 to the gate connection G, the em / off switch 84 connecting the gate connection G of the IGBT high-current module 2 to an input 86 of the ramp generator 72 and the em- / Off switch 82 connects the output 88 of the ramp generator 72 to the gate terminal G.
  • the ramp generator 72 can optionally control the gate-emitter voltage U GE (em / off switch 82 closed) or track the value of the potential at gate G (em / off switch 84 closed) by means of the em / off switches 82 and 84.
  • the on / off switches 80 and 84 are closed, as a result of which the gate G is quickly discharged by means of the gate discharge resistor Rctt of the control device 4 and the value of the ramp generator 72 is tracked to the value of the potential of the gate G.
  • the on / off switch 82 is closed and the on / off switches 80 and 84 are opened.
  • the ramp generator 72 has exactly the value of the gate voltage. Then the gate G unloaded by means of the ramp generator 72 with the set slope.

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Abstract

L'invention concerne un procédé permettant d'optimiser le processus d'interruption d'un sectionneur de puissance à semi-conducteur (2) blocable non verrouillant dans un convertisseur saturant, ainsi qu'un dispositif permettant de mettre en oeuvre ledit procédé. Selon l'invention, à l'arrivée d'un signal d'interruption (Saus), la tension d'émetteur de grille (UGE) dudit sectionneur (2) est abaissée à l'aide d'un courant de décharge maximum admissible, et sa tension d'émetteur de collecteur (UCE) est contrôlée, de façon à détecter le dépassement d'une tension de référence (UCEref). La valeur de celle-ci est fixée de façon que le courant du collecteur commence à commuter et que, une fois ladite valeur de référence (UCEref) atteinte, le courant de décharge diminue jusqu'à une valeur inférieure à celle du courant de décharge maximum admissible. Le processus d'interruption d'un sectionneur de puissance à semi-conducteur blocable non verrouillant est ainsi optimisé par le fait que la durée de l'accroissement de tension et la durée de la chute d'intensité peuvent être commandées séparément l'une de l'autre.
EP97918888A 1996-08-27 1997-08-18 Procede et dispositif pour optimiser le processus d'interruption d'un sectionneur de puissance a semi-conducteur blocable non verrouillant Withdrawn EP0922331A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE1996134612 DE19634612A1 (de) 1996-08-27 1996-08-27 Verfahren und Vorrichtung zur Optimierung des Abschaltvorgangs eines nichteinrastenden, abschaltbaren Leistungs-Halbleiterschalters
DE19634612 1996-08-27
PCT/DE1997/001778 WO1998009378A1 (fr) 1996-08-27 1997-08-18 Procede et dispositif pour optimiser le processus d'interruption d'un sectionneur de puissance a semi-conducteur blocable non verrouillant

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EP2424112B1 (fr) * 2010-08-23 2015-07-01 ABB Research Ltd Équilibrage de courant de composants semi-conducteurs raccordés en parallèle
DE102011109537B4 (de) * 2011-08-05 2021-12-30 Sew-Eurodrive Gmbh & Co Kg Umrichtersystem mit Überwachungseinrichtung, Antrieb und Fahrzeug
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NO990962D0 (no) 1999-02-26
NO990962L (no) 1999-04-27
DE19634612A1 (de) 1998-03-12
CN1234146A (zh) 1999-11-03
WO1998009378A1 (fr) 1998-03-05

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