EP0922331A1

EP0922331A1 - Process and device for optimizing the power-down cycle of a non-engaging, interruptable power semiconductor switch

Info

Publication number: EP0922331A1
Application number: EP97918888A
Authority: EP
Inventors: Manfred Bruckmann; Benno Weis; Ingolf Hoffmann; Stefan Sparger; Hans-Günter ECKEL
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1996-08-27
Filing date: 1997-08-18
Publication date: 1999-06-16
Also published as: NO990962L; CN1234146A; NO990962D0; WO1998009378A1; DE19634612A1

Abstract

This invention concerns a process for optimizing the power-down cycle of a non-engaging, interruptable power semiconductor switch (2) in a saturating power converter and a device for carrying out the process. According to the invention, when the interrupt signal (Saus) arrives, the gate emitter voltage (UGE) of this power-semiconductor switch (2) lowered with the help of a maximally permissible discharge current and its collector-emitter voltage (UCE) are monitored against exceeding a reference voltage (UCEref), the value of which is set so that the collector current (IC) begins to commutate, and upon reaching the reference value (UCEref), the discharge current is reduced to a value which is below the value of the maximum permissible discharge current. Thus, the power-down cycle of a non-engaging, interruptable power semiconductor switch (2) is largely optimized, so that the voltage rise and current drop times can be separately controlled.

Description

description

Method and device for optimizing the switch-off process of a non-latching, switchable power semiconductor switch

The invention relates to a method for optimizing the switch-off process of a non-latching, switchable power semiconductor switch in a hard-switching converter and a device for carrying out the method.

Non-latching power semiconductor switches are semiconductor components in which a control signal must be constantly present at the control input so that they remain in the conductive state. The non-latching, switchable power semiconductor switches include the bipolar power transistor (LTR) and the field-controlled, switchable semiconductor components. The field-controlled, switchable semiconductor components include, for example, the self-blocking field effect transistor (MOS-FET), the insulated gate bipolar transistor (IGBT), the field-controlled thyristor, also referred to as MOS Controlled Thyristor (MCT), ...

In the case of power semiconductor switches with MOS control input, the trend is increasingly towards the high current carrying capacity of the modules. High-current modules are currently available that can carry a drain-source current of 1200 A with a blocking capability of 1700 V. As the current carrying capacity increases, the value of the current change rate (di / dt) also increases significantly, especially when the module is switched off. Since the modules are each electrically connected to a control device and an intermediate circuit, inductivities in the power section of converters usually cause high-energy overvoltages on the IGBT modules during switching operations. In order to achieve small switching losses when using non-latching, switchable power semiconductors in hard switching converters, the switching times must be as short as possible. However, there are limits to this due to design-related leakage capacities and the resulting overvoltages when switching off. In the case of conventional controls, the switching time is set via the respective level of the applied control voltage and an associated gate resistance. With such a drive circuit, the component properties couple the voltage rise and current drop times to one another when the power semiconductor switch is switched off.

With the increase in the voltage and current resistance of non-latching, switchable power semiconductor switches, the control of the transients also becomes important, since the current change speed (di / dt) increases with the current to be switched off and the voltage change speed (du / dt) increases with the increase in the intermediate circuit voltage . The voltage change speed must not exceed the values specified by the manufacturer so that the power semiconductor switch does not snap into place when the device is switched off. The overvoltage depends on the leakage inductance in the circuit and on the current change rate. By reducing the current change speed, the overvoltage can be reduced, particularly in the event of a short circuit.

EP 0 645 889 A1 discloses a method and a device for limiting the current drop rate when switching off power semiconductor switches with a MOS control input. With this method, a counter voltage is generated when switching off, depending on an inductance, which is fed back to a gate-emitter voltage present at the power semiconductor switch. This feedback increases the gate-emitter voltage, which means that the switching speed is effectively reduced without delay, without increasing the storage time of the power semiconductor switch or influencing the switch-on behavior. This negative feedback is particularly effective when very high negative current steepness occurs, for example overcurrent or short-circuit current. The value of the current change speed can be set independently of the nominal operation or short-circuit operation. The value of the inductance can be changed to adjust the counter voltage and thus the value of the current change rate. The change in the value of the inductance can only be varied within very narrow limits in view of the low-inductance structure of a converter.

A protective circuit for a power semiconductor switch is known from EP 0 361 211 B1, which has a load current monitoring circuit having a collector-emitter and a base-emitter monitoring and an OR gate, and a first and second negative current source or one has first and second switchable gate discharge resistor. The

The load current monitoring circuit is linked on the output side to a control element which is connected on the output side, inter alia, to the second negative current source or the second switchable gate discharge resistor. The load current monitoring circuit determines whether the power semiconductor switch is in nominal or short-circuit operation. Depending on this, either the first or the second negative current source is activated in order to switch off the power semiconductor switch. This prevents the power semiconductor switch from being cleared hard in the event of a short circuit. This leads to single-line effects, as a result of which the power transistor loses its ability to be switched off. Because the power transistor can be switched off in the event of a short circuit with a smaller surge current, the maximum short circuit strength of the power transistor can also be used in the event of a short circuit.

In the article "Optimization of the Turn-Off Performance of IGBT at Overcurrent and Short -Circuit Current", by H.-G. Eckel and L. Sack, printed in the conference volume "EPE'93, Vol.2, September 13-16, 1993, pages 317 to 322, two shutdown strategies for an IGBT in a hard-switching power converter are presented. Both strategies are two In the first switch-off strategy, the lowering of the gate-emitter voltage is first started with the low gate-discharge resistance and the collector-emitter voltage is monitored for exceeding a reference voltage of approximately 10 V. If the collector-emitter voltage is higher / equal to the reference voltage, the gate-emitter voltage with the high gate discharge resistance is lowered after a predeterminable delay time until the power semiconductor switch is blocked.This two-stage gate control requires precise knowledge of the dynamic behavior of the IGBT. If this is not known If the first gate discharge resistor is to be as small as possible, the delay time should be long he ness of the collector-emitter voltage and the second gate discharge resistor can be chosen as large as possible as the Anstiegsgeschwmd.

In the second switch-off strategy presented, the gate-emitter voltage is lowered with a characteristic gate discharge resistance until the Miller plateau of the gate-emitter voltage is reached. The collector-emitter voltage increases while the gate-emitter voltage is equal to the Miller plateau. As soon as the collector-emitter voltage exceeds a reference value, for example 10 V, the gate-emitter voltage is compared with a reference value. When the collector current is low, the Miller plateau is low, so the first gate discharge resistance throughout Shutdown is used. With a higher collector current, the Miller plateau of the gate-emitter voltage is high. In this case, the first gate discharge resistor is switched off and a large gate discharge resistor is switched on after a predetermined delay time. When using this second shutdown strategy, precise knowledge of the Miller plateau is needed to implement this strategy.

The main disadvantage of the two shutdown strategies presented is that you have to know the exact relationship between the Miller plateau and the collector current. This can differ from IGBT to IGBT and the delay time must also be adapted to the respective IGBT types, since a delay time that is too short leads to unnecessarily higher losses and a delay time that is too long means a late intervention and the increase in the resistance value of the gate Discharge resistance can therefore no longer have an effect.

The invention is based on the object of specifying a method and a device for optimizing the disconnection process of a non-latching, disconnectable power semiconductor switch in a hard-switching converter, with a simple mode of operation as well as minimal and simple ascertainable measurement variables having priority.

This object is achieved according to the invention with the features of claim 1.

With this method it is achieved that the voltage gradient and the current gradient of the switch-off process of a non-latching, switchable power semiconductor switch can be influenced separately. Different discharge currents are used for this, the dependency the state of the collector-emitter voltage of the power semiconductor switch can be selected. At the beginning of the switch-off process, the discharge current is set so that the maximum permissible voltage change speed of the power semiconductor switch can be set. As soon as the collector-emitter voltage has reached a predetermined reference voltage value, the discharge current is reduced to a lower value. The level of this reduced discharge current depends on the value of the overvoltage, which may occur as a maximum. The reference voltage value is the same

Voltage value at which the collector current begins to commutate. That means that in the case of a converter, the value of the reference voltage is equal to the value of the intermediate circuit voltage.

The advantage of the method according to the invention lies in the fact that for switching from one discharge current to another, precise knowledge of the dynamic behavior of the power semiconductor switch is no longer necessary, since the switchover is only carried out when the collector-emitter voltage reaches a reference voltage value at which the collector current begins to commutate. To determine this switchover point, only the collector-emitter voltage has to be compared with a corresponding reference voltage value. By decoupling the voltage rise and current drop time, it is possible to make the switching times of non-latching, switchable power semiconductor switches in hard-switching converters as short as possible, with small switching losses being achieved.

In an advantageous method according to the invention, the gate-emitter voltage of the power semiconductor switch is lowered at the beginning of the switch-off process with the aid of a constantly reduced discharge current until the collector-emitter voltage of the power semiconductor switch increases. This Slow switch-off at the beginning of the switch-off process is particularly advantageous in the event of a short circuit.

A device for carrying out the method according to the invention uses a conventional control device for a non-latching, switchable power semiconductor switch, which is expanded by a device for detecting the condition of the collector-emitter voltage of the power semiconductor switch, a logic circuit and two switchable devices for generating two different discharge currents is, these switchable devices are controlled by the logic circuit depending on the state of the collector-emitter voltage during the switch-off process. The switchable device for generating a high discharge current is usually superfluous, since a conventional control device already has a switchable device for generating a high discharge current. Thus, with a few additional devices, a conventional drive device can be modified such that the switch-off process for a non-locking, switchable power -Semiconductor switch is optimized.

In an advantageous device, instead of the logic circuit and the switchable devices for generating different discharge currents, a ramp generator is provided which can be linked to the gate connection of the power semiconductor switch by means of a switch, the switch being provided with a sequence control. This results in a particularly simple modification of a conventional control device with which the switch-off process can be optimized.

In a further advantageous device, three switches are used instead of the changeover switch, the actuation receptacles of which are connected to the sequence control, the third switch connects the gate terminal of the power semiconductor switch to an input of the ramp generator. The advantage of this circuit variant compared to the circuit variant with ramp generator and changeover switch, also known as the memory circuit, is that it is ensured that the gate and the ramp generator have the same value at the time of the changeover by the sequence control. Problems with leakage currents can occur in the memory circuit, while the gate potential of the power semiconductor switch is equal to the Miller plateau.

To further explain the invention, reference is made to the drawing, in which exemplary embodiments of the device for carrying out the method according to the invention for optimizing the switch-off process of a non-latching, switchable power semiconductor switch are schematically illustrated.

1 shows in a diagram the time profiles of the collector-emitter voltage, the collector current and the gate-emitter voltage of an IGBT during a switch-off process. FIG. 2 is a block diagram of a first embodiment of the device for performing the method according to the invention shown the

3 shows a block diagram of a device for detecting the condition of the collector-emitter voltage of the device according to FIG. 2, FIG. 4 shows an exemplary embodiment of the device for detecting the condition of the collector-emitter voltage

The device according to FIG. 2, FIG. 5 shows a block diagram of the logic circuit of the device according to FIG. 2, in 6 shows a block diagram of a further device for state detection of the collector-emitter voltage of the device according to FIG. 2, FIG. 7 shows a block diagram of an evaluation device of the further device for state detection of the collector-emitter voltage according to FIG. 6, FIG. 8 shows a block diagram of a Second embodiment of the device for performing the method according to the invention is shown and FIG 9 shows a block diagram of a third embodiment of the device for performing the method according to the invention.

The method and the device for optimizing the disconnection process of a non-latching, disconnectable power semiconductor switch is explained in the figures mentioned using the example of an IGBT high-current module 2 with a conventional control device 4, the IGBT high-current module 2 being provided with a wider line for better identification. strength is drawn. The IGBT high-current module 2 is connected with its collector connection C to a positive intermediate circuit rail 6, which carries a positive intermediate circuit voltage + U _Z. The emitter connection E is connected on the one hand to an AC connection 8 and on the other hand to a collector connection C of a further IGBT high-current module with a control device, which are not shown in more detail for reasons of clarity. The control device 4 is connected with its two outputs 10 and 12 to the gate connection G and to the emitter control input E _{s of} the IGBT high-current module 2.

In the article "Optimized Power Control" by W. Bosterling, W. Keuter and M. Tscharn, printed in the DE-Zeitschπft "Electronics", Volume 24, 1990, pages 62-67, various control devices for IGBT modules are described in detail ben, so that it can be dispensed with at this point.

The device for performing the method according to the invention is independent of the design of the control device.

The switch-off process of an IGBT high-current module 2 will first be explained in more detail with reference to the waveforms of collector-emitter voltage O _CE , collector current I _c and gate-emitter voltage U _GL of FIG. 1:

In order to be able to switch off an IGBT high-current module 2, the potential of the gate G must be discharged to the emitter potential. As a rule, the gate potential is applied to (opposite to the emitter) negative potential in order to counter interference. The gate G is discharged via a gate discharge resistor R _Gθ ff, which can also be the gate charge resistor Rαon. The discharge process begins at time t ₀ and initially falls to the Miller plateau U (time ti), which depends on the load current ι. is, from. The parasitic capacities are first reloaded here. The collector-emitter voltage U _CE rises at the time t- (Miller plateau). If the collector-emitter voltage U _{CF reaches} the value of the intermediate circuit voltage + U _Z (time t,). a freewheeling diode can take over the current from the IGBT high-current module 2 and the collector current I _c drops. At the same time, the gate voltage U _Gt drops - the current drop time can be influenced by a type of control (low or high discharge current of the control capacity) and ends at time t3. From this time t ₃ , only a tail current flows through the IGBT high-current module 2, which results from the stored charge of the component. In contrast to the previous phases, the control 4 has no influence on the tail current. During the current drop, the collector-emitter voltage U _CE at the IGBT high-current module 2 exceeds the intermediate circuit voltage + U _Z due to the stray inductance in the supply lines. The shutdown process can be changed by changing the

Value of the gate discharge resistance Raot t can be influenced.

A small resistance value means a large current flow out of the gate G of the IGBT high-current module 2, thus a faster recharging, a higher voltage rise rate and a higher current drop rate in the individual switching processes.

2 shows a block diagram of a first embodiment of a device for carrying out the method according to the invention. This device has a conventional control device 4, a device 14 for state detection of the collector-emitter voltage U _{CE of} the IGBT high-current module 2, a logic circuit 16 and two switchable devices 18 and 20 for generating two different ones

Discharge currents. The input 22 of the device 14 is connected to a collector terminal C of the power semiconductor switch 2 and its output 24 to a first input 26 of the logic circuit 16. At a second input 28 of this logic circuit 16 there is an off _signal S _AlJ ". The output 30 or 32 of the logic circuit 16 is connected to a control input 34 or 36 of the devices 18 or 20. The output of the device 18 or 20 is linked to the gate connection G of the power semiconductor switch 2 and the input thereof is connected to a signal output 38 or 40 of the control device 4. In addition, the apparatus of the gate terminal G is the power semiconductor switch 2 to a second input 42 of the means 14 of the collector-emitter voltage U _C F of the power semiconductor switch 2 is connected to the state detecting means of a broken line in this species. The connection of the potential profile of the gate-emitter voltage U _GE depends on the embodiment of the device 14.

3 shows a block diagram of a first embodiment of the device 14 in more detail. This em- direction 14 to the state detection of the collector-emitter voltage U _CE of the IGBT high-current module 2 comprises a voltage divider 44, a fast comparator 46, an adjustable Re ^¬ erenzspannungsquelle 48 and a monostable multivibrator 50. The voltage divider 44 is connected on the input side to the input 22 of the device 14 and on the output side to the non-inverting input of the comparator 46. The reference voltage source 48 is connected to the inverting input of this comparator 46. On the output side, the comparator 46 is connected to the output 24 of the device 14 via the monostable tilting stage 50. The output signal y of the fast comparator 46 changes from low to high as soon as the collector-emitter voltage U _{ct is} equal to the reference _voltage U _Eret . As a result, the monostable multivibrator 50 is started, so that the output signal S _Pu ι _{s of} the device 14 changes from low to high. As soon as the time of the monostable multivibrator 50 has expired, the output signal S _Pu ι _{s of} the device 14 changes back to low. The time of this monostable multivibrator 50 is set, for example, to a time which elapses if the maximum fall time were realized. For example, the voltage value of the intermediate circuit voltage + U _{Z is} selected as the reference voltage U _C Eret. The value can also be above or below an operational DC link voltage + U-. By choosing the reference voltage U _CE re> _d is in the regular

Fast operation and slow operation during increased intermediate circuit voltage.

In FIG 4 is an exemplary embodiment of the device 14 for the state _detection of the collector-emitter voltage O _Cι des

Power semiconductor switch 2 shown. This illustrated embodiment of the device 14 is designed as an analog circuit. As long as the collector-emitter voltage U _CE at the input 22 of the device 14 is less than the reference voltage U _CEr et _< , the voltage from the Zener diode Dl added. Exceeds the collector-emitter voltage

U _{CE is} the reference voltage U _C Eref so a current flows through the

Capacitor Cl and resistor Rl as long as the collector

Emitter voltage change rate is greater than zero. At the same time, capacitor C2 is quickly charged via diode D2. As soon as the voltage across the capacitor C2 is equal to the working gate-source voltage of the MOSFET T, this transistor T conducts and at the output 24 the device 14 changes the output signal S _Pu ι _B from 5 V to, for example, 0 V. If the rise is Collector-emitter voltage U _CE over, no more current flows through the capacitor Cl. The capacitor C2 is slowly discharged through the resistors R1 and R2. With the choice of the resistor R2, this discharge time constant and thus the pulse duration of the output signal S _Pu ι _s at the output 24 of the device 14 can be set. By means of the diode D4, the capacitor C1 can quickly discharge again when the power semiconductor switch 2 is switched on again. The output signal S _Pu ι _R must be inverted for further use or the outputs 30 and 32 of the logic circuit 16 must be interchanged.

5 shows a block diagram of the logic circuit 16 of the device according to FIG. 2. This logic circuit 16 has first and second AND gates 52 and 54 and first and second inverters 56 and 58. The output of the first inverter 56 is connected to an input of the first and second AND gates 52 and 54, respectively. The second input of the first AND gate 52 is linked to the first input 26 of the logic circuit 16, the output of this AND gate 52 being connected to the second output 32 of the logic circuit 16. The input of the second inverter 58 is also connected to the first input 26 of the logic circuit 16 connected and on the output side to a second input of the second AND gate 54, which is connected on the output side to the first output 30 of the logic circuit 16. The first inverter 56 is connected on the input side to the second input 28 of the logic circuit 16. By means of this logic circuit 16, the control signal S ^, _F for the first switchable device 18 changes from low to high as soon as the control signal S _{AUS changes} from high to low and the status signal S _Pu ι _{E is} low. The control signal S _T for the second switchable device 20 changes from low to high when the state signal S _P ui _alternates from low to high and the switch-off signal _S SAU is low. With this level change of the state signal S _[uls , the control signal S _{^ LF changes} from high to low.

6 shows a block diagram of a further embodiment of the device 14 for state detection of the collector-emitter voltage UCE of the power semiconductor switch 2. This embodiment of the device 14 differs from the embodiment of the device 14 according to FIG. 3 in that an evaluation device 60 is used instead of the monostable multivibrator 50. The first input 62 of this evaluation device 60 is connected to the output of the comparator 46 and the second input 64 connected to the second input 42 of the device 14, at which the gate emitter voltage U _GE is present. The gate-emitter voltage U _GE and the collector-emitter voltage U _{CE are} queried by means of this evaluation device 60.

FIG. 7 shows a block diagram of the evaluation device 60 in more detail. This evaluation device 60 has a comparator 66, a reference voltage source 68 and an AND gate 70. One input of the AND gate 70 is connected to the first input 62 of the evaluation device 60, at which the comparator signal y of the comparator 46 is connected Device 14 is pending. The second input of the AND gate 70 is connected to the output of the comparator 66, the non-inverting input of which is linked to the second input 64 of the evaluation device 60 and the reference voltage source 68 is connected to the inverting input.

The evaluation device 60 only delivers a signal when the collector-emitter voltage U _{CE is} greater than / equal to the reference voltage Ucref and the gate-emitter voltage U _{GE is} also _{greater than} / equal to a reference _voltage U _GEr p _f . The reference voltage UcEref indicates the reference value for the Miller plateau, which is known to be dependent on the collector current I _c . The reference voltage U _GF r _e f can also be below the Miller plateau (i.e. below the threshold voltage of the IGBT / type <5 V). Thus, at time t _? According to FIG. 1, the gate potential is only reduced with a reduced discharge current if, as a function of the gate-emitter voltage U _GE, it has been determined that there is an overload or short circuit. If the gate-emitter voltage UG _E remains below the reference voltage U _G ret, there is no overload or short circuit, so that the gate potential can be further reduced with an increased discharge current.

The switch-off process is thus optimized in such a way that the current drop speed is reduced only in the event of an overload or short circuit, so that the overvoltage is limited to acceptable values.

The switchable device 18 or 20 for generating a discharge current can be implemented in different ways. The simplest implementation is em switching off by means of a gate discharge resistor Rcoffi or R _Go tt2. The value of the gate discharge resistor Rc _{o can be selected as} the value of the switch-off resistance during conventional switching off. The value of the gate discharge resistor Rcoft is chosen so large that the shutdown process is continued only in a slow manner. These gate discharge resistors R _G offi and R _GO ft2 are each connected to a negative potential of the control device 4 by means of a switch, in particular a transistor.

Instead of switchable gate discharge resistors R _Got n and R _{Go £ f2} , two switchable voltage sources with the voltages U ₀ f-ι and U ₀ ff2 can also be used, which are connected to the gate connection G of the IGBT high-current module 2 via a gate discharge resistor are. The voltage U _{0tfι has} a small or negative value, so that the voltage drop across the gate discharge current U _{R is} large. The voltage U _0ff2 has a higher value, so that the voltage U _R becomes small. The voltage U ₀ ff ₂ may only be so high that the voltage U _R remains positive even at the lowest level of the Miller plateau, in order to prevent the gate G of the power semiconductor switch 2 from being recharged. The different voltage sources can be realized by different supply potentials.

Instead of switchable voltage sources, switchable current sources can also be used, with one current source supplying a discharge current for a quick shutdown and the other current source delivering a discharge current for a slow shutdown.

The method for optimizing the switch-off process of a non-latching, switchable power semiconductor switch 2 is described in more detail below with reference to the described device according to FIG. 2:

A switch-off signal SAUS is applied to the control device 4 of the IGBT high-current module 2 from a control set (not shown in more detail). This switch-off _signal S _{ΛU £} is thus with also on the logic circuit 16. This switch-off signal

S _AUS hits, for example, at time t ₀ em. At this time t ₀ , the collector-emitter voltage U _{CE is} equal to a saturation voltage which is dependent on the power semiconductor switch 2 and which is approximately zero in comparison to the intermediate circuit voltage + U _{7 of} the converter. As a result, the output signal Sp _u i _{s of} the device 14 for state detection of the collector-emitter voltage U _CE is in the low state. At the output 30 of the logic circuit 16, the control signal S _th , which represents the fast shutdown mode, is in the high state and the control signal SstsL, which represents the slow shutdown mode, is in the low state. The gate-emitter potential U _{Gi of} the IGBT high-current module 2 is thus lowered with the aid of a constant maximum permissible discharge current. During this reduction in the gate-emitter voltage U _GF , the collector-emitter voltage U _{CE increases} . From the signal curve of the collector-emitter voltage U _CE according to FIG. 1 it can be seen that this collector-emitter voltage U _CE begins to rise precisely when the gate-emitter voltage U _{GE is} equal to the Miller plateau. As long as the collector-emitter voltage U _{E is} not equal to the reference voltage Uc _Er et, the device 18 for generating a discharge current for the fast shutdown mode remains switched on. As soon as the collector-emitter voltage U _{CL is} equal to or greater than the reference voltage U _C Eret, for example equal to the intermediate circuit voltage + U ₂ (time t _? ), The output signal S _Pu ι _{s of} the device 14 changes from low to high, so that the control signal S _S tF at output 30 of logic circuit 16 changes from high to low and the control signal S _S rsι at output of logic circuit 16 changes from low to high. As a result, during the switch-off process, the delay is switched from the fast switch-off mode to the slow switch-off mode. The gate-emitter voltage U _GE is reduced with a smaller discharge current from time t ₂ . The level of this discharge current depends on the permissible reverse voltage at the power semiconductor switch 2, which may occur without to damage it. At time t-, the collector current is

Ic already lowered so much that from this time t ₃ only the tail current resulting from the stored charge of the component flows. The switch-off process is ended at time t ₄ , since then the collector current I _c and the gate-emitter voltage U _{GE are} equal to zero and the collector-emitter voltage U _C E is equal to the intermediate circuit voltage + U ₇ . is. So that the power semiconductor switch 2 does not switch itself on again due to interference, it is advisable to set the gate emitter voltage U _GE to a negative potential, for example -5 V, this not in the time profile of the gate emitter voltage U _{GE is shown in} FIG 1. The output signal S ^ ui _ε changes after the time set in the monostable multivibrator 50 (> t ₄ max) from the high state to the low state, so that the device 18 for the fast shutdown mode is switched on again. If these devices 18 and 20 are realized by means of gate discharge resistors R _GoEU and R _Go πz, then the gate connection G of the IGBT high-current module 2 is connected to a negative potential with a low resistance after the time of the monostable multivibrator 50.

If the device 14 for status detection of the collector-emitter voltage U _{CE is} also supplied with the gate-emitter voltage U _GE , it is possible to prevent the switchover from the fast switch-off mode to the slow switch-off mode. That means that this switchover is only carried out if the gate-emitter voltage U _{CE is} greater than / equal to a reference _voltage U _GEr e £ which specifies a threshold value for the Miller plateau. Since the height of the Miller plateau depends on the collector current I _c , the height of the Miller plateau is an indication of normal operation or overload or short-circuit operation of the power semiconductor switch 2. Only when the overload or short-circuit operation is recognized is switched from the fast shutdown mode without delay to the slow shutdown mode.

Thus, with the method according to the invention, a switch-off process can be optimized with little effort to the effect that when non-latching, switchable power semiconductor switches 2 are used in hard-switching converters, whose switching times should be as short as possible, regardless of the operating state of this power semiconductor switch 2, the Verkuppelung of voltage increase and current is llezeit separately and independently depending on the operating state of the power semiconductor switch 2 is controlled from each other ^¬ the.

8 shows a second embodiment of the device for carrying out the method according to the invention. This embodiment of the device differs from the embodiment of the device according to FIG. 2 in that instead of the device 14, the logic circuit 16 and the switchable devices 18 and 20, a ramp generator 72, a changeover switch 74 and a sequence control 76 are provided. The ramp generator 72 has its output side connected to an input of the change-over switch 74, whose other input is connected to a first output ^'10 of the driving device. 4 The output of this switch 74 is linked to the gate connection G of the IGBT high-current module 2. The second output 12 of the control device 4 is connected to the emitter control gear E _{st of} the IGBT high-current module 2. The switch 78 of this switch 74 is controlled by the sequence controller 76. This sequence control 76 is connected on the input side to the collector connection C of the IGBT high-current module 2. In addition, this sequence control 76 is supplied with the switch-off signal S _Aus . Depending on the state of the collector-emitter voltage U _CE during the shutdown process Control signal Sum generates that the switch 78 of the switch 74 controls during the shutdown process.

With the arrival of the switch-off signal S _A "4, at the control device 4 and the sequence control 76, on the one hand the gate discharge resistor R _G ci ι is connected in the control device 4 by means of a transistor of the push-pull stage to the negative potential of -5 V and on the other hand the switch 78 of the changeover switch 74 is controlled by the sequence control 76 such that the ramp generator 72 is connected to the gate connection G of the IGBT high-current module 2. As a result, the gate G is discharged by means of the ramp generator 72. As soon as the collector-emitter voltage U _ΓE increases (time t _t of FIG 1), the control signal S changes _to the state control 76, whereby the switch 78 of the switch 74 is flipped, so that the gate G of the IGBT high-current module 2 with the Gate discharge resistor R _θ ( _{f is} connected. This is stopped by switching off the ramp generator 72 from the gate terminal G. The gate G of the IGBT high-current module 2 is now rapidly discharged via the gate discharge resistor R _Co tt. During this rapid discharge The gate-emitter voltage Ui rises in the gate G. If this collector-emitter voltage U _{CF is} equal to / greater than the reference voltage U _C Er._f, the control signal Su "of the sequence controller 76 changes its state again, as a result of which the switch 78 of the changeover switch 74 is switched over again so that the gate G is again discharged with a set steepness in a controlled manner via the ramp generator 72. As soon as the collector current I is zero and the co If the emitter voltage UΓ _{E is} equal to the intermediate circuit voltage + U _Z (time t ₄ according to FIG. 1), the control signal S _{Ur changes} its state again and now connects the gate G to the gate discharge resistor Rcott, so that the gate G of the power semiconductor switch 2 is connected with low resistance to the negative potential. This embodiment of the device, also referred to as a memory circuit, has the advantage over the embodiment of the device according to FIG. 2 that at the beginning of the switch-off process the gate G of the power semiconductor switch 2 is discharged with the same steepness as in the period t ₄ - t ₂ , m which is the collector-emitter voltage U _CE greater than / equal to the reference voltage U _Cir , r. This measure is particularly noticeable in the event of a short circuit.

9 shows a third embodiment of the device for carrying out the method according to the invention. Compared to the second embodiment in accordance with FIG. 8, three em / off switches 80, 82 and 84 are provided instead of the switch 74. The actuation events of these on / off switches 80, 82 and 84 are each connected to a control output of the sequence control 76. The on / off switch 80 connects the output 10 of the control device 4 to the gate connection G, the em / off switch 84 connecting the gate connection G of the IGBT high-current module 2 to an input 86 of the ramp generator 72 and the em- / Off switch 82 connects the output 88 of the ramp generator 72 to the gate terminal G. The ramp generator 72 can optionally control the gate-emitter voltage U _GE (em / off switch 82 closed) or track the value of the potential at gate G (em / off switch 84 closed) by means of the em / off switches 82 and 84. In the time interval [t ₀ , t _? ], the on / off switches 80 and 84 are closed, as a result of which the gate G is quickly discharged by means of the gate discharge resistor Rctt of the control device 4 and the value of the ramp generator 72 is tracked to the value of the potential of the gate G. At the time of the switchover (time t according to FIG. 1), the on / off switch 82 is closed and the on / off switches 80 and 84 are opened. At this changeover time t ₂ , the ramp generator 72 has exactly the value of the gate voltage. Then the gate G unloaded by means of the ramp generator 72 with the set slope.

The advantage of this third embodiment of the device over the second embodiment according to FIG. 8 (memory circuit) is that it is ensured that the gate G and the ramp generator 72 have the same voltage value at the changeover time t. In the so-called memory circuit, problems due to leakage currents can occur during the time interval [ti, t _? ], while the gate voltage is equal to the Miller plateau voltage.

Claims

claims

1. Method for optimizing the switch-off process of a non-latching, switchable power semiconductor switch (2) m a hard-switching converter, with the arrival of a switch-off signal (S _A us) de gate-emitter voltage (U _E ) of this power semiconductor switch (2) are lowered with the aid of a maximum permissible discharge current and its collector-emitter voltage (U _C E) is exceeded when a reference value (U _C Lre £) is exceeded, the value of which is set such that the collector current (I ₀ ) begins to commutate, monitored and wherein when this reference value (U _{ctI t} ) is reached, the discharge current is reduced to a value which is less than the value of the maximum permissible discharge current.

2. The method according to claim 1, wherein the gate-emitter voltage (UG _E ) of the power semiconductor switch (2) is lowered at the beginning of the switch-off process with the aid of a constantly reduced discharge current until the collector-emitter voltage (U _CE ) of the power semiconductor switch (2 ) increases.

3. The method according to claim 1 and 2, wherein the values of the constant reduced discharge current at the beginning and at the end of the switching-off process of the power semiconductor switch (2) are the same.

4. Device for performing the method according to claim 1 with a control device (4), the signal output (10) with a gate terminal (G) and the reference output (12) with an emitter control input (E.- _r ) a non-latching, switchable power semiconductor switch (2) of a hard-switching converter are connected, a control signal (S _Alls ) being present at the input of the control device (4), a device (14) for detecting the condition of the collector-emitter voltage (U _C E ) on the receiving side with a Collector connection (C) of the power semiconductor switch (2) and the output side is connected to a first input (26) of a logic circuit (16), at whose second input (28) the control signal (S _off ) is present and that two switchable on - directions (18, 20) are provided for generating two different discharge currents, the control inputs (34, 36) of which are each connected to an output (30, 32) of the logic circuit (16), the outputs of the devices (18, 20) with the gate terminal (G) of the power semiconductor switch (2) and its inputs are linked to the signal output (38, 40) of the control device (4).

5. Device for carrying out the method according to claims 1 and 2 with a control device (4), the signal output (10) with a gate connection (G) and the reference output (12) with an emitter control output (E _{^ r} ) a non-latching, turn-off power semiconductor switch (2) of a hard-switching converter are connected, at the input of the control device (4) e control signal (S _A us) is present, characterized in that a ramp generator (72) is provided which the output side is linked to an input of a change-over switch (74), the other input of which is connected to the signal output (10) of the control device (4) and whose output is connected to the gate connection (G) of the power semiconductor switch (2) and that a sequence control (76) is provided, which is linked on the output side to the collector connection (C) of the power semiconductor switch (2) and on the output side to the switch (78) of the changeover switch (74), this discharge fcontrol (76) the switch-off signal (S _{Au is} supplied.

6. The device according to claim 4, wherein the device (14) for _detecting the state of the collector-emitter voltage (U _ΓF ) is connected on the input side to the gate terminal (G) of the power semiconductor switch (2).

7. The device according to claim 5, wherein instead of the switch (74) three on / off switches (80,82,84) are provided, the actuating inputs of which are connected to the sequence control (76), and wherein the third switch (84) is the gate - Connection (G) of the power semiconductor switch (2) with an input (86) of the ramp generator (72) connects.

8. The device according to claim 4, wherein the device (14) for detecting the condition of the collector-emitter voltage (U _CE ) of the power semiconductor switch (2) on the input side a voltage divider (44) with a comparator (46), an adjustable reference voltage source (48) and has a monostable multivibrator (50) on the output side, this monostable multivibrator (50) is connected on the input side to the output of the comparator (46) and the reference voltage source (48) is connected between the inverting input of the comparator (46) and a reference potential.

9. The device according to claim 4 and 6, wherein the device (14) for detecting the state of the collector-emitter voltage (UC _E ) of the power semiconductor switch (2) on the input side of a voltage divider (44) with a comparator connected downstream

(46), an adjustable reference voltage source (48) and an evaluation device (60) on the output side, this evaluation device (60) on the input side on the one hand with the gate connection (G) of the power semiconductor switch (2) and on the other hand with the output of the comparator ( 46) is connected and the reference voltage source (48) is connected between the inverting input of the comparator (46) and a reference potential.

10. The apparatus of claim 4, wherein the logic circuit (16) comprises first and second AND gates (52, 54) and first and second inverters (56, 58), the output of the first inverter (56) each having one Input of the two AND gates (52, 54) is linked, the output of the second inverter (58) being connected to a second input of the second AND gate (54), the input of the second inverter (58) being connected on the one hand to a second input of the first AND gate (52) and on the other hand is linked to an input (26) of the logic circuit (16) at which the output signal (S _Pul .) of the device (14) for status detection is present, the Input of the first inverter (56) is connected to a second input (28) of the logic circuit (16) at which the control signal (S _Au ) is present and the outputs of the AND gates (52, 54) are connected to a control Output (32,30) of the logic circuit (16) connected

11. The device according to claim 9, wherein the evaluation circuit (60) has a comparator (66), an adjustable reference voltage source (68) and an AND gate (70), this AND gate (70) on the output side with the output of the evaluation circuit ( 60) and on the input side is connected on the one hand to the comparator (66) and on the other hand to an input (62) of the evaluation circuit (60), at which an e comparator signal (y _ce ) is present, the reference voltage source (68) between the inverting input of the comparator ( 66) and a reference potential, and wherein the non-inverting input of the comparator (66) is linked to a second input (64) of the evaluation circuit (60) at which the gate-emitter voltage (U _G ι) of the power semiconductor switch (2) is pending.

12. The device according to claim 4, wherein as switchable devices (18, 20) each switchable resistor is provided .

13. The apparatus according to claim 4, wherein a switchable voltage source is provided as switchable devices (18, 20).

14. The apparatus of claim 4, wherein a switchable current source is provided as switchable devices (18, 20).