CN1234146A - Process and device for optimizing power-down cycle of a non-engaging, interruptable power semiconductor switch - Google Patents
Process and device for optimizing power-down cycle of a non-engaging, interruptable power semiconductor switch Download PDFInfo
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- CN1234146A CN1234146A CN 97199012 CN97199012A CN1234146A CN 1234146 A CN1234146 A CN 1234146A CN 97199012 CN97199012 CN 97199012 CN 97199012 A CN97199012 A CN 97199012A CN 1234146 A CN1234146 A CN 1234146A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
- H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
- H03K17/166—Soft switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
Abstract
This invention concerns a process for optimizing the power-down cycle of a non-engaging, interruptable power semiconductor switch(2)in a saturating power converter and a device for carrying out the process. According to the invention, when the interrupt signal(Saus)arrives, the gate emitter voltage(UGE)of this power-semiconductor switch(2)lowered with the help of a maximally permissible discharge current and its collector-emitter voltage(UCE)are monitored against exceeding a reference voltage(UCEref), the value of which is set so that the collector current(IC)begins to commutate, and upon reaching the reference value(UCEref), the discharge current is reduced to a value which is below the value of the maximum permissible discharge current. Thus, the power-down cycle of a non-engaging, interruptable power semiconductor switch(2)is largely optimized, so that the voltage rise and current drop times can be separately controlled.
Description
A kind of device that the present invention relates to a kind of method and carry out this method, this method are used for optimizing the cutting-off process at a nonlocking can-cut power semiconductor switch of a hard switching formula current transformer.
Non-locking power semiconductor switch is meant such semiconductor device, in their control input end one control signal must be arranged all the time, makes them be in conducting state like this.Belong to an ambipolar high power transistor of having of nonlocking can-cut power semiconductor switch (LTR) and a can-cut semiconductor subassembly of control.The can-cut semiconductor subassembly of this control for example has self-locking field-effect transistor (MOS-FET), insulated gate bipolar transistor (IGBT), field controlled thyristor also to claim the thyristor (MCT) of MOS controller ...
To having the power semiconductor switch of MOS control input, its developing direction is the high current-carrying capacity towards module always.Can obtain high current module at present, they can conduct the drain current of a 1200A during for 1700V at locking function.Raising along with ampacity, electric current changes velocity amplitude (di/dt) and also greatly improves thereupon, especially when module is cut off, since module separately with a control device and an intermediate circuit electrical communication, cause in switching process inductance by the power section of current transformer on insulated gate bipolar transistor, produce usually rich can overvoltage.
Only produce switching losses seldom when using nonlocking can-cut power semiconductor in the hard switching current transformer, should lack switching time as far as possible.This point but be by the leakage inductance of structure regulation and when cutting off determined overvoltage limited.In routine control, be to adjust with the control voltage magnitude that respectively applies and the resistance of a subordinate switching time.Then in a kind of like this control circuit, in the cutting-off process to a kind of like this power semiconductor switch, the voltage time that raises connected each other with the electric current reduction time is in the same place by component capabilities.
Raising along with the withstand voltage and anti-intensity of flow of nonlocking can-cut power semiconductor switch, control to transient process also becomes important, raises with the rising of letter voltage change speed (du/dt) with intermediate circuit voltage with outage stream to be cut because electric current changes speed (di/dt).Change in voltage speed should not surpass the determined value of manufacturer, and the locking that can avoid producing power semiconductor switch when cutting off circuit like this, overvoltage depend on that leakage inductance and the electric current in the circuit changes speed.Especially can under short-circuit conditions, reduce overvoltage by reducing electric current change speed.
There is a kind of being used for when cut-out has the power semiconductor switch of MOS control input, to limit the method and apparatus that electric current underspeeds from patent documentation EP0645889A1 is known.In the method, when cutting off, produce a reverse voltage according to an inductance, this voltage is fed the grid-emitter voltage to the power semiconductor switch, by this feedback, this grid-emitter voltage is enhanced, can reduce cut-off velocity without delay effectively like this, simultaneously the waiting time of amplifying power semiconductor switch or influence conducting state not.This negative feedback especially very high negative current climbing occurring, for example becomes strong especially when overcurrent or short circuit current.Electric current changes velocity amplitude and is adjusted with can being independent of specified operation or short circuit operation.Change velocity amplitude for regulating reverse voltage and also regulating electric current thus, can change the value of inductance.But the low inductive structure of a current transformer thereby only change in close limit are considered very much in the change of inductance value.
Known a kind of protective circuit that is used for power semiconductor switch from patent documentation EP0361211B1, this circuit have one have the monitoring of collector electrode-emitter and base-emitter monitoring and one or the load current supervisory circuit and one first and second negative current source or one first and second of door can insert the grid discharge resistance.The load current supervisory circuit is connected with a control element at output, and this element can insert the grid discharge resistance with second negative current source or second again at output and be connected.The load current supervisory circuit determines whether power semiconductor switch is in specified operation or short circuit operation state, is the rupturing duty semiconductor switch in view of the above, activates first negative current source or activates second negative current source.Can stop like this that power semiconductor switch is eliminated rigidly under short-circuit conditions.Can cause blockage effect like this, power transistor can be lost its cut-out ability thus.Because available one less removing electric current comes the rupturing duty transistor under short-circuit conditions, so the maximum short-circuit strength of power transistor also is used under short-circuit conditions.
The byliner of publication be the article " igbt at overcurrent and short circuit current time cut-out optimization in Properties " (" Optimization of the Turn-Off Performanceof IGBT at Overcurrent and Shorr-Circuit Current " of H.-G.Eckel and L.Sack on the 317th～322 page of procceedings EPE ' 93 second volume of publishing on September 13rd～16,1993, von H.-G.Eckel undL.Sack, Konferenzband EPE ' 93, Vol.2,13.～16, September 1993, Seiten 317～322) in the literary composition, introduced two kinds of cut-out strategies that are used at the igbt of a hard switching current transformer.Two grid discharge resistances in two kinds of strategies, have all been used.Cut off in the strategy at first kind, the decline of grid-emitter voltage is at first begun by low grid discharge resistance, the then monitored reference voltage that whether surpasses an about 10V of collector emitter voltage.After predetermined time of delay, if collector emitter voltage greater than/equal reference voltage, then grid-emitter voltage reduces with high grid discharge resistance, till power semiconductor switch is by locking.This twin-stage grid control mode requires accurately to know the dynamic property of igbt, if do not know this point, then the first grid discharge resistance should be selected as far as possible for a short time, and should elect as time of delay should be big as far as possible greater than the rate of climb of collector emitter voltage and second grid discharge resistance.
In second cut-out strategy of being introduced, grid-emitter voltage is reduced with a feature grid discharge resistance, until Miller level ground (Miller-Plateau) state that reaches grid-emitter voltage.When grid-emitter voltage equaled the Miller level ground, collector emitter voltage raise.In case collector emitter voltage surpasses a reference value such as 10V, then a grid-emitter voltage and a reference value compare.When low collector current, the Miller level ground is also lower, and the first grid discharge resistance is used in whole cutting-off process like this.When high collector current, the Miller level ground of grid-emitter voltage is also high.In this case after predetermined time of delay, the first grid discharge resistance is cut off and a bigger grid discharge resistance is switched on.When using this second cut-out strategy, the Miller level ground need be accurately known, so just this strategy can be implemented.
Two disadvantage of cutting off strategy of this that introduced are the exact relationships that must know between Miller level ground and collector current.And this is different for different igbts, and must mate time of delay with each igbt, because can cause unwanted too high loss a too short time of delay, then mean oversize time of delay too slow ON Action and thus the raising of the resistance of grid discharge resistance no longer expressed any effect.
The purpose of this invention is to provide a kind of method and apparatus, be used for optimizing the cutting-off process of the nonlocking can-cut power semiconductor switch in a hard switching formula current transformer, wherein a kind of simple working mode and minimum and simply can measure measurement parameter and occupy preferential status.
The objective of the invention is to realize by claim 1 described feature,
Can realize with this method: can be separately the voltage gradient and the current gradient of the cutting-off process of a nonlocking can-cut power semiconductor switch be exerted one's influence.Will use different discharging currents, these electric currents will be selected according to the state of the collector emitter voltage of power semiconductor switch for this reason.When cutting-off process begins, can adjust discharging current like this, make the voltage that maximum admissible power semiconductor switch occurs change speed.In case collector emitter voltage reaches a predetermined reference voltage value, discharging current just is reduced to one than low value.This discharge current value that is lowered depends on overvoltage value, and maximum can appear in this overvoltage value.Reference voltage level equals collector current when beginning to commutate required magnitude of voltage.That is: reference voltage level equals the value of intermediate circuit voltage in a current transformer.
The advantage of the inventive method is: for a discharging current is transformed into the dynamic characteristic that no longer needs accurately to understand power semiconductor switch on another discharging current, because this conversion is only just carried out during a required reference voltage level when collector emitter voltage arrives collector current and begins to commutate.Then must only a collector emitter voltage and a corresponding reference voltage level be made comparisons for recording this transfer point.By with voltage rise time and downslope time decoupling zero, can be accomplished the switching time of the nonlocking can-cut power semiconductor switch in a hard switching formula current transformer the shortlyest, reach little switching losses thus.
In a kind of the method according to this invention with advantage, grid-the emitter voltage of power semiconductor switch just reduces with the discharging current of a constant reduction at the beginning from cutting-off process, till the collector emitter voltage of power semiconductor switch raises.This slow shutoff that begins just to take place from cutting-off process has special superiority under short-circuit conditions.
A kind of device that is used to carry out the inventive method uses a common control device to be used for a nonlocking can-cut power semiconductor switch, but this device is expanded to a kind of and is used for the device that access device that collector emitter voltage, a logical circuit to power semiconductor switch and two are used to produce two different discharging currents obtains as state, but wherein logical circuit should access device in cutting-off process according to the state Be Controlled of collector emitter voltage.But be used to produce the access device of a high discharging current because a kind of common control device has had one, but the access device that therefore is used to produce a high discharging current is unnecessary mostly.Available like this attachment device is seldom revised a kind of common control device, and the cutting-off process that makes this be used for a nonlocking can-cut power semiconductor switch is optimised.
Have in the device of advantage one, but replace this logical circuit with in order to produce the access device of different discharging currents, be provided with a ramp signal generator, it is connected with the gate terminal of power semiconductor switch with a change over switch, and wherein change over switch is provided with a program control.Can obtain like this a kind of of a general control device especially simply revised, can do optimization process to cutting-off process thus.
Have in the device of advantage at another, replace this change over switch but to use three switches, its operation input links to each other with program control, and wherein the 3rd switch imported the gate terminal of power semiconductor switch and be connected with one of ramp signal generator.This circuit types is than the advantage of the circuit types that also is referred to as memory circuit with ramp signal generator and change over switch: can guarantee that grid constantly has the value that equates by program control with the ramp signal generator in conversion.Can be in this memory circuit owing to the leakage current generating problem, and the grid potential of power semiconductor switch equals the Miller level ground.
Can be with reference to the following drawings for further specifying the present invention, be used to carry out embodiment shown in it according to the device of the method for the cutting-off process that is used to optimize a nonlocking can-cut power semiconductor switch of the present invention.
Fig. 1 is illustrated in the process over time of collector emitter voltage, collector current and the grid-emitter voltage of an igbt in the cut-out process respectively in a figure,
Fig. 2 illustrates the calcspar of first form of implementation of the device that is used to implement the inventive method,
Fig. 3 illustrates the calcspar of device of the state of the collector emitter voltage that is used to obtain device shown in Figure 2,
Fig. 4 illustrates the embodiment of device of the state of the collector emitter voltage that is used to obtain device shown in Figure 2,
Fig. 5 illustrates a calcspar of the logical circuit of device shown in Figure 2,
Fig. 6 illustrates the calcspar of device of the state of another collector emitter voltage that is used to obtain device shown in Figure 2,
Fig. 7 illustrate this another be used to obtain the calcspar of evaluation device of the device of collector emitter voltage state shown in Figure 6,
Fig. 8 illustrates the calcspar of another form of implementation of the device that is used to carry out the inventive method,
Fig. 9 illustrates a calcspar of the 3rd form of implementation of the device that is used to carry out the inventive method.
The method and apparatus that is used for optimizing a kind of cutting-off process of nonlocking can-cut power semiconductor switch is that to have the high current module of the igbt of a general control device 42 at above-mentioned accompanying drawing with one illustrational, and wherein the high current module 2 of this igbt draws with thick line for identification better.The collector terminal C of the high current module 2 of igbt is received on the forward intermediate circuit bus 6, and this intermediate circuit bus provides a forward intermediate circuit voltage+Uz.Emitter terminal E is on the one hand with an alternating current terminal 8, link to each other with another collector terminal C with high current module of igbt of a control device on the other hand, and this control device is not shown specifically among the figure for simplicity's sake.Two outputs 10 and 12 of control device 4 are imported E with the gate terminal G and the emitter control of the high current module 2 of this igbt respectively
StBe connected.
The signature of publishing on German journals " Elektronik " the 24th volume (nineteen ninety) 62-67 page or leaf is W.Boesterling, the article of W.Keuter and M.Tscharn " the power control of optimization " (" OptimierteLeistungssteuerung ", W.Boesterling, W.Keuter und M.Tscharn, DE-Zeitschrift " Elektronik ", Band 24,1990, Seiten 62-67) describes the different control device that are used for insulated gate bipolar transistor module in detail, just can save these contents so in this article.The structure that is used to carry out the device of the inventive method and control device is irrelevant.
Collector emitter voltage U according to Fig. 1
CE, collector current I
CAnd grid-emitter voltage U
GESignal process the cutting-off process of the high current module 2 of igbt then should at first be described.
For cutting off the high current module 2 of an igbt, the current potential of grid G must be discharged to till the emitter current potential.Generally grid potential is placed on (with respect to emitter) negative potential and disturbs to eliminate.The discharge of grid G is through a grid discharge resistance R
GoffCarry out, this discharge resistance also can be charging resistor R simultaneously
GonDischarge process is at moment t
0Beginning and reduce to Miller level ground U earlier
p(moment t
1), Miller level ground U
pDepend on load current i
LHere at first parasitic capacitance is recharged.Collector emitter voltage U
CEAt moment t
1Rise on (Miller level ground).As collector emitter voltage U
CEReach intermediate circuit voltage+U
ZValue the time (t constantly
2), then a free wheeling diode is accepted electric current and collector current I from the high current module 2 of igbt
CDescend.While grid-emitter voltage U
GEAlso descend.Downslope time can be influenced and at moment t by a kind of control (control capacitance less or big discharging current)
3Stop.From this moment t
3What begin to flow through the high current module 2 of this igbt only is the tail current (Tailstrom) that results from the parts stored charge.Opposite with aforementioned stages, can not exert one's influence to tail current by controller 4.When electric current descended, the collector emitter voltage UCE on the high current module 2 of igbt had surpassed by the determined intermediate circuit voltage+U of the leakage inductance in the feed line
ZCan be by changing the value R of grid discharge resistance
GoffInfluence cutting-off process.Little resistance value means a big current affects from the grid G of the high current module 2 of igbt, so also just means charging, the higher voltage rate of climb and higher electric current decrease speed faster in the single switch process.
Fig. 2 illustrates a calcspar of first form of implementation that is used to carry out the device of the inventive method.The control device 4, one that this device has a routine is used to obtain the collector emitter voltage U of the high current module 2 of igbt
CEBut the device 14 of state, a logical circuit 16 and two access devices 18 and 20 that are used to produce different discharging currents.Device 14 input 22 its output 24 that links to each other with a collector terminal C of power semiconductor switch 2 is then imported 26 with one first of logical circuit 16 and is connected.One second input 28 at this logical circuit 16 has a shutoff signal S
AusThe output 30 of logical circuit 16 or 32 is connected with a control input 34 or 36 of device 18 or 20. Device 18 or 20 output its input that then links to each other with the gate terminal G of power semiconductor switch 2 is then exported 38 or 40 with a signal of control device 4 and is linked to each other.In this external this device, the gate terminal G of power semiconductor switch 2 links to each other through second input 42 of a dotted line with the device 14 of the collector emitter voltage UCE state that is used to obtain power semiconductor switch 2.Grid-emitter voltage U
GEThe connection of current potential process depend on the form of implementation of device 14.
A calcspar of one first form of implementation of device 14 shown in Fig. 3.This is used to obtain the collector emitter voltage U of the high current module 2 of igbt
CEThe device 14 of state has a voltage divider 44, one quick comparator 46, one an adjustable reference voltage source 48 and a monostable trigger 50.Voltage divider 44 inputs link to each other with the input 22 of device 14, and output links to each other with the non-inverting input of comparator 46.Reference voltage source 48 is received the inverting input of this comparator 46.Link to each other through the output 24 of monostable trigger 50 at this comparator 46 of output with device 14.In case collector emitter voltage U
CEEqual reference voltage U
CEref, the output signal Y of quick comparator 46
CEJust uprise from low.So just, can start this monostable trigger 50, the output signal S of this sampling device 14
PulsFrom the low height that becomes.In case the operation of the time of monostable trigger 50 finishes, the output signal S of device 14
PulsAgain step-down.The time of this monostable trigger 50 for example can transfer to one and can realize the maximum current time of fall time.As the reference voltage U
CErefFor example can select intermediate circuit voltage+U
ZMagnitude of voltage.This reference voltage level also can be higher or lower than the one intermediate circuit voltage+U that meets service conditions
ZBy selecting reference voltage U
CEref＞U
d, then can be when operate as normal switch switch lentamente then when the intermediate circuit voltage of rising is arranged apace.
Be used to obtain the collector emitter voltage U of power semiconductor switch 2 shown in Fig. 4
CEOne embodiment of the device 14 of state.The diagram form of implementation of this device 14 is to be designed to the analog circuit form.As long as the collector emitter voltage U on the input 22 of device 14
CELess than reference voltage U
CEref, then this voltage is received by Zener diode D1.If collector emitter voltage U
CESurpass reference voltage U
CEref, an electric current flow through capacitor C 1 and resistance R 1 are then arranged, as long as collector emitter voltage changes speed greater than zero.Simultaneously capacitor C2 is charged rapidly through diode D2, in case the voltage on the capacitor C2 equals the work gate source voltage of metal-oxide-semiconductor field effect transistor T, this transistor T conducting and on output 24 device 14 with output signal S
PulsChange over such as 0V from 5V.If collector emitter voltage U
CERising termination after, then no longer include electric current and flow through capacitor C1.Capacitor C 2 is slowly discharged through resistance R 1 and R2.By selecting the resistance R 2 can be to discharge time constant and therefore also can be to installing the output signal S on 14 the output 24
PulsPulse duration regulate.Make capacitor C1 repid discharge again in the next one connection process of power semiconductor switch 2 with diode D4.Output signal S
PulsMust must be exchanged with the output 30 and 32 of making further application or logical circuit 16 by anti-phase.
Fig. 5 illustrates the calcspar according to the logical circuit 16 of the device of Fig. 2.This logical circuit 16 have one first and second with the door 52 and 54 and 1 first and second inverter 56 and 58.The output of first inverter 56 respectively with first and second with door 52 with 54 one the input link to each other.First imports 26 with second input of door 52 with first of logical circuit 16 links to each other, and wherein should be connected with second output 32 of logical circuit 16 with the output of door 52.The input of second inverter 58 links to each other with first input 26 of logical circuit 16 equally and links to each other with one second input of door 54 with second at output, should then link to each other with first output 30 of logical circuit 16 with the output of door 54.First inverter 56 links to each other with second input 28 of logical circuit 16 at input.Working as control signal S with this logical circuit 16
AusFrom hypermutation is low and status signal S
PulsWhen low, but be used for the control signal S of first access device 18
StFThen by the low height that becomes.And as status signal S
PulsBy low height and the shutoff signal S of becoming
AusWhen low, but be used for the control signal S of second access device 20
StsLThen by the low height that becomes.Use status signal S
PulsThis level change and make control signal S
StfBy hypermutation is low.
Be used to obtain the collector emitter voltage U of power semiconductor switch 2 shown in Fig. 6
CEOne calcspar of another form of implementation of the device 14 of state.Device this form of implementation of 14 is with difference according to the form of implementation of the device 14 of Fig. 3: substitute monostable trigger 50 and adopted an evaluation device 60.First input 62 of this evaluation device 60 link to each other with the output of comparator 46 second input 64 then with install 14 second import 42 and be connected, grid-emitter voltage U is arranged in this input 42
GECome grid-emitter voltage U with this evaluation device 60
GEAnd collector emitter voltage U
CEInquire.
Be shown specifically a calcspar of evaluation circuit 60 among Fig. 7.This evaluation circuit 60 has a comparator 66, a ginseng piezoelectricity potential source 68 and one and 70.Link to each other with the first input end 62 of evaluation circuit 60 with an input of door 70, on this input, be added with the comparator signal Y of the comparator 46 of device 14
CELink to each other with the output of comparator 66 with second input of door 70, the noninverting input of this comparator 66 links to each other with second input 64 of evaluation circuit 60 and is connected with reference voltage source 68 at inverting input.
As collector emitter voltage U
CEGreater than/equal reference voltage U
CErefAnd grid-emitter voltage U
GEAlso greater than/equal a reference voltage U
GErefThe time, evaluation device 60 just only provides a signal.Reference voltage U
GErefProvide the reference value that is used for the Miller level ground, this Miller level ground is known to be to depend on collector current I
C.Reference voltage U
GErefAlso can be lower than the Miller level ground and (that is be lower than the threshold voltage of igbt/model＜5V.Work as according to grid-emitter voltage U like this
GEWhen having determined to have an overload or short-circuit conditions, at moment t
2, grid potential shown in Figure 1 only descends with the discharging current that reduces.If grid-emitter voltage U
GEKeep below reference voltage U
GEref, any overload or short-circuit conditions then do not take place, grid potential can further descend with the discharging current that improves like this.
Like this cutting-off process is done following optimization, only make that the electric current decrease speed just reduces under overload or short-circuit conditions, overvoltage just is limited on the typical value like this.
But the access device 18 or 20 that is used to produce a discharging current can be realized by different way.The simplest implementation is by a grid discharge resistance R
Goff1Open circuit.This grid discharge resistance R thus
Goff1Value when doing common cut off, be chosen as the value of breaking resistor.Grid discharge resistance R
Goff2Its size of value may be selected to that making opens circuit only continues with a kind of methods slowly.This grid discharge resistance R
Goff1And R
Goff2Respectively hang oneself a switch especially a negative potential of a transistor AND gate control device 4 link to each other.
Substitute and to insert grid discharge resistance R
Goff1And R
Goff2, also can use and have voltage U
Off1And U
Off2All right one way or the other access voltage source, they link to each other through the gate terminal G of a grid discharge resistance with the high current module 2 of igbt.In this this voltage U
Off1Have a little or negative value, drop on the voltage U on the gate discharge current like this
RJust big.Voltage U
Off2Have higher value, a voltage U like this
RJust little.Voltage U
Off2Only allow greatly, make voltage U when the minimum level on Miller level ground to certain degree
RStill just remain, the grid G of power semiconductor switch 2 is recharged so that prevent.Different voltage sources can be realized by different power supply potentials.
Substitute and can insert voltage source and also can adopt and can insert current source, one of them current source is provided for a discharging current of quicking break, and another current source then is provided for a discharging current that slowly opens circuit.
According to described device as shown in Figure 2, below the method for the cutting-off process that is used to optimize a nonlocking can-cut power semiconductor switch 2 is described in more detail.
The shutoff signal S that the control device of not representing in detail from a figure comes
AusBe added on the control device 4 of the high current module 2 of igbt.This shutoff signal S
AusTherefore also be positioned on the logical circuit 16.This shutoff signal S
AusAt moment t
0In time, arrive.At this moment t
0, collector emitter voltage U
CEEqual a saturation voltage that depends on power semiconductor switch 2, the intermediate circuit voltage+U of this voltage and current transformer
ZCompare and then be approximately zero.This is used to obtain collector emitter voltage U like this
CEThe output signal S of the device 14 of state
PulsBe in low level state.On the output 30 of logical circuit 16, represent the control signal S of fast shut-off pattern
StFBe in high level state, and represent the control signal S of lockout mode at a slow speed
StsLThen be in low level state.The grid of the high current module 2 of igbt-emitter current potential U like this
GEDescend by means of a constant maximum permission discharging current.At this grid-emitter voltage U
GEDuring decline, collector emitter voltage U
CEThen rise.At collector emitter voltage U shown in Figure 1
CESignal curve in can find out this collector emitter voltage U
CEExactly working as grid-emitter voltage U
GEBegin when equaling the Miller level ground to rise.As long as collector emitter voltage U
CEBe not equal to reference voltage U
CEref, the device 18 that then is used to produce the discharging current that is used for the fast shut-off pattern remains the state of being access in always.In case collector emitter voltage U
CEEqual/greater than reference voltage U
CEref, for example equal intermediate circuit voltage+U
Z(moment t
2), the output signal S of device 14
PulsJust uprise from low, like this control signal S on the output 30 of logical circuit 16
StFControl signal S from the output of high step-down and logical circuit 16
StsLThen uprise by low.Like this can be without delay in cutting-off process from the fast shut-off mode switch to lockout mode at a slow speed.Grid-emitter voltage U
GEFrom moment t
2Rise and descend with a less discharging current.The size of this discharging current depends on the permission blocking voltage on the power semiconductor switch 2, and this blocking voltage can occur but can not damage power semiconductor switch 2.At moment t
3The time, collector current I
CIt is a lot of to have descended, to such an extent as to from this moment t
3The tail current that plays the electric weight only only result from parts and stored flows through.At moment t
4Cutting-off process finishes because this moment collector current I
CAnd grid-emitter voltage U
GEEqual zero and collector emitter voltage U
CEEqual intermediate circuit voltage+U
ZNo longer because interference heavily is switched on automatically, suggestion is with grid-emitter voltage U for power semiconductor switch 2 thus
GEPlace on the negative potential such as-5V, wherein this point is at grid shown in Figure 1-emitter voltage U
GETime graph on be not expressed out.Output signal S
PulsAt monostable trigger 50 controlled time (＞t
4max) through changing low state into from high state afterwards, the device 18 that is used for the fast shut-off pattern like this is access in again.If device 18 and 20 usefulness grid discharge resistance R
Goff1And R
Goff2Realize that Low ESR ground linked to each other with a negative potential after then the gate terminal G of the high current module 2 of igbt covered in the time of monostable trigger 50.
If be used to detect collector emitter voltage U
CEThe device 14 of state also is transfused to has grid-emitter voltage U
GE, then might stop the fast shut-off mode switch to slow lockout mode.This means that this conversion is only as grid-emitter voltage U
GEGreater than/equal a reference voltage U
GErefIn time, just carry out, and this reference voltage has provided a threshold value on Miller level ground.Because the size on Miller level ground depends on collector current I
C, then Miller level ground size is an operate as normal of power semiconductor switch 2 or a sign of overload work or short circuit work.Only when overload work or short circuit work were identified, the fast shut-off pattern just was transformed into slow lockout mode without delay.
So just, can adopt the inventive method to optimize a cutting-off process with less expense, make that its switching time must be as far as possible in short-term nonlocking can-cut power semiconductor switch 2 being used in the hard switching formula current transformer, the operating state of cutting-off process and power semiconductor switch 2 is irrelevant, the contact of voltage rise time and downslope time therein is disconnected, and relies on the operating state of power semiconductor switch 2 to control this voltage rise time and downslope time independently of each other.
Be used to carry out one second form of implementation of the device of the inventive method shown in Fig. 8.The difference of the form of implementation of this form of implementation of device and device shown in Figure 2 is: but replacement device 14, logical circuit 16 and access device 18 and 20 are provided with a ramp signal generator 72, a change over switch 74 and a sequential controller 76.Ramp signal generator 72 links to each other with an input of change over switch 74 at output, and its another input then links to each other with one first output 10 of control device 4.The output of this change over switch 74 links to each other with the gate terminal G of the high current module 2 of igbt.Second output 12 of control device 4 is imported E with the emitter control of the high current module 2 of igbt
StLink to each other.The switch 78 of this change over switch 74 is subjected to sequential controller 76 controls.This sequential controller 76 is connected at the collector terminal C of the high current module 2 of its input and igbt.In addition, this sequential controller 76 is transfused to shutoff signal S
AusAccording to collector emitter voltage U in the cutting-off process
CEState can produce a control signal S
Um, come the switch 78 of control transformation switch 74 in cutting-off process with it.
Along with shutoff signal S
AusArrive control device 4 and sequential controller 76, on the one hand grid discharge resistance R in control device 4
GoffNegative potential with the transistor AND gate-5V of a push-pull cascade links to each other, and the switch 78 of change over switch 74 is subjected to the control of sequential controller 76 on the other hand, makes the gate terminal G of the high current module 2 of ramp signal generator 72 and igbt be connected.Grid G is through 72 discharges of ramp signal generator like this.In case collector emitter voltage U
CE(the moment t among Fig. 1 raises
1), the control signal S of sequential controller 76
UmWith regard to the change state, the switch 78 of change over switch 74 turns to like this, thereby makes the grid G and the grid discharge resistance R of the high current module 2 of igbt
GoffLink to each other.By ramp signal generator 72 is cut off from gate terminal G, the ramp signal generator is interrupted.The grid G of the high current module 2 of igbt now will be by grid discharge resistance R
GoffRepid discharge.In this repid discharge process of grid G, collector emitter voltage U
CERaise.If this collector emitter voltage U
CEEqual/greater than reference voltage U
CEref, the control signal S of sequential controller 76 then
UmChange its state once more, the switch 78 of change over switch 74 is commutated again like this, thus make grid G again through ramp signal generator 72 controllably with a slope discharge that is conditioned.As collector current I
CBe zero and collector emitter voltage U
CEEqual intermediate circuit voltage+U
ZThe time (t constantly among Fig. 1
4), control signal S
UmChange its state and this moment once more with grid G and grid discharge resistance R
GoffLink to each other, link to each other to the grid G low-resistance of power semiconductor switch 2 like this with negative potential.
The device this form of implementation, also be called storage circuit, with respect to device form of implementation shown in Figure 2 following advantage is arranged: when cutting-off process begins the slope of its discharge of grid G of power semiconductor switch 2 with in time period t
4-t
2In slope the same, collector emitter voltage U in this time period
CEGreater than/equal reference voltage U
CErefThis measure especially has outstanding advantage under short-circuit conditions.
Fig. 9 illustrates one the 3rd form of implementation of the device that is used to carry out the inventive method.With respect to second form of implementation shown in Figure 8, substitute change over switch 74 herein and be provided with three on/off switches 80,82 and 84.This on/off switch 80,82 is exported with a control of sequential controller 76 separately with 84 operation input and is linked to each other.On/off switch 80 links to each other the output 10 of control device 4 with gate terminal G, on/off switch 84 then links to each other the gate terminal G of the high current module 2 of igbt with an input 86 of ramp signal generator 72, on/off switch 82 then links to each other the output 88 of ramp signal generator 72 with gate terminal G.By means of on/off switch 82 and 84, ramp signal generator 72 can be controlled grid-emitter voltage U selectively
GE(on/off switch 82 closures) or adjust to potential value (on/off switch 84 closures) on the grid G.At time period [t
0, t
2] in, on/off switch 80 and 84 is closed, and grid G is through the grid discharge resistance R of control device 4 like this
GoffRepid discharge, the value of ramp signal generator 72 is adjusted to the potential value of grid G.At the change over switch moment (moment t among Fig. 1
2), on/off switch 82 is closed and on/off switch 80 and 84 disconnections.At this change over switch moment t
2, ramp signal generator 72 just in time has gate voltage values.Grid G is through ramp signal generator 72 slope discharge to be regulated subsequently.
The 3rd form of implementation of device is with respect to the advantage of second form of implementation shown in Figure 8 (memory circuit): grid G and ramp signal generator 72 are at conversion moment t
2Has identical magnitude of voltage.In so-called memory circuit, at time period [t
1, t
2] in due to leakage current may have problems, grid voltage equals the Miller plateau voltage in this time period.
Claims (14)
1. method that is used for optimizing in the cutting-off process of a nonlocking can-cut power semiconductor switch (2) of a hard switching formula current transformer is wherein along with a shutoff signal (S
Aus) arrival, grid-emitter voltage (U of this power semiconductor switch (2)
GE) descend by means of a maximum permission discharging current, and its collector emitter voltage (U
CE) monitoredly whether surpass one and be adjusted to and can make collector current (I
C) reference value (U that begins to commutate
CEref), when reaching this reference value (U
CEref) time, discharging current is reduced to less than maximum and permits on the value of discharge current value.
2. the method for claim 1, wherein grid-emitter voltage (U of power semiconductor switch (2)
GE) when cutting-off process begins, be lowered by means of a constant discharging current that is reduced, until the collector emitter voltage (U of power semiconductor switch (2)
CE) till the rising.
3. as claim 1 and 2 described methods, wherein, this constant discharge current value that is reduced equates in the beginning and the end of a period of the cutting-off process of power semiconductor switch (2).
4. one kind is used to carry out the device of method according to claim 1, it has a control device (4), its signal output (10) links to each other with a gate terminal (G) of a nonlocking can-cut power semiconductor switch (2) of a hard switching formula current transformer, and its benchmark output (12) is imported (E with the emitter control of switch (2)
St) be connected, wherein, be added with a control signal (S at the input of control device (4)
Aus), be used to obtain collector emitter voltage (U
CE) device (14) of state links to each other with a collector terminal (C) of power semiconductor switch (2) at input and then import (26) with one first of a logical circuit (16) at output and be connected, and on its second input (28) control signal (S arranged
AusBut) and provide two access devices (18 that are used to produce two different discharging currents, 20), its control input (34,36) export (30 with one of logical circuit (16) separately, 32) link to each other, at this, device (18,20) output links to each other with the gate terminal (G) of power semiconductor switch (2) and its input is connected with the signal of control device (4) output (39,40).
5. device that is used to carry out as method as described in claim 1 and 2, it has a control device (4), its signal output (10) links to each other with a gate terminal (G) of a nonlocking can-cut power semiconductor switch (2) of a hard switching formula current transformer, its benchmark output (12) is connected with the emitter control input (Est) of this switch (2), and wherein the input at control device (4) is added with a control signal (S
Aus), it is characterized in that: be provided with a ramp signal generator (72), it links to each other with an input of a change over switch (74) at output, its another input and the signal of control device (4) are exported (10) and are linked to each other and its output links to each other with the gate terminal (G) of power semiconductor switch (2), also be provided with a sequential controller (76), it links to each other with the collector terminal (C) of power semiconductor switch (2) at input and then is connected with the switch (78) of change over switch (74) at output, and wherein this sequential controller (76) is transfused to shutoff signal (S
Aus).
6. device as claimed in claim 4 wherein, is used to obtain collector emitter voltage (U
CE) the device (14) of state be connected with the gate terminal (G) of power semiconductor switch (2) at input.
7. device as claimed in claim 5, wherein, substitute change over switch (74) and be provided with three on/off switches (80,82,84), its operation input links to each other with sequential controller (76), and wherein the 3rd switch (84) imported (86) with the gate terminal (G) of power semiconductor switch (2) with one of ramp signal generator (72) and linked to each other.
8. device as claimed in claim 4 wherein, is used to obtain the collector emitter voltage (U of power semiconductor switch (2)
CE) the device (14) of state have the voltage divider (44) that is connected to comparator (46) after one, an adjustable reference voltage source (48) and have a monostable trigger (50) at input at output, wherein, this monostable trigger (50) links to each other in the output of input with comparator (46), and reference voltage source (48) is connected between the anti-phase input and a reference potential of comparator (46).
9. as claim 4 and 6 described devices, wherein, be used to obtain the collector emitter voltage (U of power semiconductor switch (2)
CE) the device (14) of state have the voltage divider (44) that is connected to comparator (46) after one, an adjustable reference voltage source (48) and have an evaluation device (60) at input at output, wherein this evaluation circuit (60) links to each other with the gate terminal (G) of power semiconductor switch (2) and links to each other with the output of comparator (46) on the other hand on the one hand at input, and reference voltage source (48) is connected between the anti-phase input and a reference potential of comparator (46).
10. device as claimed in claim 4, wherein, logical circuit (16) have one first and second with the door (52,54) and one first and second inverter (56,58), wherein the output of first inverter (56) separately with two with the door (52,54) a input links to each other, and wherein the output of second inverter (58) links to each other with one second input of door (54) with second, and wherein the input of second inverter (58) is on the one hand imported to link to each other with one second of door (52) and is then linked to each other with an input (26) of logical circuit (16) on the other hand with first, adds the output signal (S of the device (14) that is useful on the state of obtaining at this input
Puls), wherein the input of first inverter (56) links to each other with one second input (28) of logical circuit (16), and control signal (S is arranged on this input
Aus) and link to each other with a control output (32,30) of the output of door (52,54) and logical circuit (16).
11. device as claimed in claim 9, wherein, evaluation circuit (60) has a comparator (66), an adjustable reference voltage source (68) and one and door (70), wherein should link to each other with the output of evaluation circuit (60) and in input one side and comparator (66) at output with door (70), be connected with an input (62) of evaluation circuit (60) on the other hand, on this input (62), be added with a comparator signal (Y
Ce), wherein, this reference voltage source (68) is connected between the anti-phase input and a reference potential of comparator (66), and the noninverting input of comparator (68) links to each other with one second input (64) of evaluation circuit (60), is added with grid-emitter voltage (U of power semiconductor switch (2) on this second input (64)
GE).
12. device as claimed in claim 4 wherein, can insert resistance but be respectively equipped with one as described access device (18,20).
13. device as claimed in claim 4 wherein, can insert voltage source but be respectively equipped with one as described access device (18,20).
14. device as claimed in claim 4 wherein, can insert current source but be respectively equipped with one as described access device (18,20).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1996134612 DE19634612A1 (en) | 1996-08-27 | 1996-08-27 | Method and device for optimizing the switch-off process of a non-latching, switchable power semiconductor switch |
| DE19634612.6 | 1996-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1234146A true CN1234146A (en) | 1999-11-03 |
Family
ID=7803822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 97199012 Pending CN1234146A (en) | 1996-08-27 | 1997-08-18 | Process and device for optimizing power-down cycle of a non-engaging, interruptable power semiconductor switch |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0922331A1 (en) |
| CN (1) | CN1234146A (en) |
| DE (1) | DE19634612A1 (en) |
| NO (1) | NO990962L (en) |
| WO (1) | WO1998009378A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377325A (en) * | 2010-08-23 | 2012-03-14 | Abb研究有限公司 | Current balancing of parallel connected semiconductor components |
| CN103378829A (en) * | 2012-04-27 | 2013-10-30 | 英飞凌科技股份有限公司 | Method for driving power semiconductor switches |
| CN103718455A (en) * | 2011-08-05 | 2014-04-09 | 索尤若驱动有限及两合公司 | Inverter system with monitoring device, drive and vehicle |
| CN104378097A (en) * | 2014-09-29 | 2015-02-25 | 株洲变流技术国家工程研究中心有限公司 | Drive system and method of insulated gate bipolar transistor |
| CN105281729A (en) * | 2014-06-16 | 2016-01-27 | 英飞凌科技股份有限公司 | Circuit and method for driving a power semiconductor switch |
| CN110365321A (en) * | 2018-03-26 | 2019-10-22 | 赛米控电子股份有限公司 | Control device for power semiconductor switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3664061B2 (en) * | 1999-12-28 | 2005-06-22 | 日産自動車株式会社 | Current control type drive circuit for semiconductor device |
| DE10137764A1 (en) * | 2001-08-02 | 2003-02-13 | Daimler Chrysler Ag | Method and device for protection against overvoltages when switching off a semiconductor switch |
| DE10355255A1 (en) * | 2003-11-26 | 2005-07-07 | Rexroth Indramat Gmbh | Method for driving an insulated gate bipolar transistor and device for carrying out the method |
| GB2433358A (en) * | 2005-12-13 | 2007-06-20 | Bombardier Transp Gmbh | Operating electronic valves having an insulated gate |
| GB2458704A (en) * | 2008-03-28 | 2009-09-30 | Bombardier Transp Gmbh | An improved overcurrent protection circuit for an IGBT in an inverter |
| EP3729647A1 (en) * | 2018-01-31 | 2020-10-28 | Siemens Aktiengesellschaft | Method for switching off a power semiconductor component |
| EP3719997A1 (en) * | 2019-04-01 | 2020-10-07 | Siemens Aktiengesellschaft | Connection of a semiconductor switch |
| DE102019134525A1 (en) * | 2019-12-16 | 2021-06-17 | Valeo Siemens Eautomotive Germany Gmbh | Circuit arrangement and method for protecting a power semiconductor switch from overvoltages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4591734A (en) * | 1984-04-27 | 1986-05-27 | General Electric Company | Integratable circuit for controlling turn-off voltage rate-of-change of non-regenerative voltage-controlled switching semiconductor devices |
| DE58906812D1 (en) * | 1988-09-28 | 1994-03-10 | Siemens Ag | Protection circuit for a power semiconductor device. |
| DE3936544A1 (en) * | 1988-12-21 | 1990-06-28 | Siemens Ag | Protection circuit for power MOSFET - has switch across gate-source and responsive to drain and input voltages |
| US5204562A (en) * | 1991-11-29 | 1993-04-20 | Motorola, Inc. | Turn off delay reduction circuit and method |
| EP0645889B1 (en) * | 1993-09-13 | 2001-12-12 | Siemens Aktiengesellschaft | Method and device for limiting the rate of current decrease at swith-off of semiconductor power switches with MOS control imput |
| DE4428548B4 (en) * | 1994-08-12 | 2007-11-22 | Robert Bosch Gmbh | Circuit arrangement with a field effect transistor |
-
1996
- 1996-08-27 DE DE1996134612 patent/DE19634612A1/en not_active Withdrawn
-
1997
- 1997-08-18 EP EP97918888A patent/EP0922331A1/en not_active Withdrawn
- 1997-08-18 CN CN 97199012 patent/CN1234146A/en active Pending
- 1997-08-18 WO PCT/DE1997/001778 patent/WO1998009378A1/en not_active Application Discontinuation
-
1999
- 1999-02-26 NO NO990962A patent/NO990962L/en not_active Application Discontinuation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102377325A (en) * | 2010-08-23 | 2012-03-14 | Abb研究有限公司 | Current balancing of parallel connected semiconductor components |
| CN103718455A (en) * | 2011-08-05 | 2014-04-09 | 索尤若驱动有限及两合公司 | Inverter system with monitoring device, drive and vehicle |
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| CN103378829A (en) * | 2012-04-27 | 2013-10-30 | 英飞凌科技股份有限公司 | Method for driving power semiconductor switches |
| CN103378829B (en) * | 2012-04-27 | 2016-11-23 | 英飞凌科技股份有限公司 | For the method manipulating power semiconductor switch |
| CN105281729A (en) * | 2014-06-16 | 2016-01-27 | 英飞凌科技股份有限公司 | Circuit and method for driving a power semiconductor switch |
| US10033370B2 (en) | 2014-06-16 | 2018-07-24 | Infineon Technologies Ag | Circuit and method for driving a power semiconductor switch |
| CN105281729B (en) * | 2014-06-16 | 2019-12-10 | 英飞凌科技股份有限公司 | Method and circuit for controlling a power semiconductor switch |
| CN104378097A (en) * | 2014-09-29 | 2015-02-25 | 株洲变流技术国家工程研究中心有限公司 | Drive system and method of insulated gate bipolar transistor |
| CN104378097B (en) * | 2014-09-29 | 2018-06-12 | 株洲变流技术国家工程研究中心有限公司 | The drive system and method for a kind of insulated gate bipolar transistor |
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| CN110365321B (en) * | 2018-03-26 | 2023-07-28 | 赛米控电子股份有限公司 | Control device for power semiconductor switch |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1998009378A1 (en) | 1998-03-05 |
| NO990962L (en) | 1999-04-27 |
| DE19634612A1 (en) | 1998-03-12 |
| NO990962D0 (en) | 1999-02-26 |
| EP0922331A1 (en) | 1999-06-16 |
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