EP0903746A1 - Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle - Google Patents

Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle Download PDF

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Publication number
EP0903746A1
EP0903746A1 EP98402186A EP98402186A EP0903746A1 EP 0903746 A1 EP0903746 A1 EP 0903746A1 EP 98402186 A EP98402186 A EP 98402186A EP 98402186 A EP98402186 A EP 98402186A EP 0903746 A1 EP0903746 A1 EP 0903746A1
Authority
EP
European Patent Office
Prior art keywords
decoupling
transistors
memory cell
state
amplification means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP98402186A
Other languages
English (en)
French (fr)
Other versions
EP0903746B1 (de
Inventor
Noureddine El Haji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP0903746A1 publication Critical patent/EP0903746A1/de
Application granted granted Critical
Publication of EP0903746B1 publication Critical patent/EP0903746B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • dynamic random access memories are organized in rows and columns of memory cells and include, for each column, a device for amplifying read / rewrite of each selected memory cell, this device comprising precharge means making it possible to preload the corresponding column of the matrix (commonly called "bit line” or ("Bit Line” in English) by the man of the profession) at a selected voltage level, and amplification means with two looped reversers (forming a bistable rocker) each formed of two complementary transistors and controlled by two successive read and rewrite signals (commonly called respectively "sense” and "restore” in English).
  • the decoupling structure in its first state during the entire preload phase.
  • the PMOS decoupling transistors are also on.
  • the only precharge circuit 2 at the bottom of the column, i.e. opposite the memory cell with respect to means for amplifying and rendering the decoupling transistors NMOS T6 and T9 controllable on their grid by a second signal control (not shown in Figure 1 for the purpose of simplification) instead of connecting their grid constantly to the voltage of VDD polarization.
  • a second signal control not shown in Figure 1 for the purpose of simplification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
EP98402186A 1997-09-23 1998-09-04 Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle Expired - Lifetime EP0903746B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9711807A FR2768847B1 (fr) 1997-09-23 1997-09-23 Dispositif et procede de lecture/re-ecriture d'une cellule-memoire vive dynamique
FR9711807 1997-09-23

Publications (2)

Publication Number Publication Date
EP0903746A1 true EP0903746A1 (de) 1999-03-24
EP0903746B1 EP0903746B1 (de) 2003-12-17

Family

ID=9511359

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98402186A Expired - Lifetime EP0903746B1 (de) 1997-09-23 1998-09-04 Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle

Country Status (4)

Country Link
US (1) US5936904A (de)
EP (1) EP0903746B1 (de)
DE (1) DE69820555D1 (de)
FR (1) FR2768847B1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2774209B1 (fr) * 1998-01-23 2001-09-14 St Microelectronics Sa Procede de controle du circuit de lecture d'un plan memoire et dispositif de memoire correspondant
FR2775382B1 (fr) * 1998-02-25 2001-10-05 St Microelectronics Sa Procede de controle du rafraichissement d'un plan memoire d'un dispositif de memoire vive dynamique, et dispositif de memoire vive correspondant
US9679619B2 (en) * 2013-03-15 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Sense amplifier with current regulating circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306712A2 (de) * 1987-09-10 1989-03-15 International Business Machines Corporation Abtastverstärker für einen dynamischen RAM-Speicher mit verbesserter Bitleitungsaufladung
US5241503A (en) * 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory
JPH0696582A (ja) * 1990-09-17 1994-04-08 Texas Instr Inc <Ti> メモリアレイアーキテクチャ
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
KR0142952B1 (ko) * 1995-03-31 1998-08-17 김광호 반도체 메모리장치의 감지증폭기 회로

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306712A2 (de) * 1987-09-10 1989-03-15 International Business Machines Corporation Abtastverstärker für einen dynamischen RAM-Speicher mit verbesserter Bitleitungsaufladung
US5241503A (en) * 1991-02-25 1993-08-31 Motorola, Inc. Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Also Published As

Publication number Publication date
FR2768847B1 (fr) 2001-05-18
EP0903746B1 (de) 2003-12-17
DE69820555D1 (de) 2004-01-29
FR2768847A1 (fr) 1999-03-26
US5936904A (en) 1999-08-10

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