DE69820555D1 - Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle - Google Patents
Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen SpeicherzelleInfo
- Publication number
- DE69820555D1 DE69820555D1 DE69820555T DE69820555T DE69820555D1 DE 69820555 D1 DE69820555 D1 DE 69820555D1 DE 69820555 T DE69820555 T DE 69820555T DE 69820555 T DE69820555 T DE 69820555T DE 69820555 D1 DE69820555 D1 DE 69820555D1
- Authority
- DE
- Germany
- Prior art keywords
- overwriting
- reading
- memory cell
- dynamic memory
- dynamic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9711807A FR2768847B1 (fr) | 1997-09-23 | 1997-09-23 | Dispositif et procede de lecture/re-ecriture d'une cellule-memoire vive dynamique |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69820555D1 true DE69820555D1 (de) | 2004-01-29 |
Family
ID=9511359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69820555T Expired - Lifetime DE69820555D1 (de) | 1997-09-23 | 1998-09-04 | Verfahren und Vorrichtung zum Lesen und Überschreiben einer dynamischen Speicherzelle |
Country Status (4)
Country | Link |
---|---|
US (1) | US5936904A (de) |
EP (1) | EP0903746B1 (de) |
DE (1) | DE69820555D1 (de) |
FR (1) | FR2768847B1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2774209B1 (fr) * | 1998-01-23 | 2001-09-14 | St Microelectronics Sa | Procede de controle du circuit de lecture d'un plan memoire et dispositif de memoire correspondant |
FR2775382B1 (fr) * | 1998-02-25 | 2001-10-05 | St Microelectronics Sa | Procede de controle du rafraichissement d'un plan memoire d'un dispositif de memoire vive dynamique, et dispositif de memoire vive correspondant |
US9679619B2 (en) * | 2013-03-15 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sense amplifier with current regulating circuit |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3959781A (en) * | 1974-11-04 | 1976-05-25 | Intel Corporation | Semiconductor random access memory |
US4816706A (en) * | 1987-09-10 | 1989-03-28 | International Business Machines Corporation | Sense amplifier with improved bitline precharging for dynamic random access memory |
JPH0696582A (ja) * | 1990-09-17 | 1994-04-08 | Texas Instr Inc <Ti> | メモリアレイアーキテクチャ |
US5241503A (en) * | 1991-02-25 | 1993-08-31 | Motorola, Inc. | Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers |
US5339274A (en) * | 1992-10-30 | 1994-08-16 | International Business Machines Corporation | Variable bitline precharge voltage sensing technique for DRAM structures |
KR0142952B1 (ko) * | 1995-03-31 | 1998-08-17 | 김광호 | 반도체 메모리장치의 감지증폭기 회로 |
-
1997
- 1997-09-23 FR FR9711807A patent/FR2768847B1/fr not_active Expired - Fee Related
-
1998
- 1998-09-04 EP EP98402186A patent/EP0903746B1/de not_active Expired - Lifetime
- 1998-09-04 DE DE69820555T patent/DE69820555D1/de not_active Expired - Lifetime
- 1998-09-09 US US09/150,255 patent/US5936904A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0903746A1 (de) | 1999-03-24 |
FR2768847B1 (fr) | 2001-05-18 |
EP0903746B1 (de) | 2003-12-17 |
FR2768847A1 (fr) | 1999-03-26 |
US5936904A (en) | 1999-08-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |