EP0897573B1 - Systeme d'affichage numerique a modulation d'impulsions en largeur et plan de memoire d'image a multiprogrammation autonome - Google Patents

Systeme d'affichage numerique a modulation d'impulsions en largeur et plan de memoire d'image a multiprogrammation autonome Download PDF

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Publication number
EP0897573B1
EP0897573B1 EP97921309A EP97921309A EP0897573B1 EP 0897573 B1 EP0897573 B1 EP 0897573B1 EP 97921309 A EP97921309 A EP 97921309A EP 97921309 A EP97921309 A EP 97921309A EP 0897573 B1 EP0897573 B1 EP 0897573B1
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Prior art keywords
bits
display
duration
bit
row
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German (de)
English (en)
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EP0897573A1 (fr
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Richard John Edward Aras
Paul A. Alioshin
Bryan P. Straker
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Silicon Light Machines Inc
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Silicon Light Machines Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines

Definitions

  • This invention relates to the field of pulse width modulation (PWM) techniques. More particularly, this invention relates to a method of and an apparatus for providing gray scale or colors on a digital display where bits of different weights are time interleaved in order to minimize data bandwidth peaks.
  • PWM pulse width modulation
  • a pixel When displaying an image on a digital display, a pixel is either 'on' or 'off'. To form a more variable image it is desirable to provide selectable gray scale. Such increased variability can be used to provide more information or more realism in an image. For example, consider a display where an 'on' pixel is white and an 'off' pixel is black. To achieve an in-between state, eg., gray, the pixel can be toggled equally between 'on' and 'off'. If the pixel display duration is sufficiently short, the viewer's eye/brain system automatically integrates this toggled pixel to perceive a gray image rather than black or white. To achieve a lighter or darker gray, the duty cycle for toggling the pixel can be adjusted so the pixel is on more or less of the time, respectively.
  • FIG. 1 illustrates a conventional 3-bit unweighted scheme.
  • a pixel's image display cycle commonly known as a frame, is divided into seven equal time slots. Each pixel is selected to be on or off for the duration of the time slot by the writing of the corresponding data value. Pixels can be activated during any number of the slots from zero through seven. Providing the frame rate is high enough, the same intensity will be achieved with any ordering of the bits.
  • there are eight distinct intensity levels ranging from having a pixel off during all time slots to having a pixel on in all time slots.
  • Figure 2 illustrates a conventional binary weighted 8-bit PWM scheme.
  • each event has a distinct duration which is half that of its predecessor.
  • the intensity of the pixel can be selected using conventional binary coding.
  • the frame-time is divided into N events, with the duration of each event selected by the weight of the bit.
  • the shortest duration event, corresponding to the least significant bit, is frame-time/(2 N -1).
  • the scheme illustrated in Figure 2 can select among 256 (0 to 255) levels of gray scale from black to white.
  • the present invention has been designed for inclusion into a display system that includes a plurality of pixels arranged in an array of rows and columns.
  • the system includes 1024 rows of pixels, each having 1280 pixels arranged in columns.
  • a row of 1280 registers is loaded with the display data and the data is then written into the display.
  • Shift registers are used to sequentially store the data for a row of pixels.
  • the time available for loading a row of data into the shift registers is ⁇ /(# of rows), where ⁇ is the pixel display duration and the # of rows is 1024 in this example. Therefore, the required data bus peak bandwidth for the electronics supplying data to the shift registers is (# of rows)/ ⁇ x1280. It is well understood that the cost of a system can increase significantly with increased peak bandwidth requirement.
  • the data for the longest duration event ⁇ 1 is loaded and displayed, then the next longest event ⁇ 2 and so on until the data for the shortest event ⁇ N is loaded and displayed. Because all 1024 data bits must be loaded and then displayed during the time for the shortest event ⁇ N , this causes the limiting factor for the bandwidth of the system.
  • Figures 3A, B and C show a graphical representation of the timing necessary for loading and displaying a row of pixels of a display system using a four bit weighted gray scale.
  • the graphical representation of Figure 3A - shows time on the horizontal axis and the lines for displaying a single row of the display on its vertical axis. It will be understood that the time axis of Figure 3A repeats for each column of the display to form a complete image in a single frame. Once the frame is displayed, the process for forming a frame repeats itself indefinitely to form each subsequent frame in a display sequence.
  • the data for bit 3 (the longest duration bit) for all the rows are loaded sequentially into the display.
  • the data is displayed for the duration of the event as is schematically shown in Figure 3A.
  • the data for bit 2 is written to the display.
  • the data for bit 1 is written to the display.
  • the data for bit 0 is written to the display.
  • the data for bit 3 for the next frame is written to the display. This process of displaying the data for bit 3 must be completed within the duration of the event for bit 0.
  • the sloped line 100 ( Figure 3A) schematically represents the timing for loading the register with bit 3 data during the display time for event 0. It will be apparent to one of ordinary skill in the art that the bandwidth necessary to load 1280 bits of data for bit 3 of the next row during the display time for bit 0 of the present row is high.
  • the frame rate for the display is 60 Hz, i.e., the entire frame is drawn 60 times per second such that a frame is drawn in ⁇ 16.667 mSeconds. Assuming the display has 1024 rows, each row must be displayed in ⁇ 16.28 ⁇ Seconds.
  • the shortest duration event is ⁇ 64 nSeconds. This means that all 1280 bits of the next row must be written in ⁇ 64 nSeconds or ⁇ 800 pSeconds per word if loaded 16 bits at a time. This translates to ⁇ 1.25 GHz bandwidth. Naturally, these numbers are representational only. For example, the 60 Hz frame rate was drawn from standard television display technology. Other frame rates would apply for digital video signals such as produced by a high resolution computer graphics application that would typically utilize a 1280x1024 display.
  • Figure 3B is a timing diagram accurately depicting the events of Figure 3A. Rather that showing the fictional view of all events in successive rows happening simultaneously, the events for successive rows are shown actually occurring at successive cycles.
  • Figure 3C shows graphically the bandwidth requirements for loading data into the rows for a system built according to the timing of Figure 3B. As shown, the bandwidth requirements are high during the time that the data is transferred to the display. Accordingly, a system built according to the timing diagram of Figure 3B will have a bandwidth requirement as described above, as prescribed by the shortest duration bit weight of the binary coding scheme. Thus, for any of the longer weighted bits, the bandwidth requirements falls to zero during significant portions of the frame time causing unwanted 'dead times'. In other words, the bandwidth requirements of this system are either at a maximum level or at a zero level.
  • the bandwidth cannot be reduced by simply lengthening the duration of all the events.
  • an intermediate gray level is desired. If the duration of the frame and appropriate event are sufficiently long, the displayed pixel(s) will appear to flicker rather than appear as the intermediate gray level. Thus, it is important that the display time for all of the events not be too long.
  • An algorithmic time-interleaved bit-plane, pulse-width-modulation (PWM) digital display system method and apparatus reduces the bandwidth requirements necessary for providing a plurality of data entries representing multiple points of information.
  • the bandwidth requirements are constant, and for at least one system of measurement, optimal.
  • a weighted PWM scheme modulates an output by utilizing a frame duration that is divided into events of varying durations; most conventional schemes have each bit in the frame being half the duration of its predecessor. The modulated signal is activated during all, some or none of the events in the frame to develop a signal representing a particular parameter.
  • a predetermined number of bits is stored, wherein the bits are sufficient for defining the signal, such that each one of the bits represents a different duration event.
  • a set of these bits, one for each signal, is selected such that bits for at least two different duration events are comprised in the set.
  • a set of replacement bits is selected, one for any bit representing an event that will expire at a next clock pulse.
  • This method according to the invention is implemented by an apparatus comprising a memory, a selecting circuit, a control circuit for controlling the selecting circuit, and a circuit for generating modulated signals corresponding to the selected bits.
  • This method and apparatus can be used in a display for selecting among varying levels of gray scale or from among multiple colors on a palette.
  • a register containing the same number of data bits as pixels in a row of the display is provided.
  • the register is loaded, one row at a time, with one bit per column for each pixel in the entire row.
  • the duration for successively display rows is dissimilar thereby reducing the bandwidth requirements. This allows a bit for a long duration event to be displayed in one row, while bits for shorter duration events are displayed in other rows. This obviates the need to successively load the data for the shortest duration bits in all the rows.
  • the organization of the sequence of the events amongst the various rows is arranged to achieve reduced bandwidth. If the organization is chosen in a pseudo-random manner, the order can be pre-selected for an optimized bandwidth or organized into a predetermined format to achieve an improved visual effect.
  • the display is formed of an array of diffraction grating elements, such as disclosed in the Bloom, et al., U.S. patent 5,311,360, issued May 10, 1994.
  • the array of diffraction grating elements are arranged in rows and columns to form pixels of a display.
  • the array can be formed of single grating pixels for a black and white display - or time sequential multiplexing of pixels for color.
  • the pixels can be formed using multiple grating elements for each pixel to form a color display.
  • light from an illumination source can be made to selectively enter the display optics of display.
  • the light from a pixel enters the display optics, that pixel appears lighted.
  • Various levels of gray scale are formed by lighting the pixel varying percentages of time, i.e., by modulating the pulse width.
  • the preferred embodiment utilizes a weighted PWM scheme to form the gray scale selections.
  • a conventional display draws (illuminates) one pixel at a time as it scans the beam over the entire surface of the display. Unlike conventional displays, all the pixels in a single row of the diffraction grating light valve can be updated simultaneously in the preferred embodiment. Accordingly, the descriptions of the invention that follow will be directed toward displaying a row at a time. Nevertheless, it will be apparent to one of ordinary skill in the art that the techniques of the present invention can equally be applied to other types of devices that utilize a PWM scheme for generating gray scale.
  • each frame includes 1280 x 1024 pixels for a total of 1,310,720 pixels. Assuming an 8-bit weighted gray scale, 10,485,760 data bits are required to define a single frame.
  • each row of the graphical image is formed, one row at a time. Because of the ability to draw the display, one row at a time, the number of rows multiplied by the number of bits in gray scale weighting is equal to the number of update events per frame or write cycles per frame. Thus, there are 1024x8 events to draw a frame. Note that an event is the transfer of pixel data from a row-wide register into a row. It will be readily understood that a - number of operations (such as memory cycles) may be necessary to fill the register with the pixel data for the row.
  • the row image is displayed during one frame time such that the eight bits for each pixel in the row are appropriately presented to the viewer's eye.
  • the viewer's eye/brain system then integrates the 8 weighted bits for each pixel into a row of pixels each of the appropriate gray scale.
  • the viewer's eye/brain system integrates the display for each row into a single graphical image.
  • the display apparatus of the present invention includes an image memory 400 as shown in Figure 4.
  • the image memory 400 can be any convenient memory type including semiconductor memory such as RAM, including but not limited to DRAM, SRAM or VRAM, or a non-semiconductor memory such as a hard disk, floppy disk or optical disk, with or iwthout intermediate processing (e.g., MPEG decompression).
  • the image memory 400 is shown in Figure 4 as having multiple planes. This plane metaphor is used conceptually to show that each pixel includes multiple data bits for the various bits of the weighted PWM scheme; it will be apparent to those of ordinary skill in the art that any convenient organization of the graphical image data in the image memory 400 can be used.
  • a control circuit 402 Under control of a control circuit 402, data is transferred from the image memory 400 into a register 404. Once the register is full, and at an appropriate time according to a clock signal generated by the control circuit 402, the data in the register 404 is coupled to illuminate pixels in the appropriate row of the display 406. The display retains data of a pixel state written to the rows until they are updated in a subsequent cycle.
  • the register 404 contains 1280 latch and driver circuits that buffer the memory bus to the column connections of the display. As discussed in the background section of this patent document, if all 1280 latches must be loaded with data during the shortest event duration, the bandwidth requirements for the electronics becomes too severe for an economical solution.
  • the present invention re-orders the time during which the bits of the various weights are displayed in comparison to the prior art. Because the frame time is sufficiently short so that the viewer's eye/brain system can integrate the displayed image into the appropriate shades of gray, the presentation order of these bits does not affect the image quality.
  • Figure 5 shows one example of an 8-bit binary weighted PWM scheme for four rows of data according to one embodiment of the present invention. As Figure 5 clearly shows, the shortest event is not repeated in the same time slot during any of the four rows. It will be apparent to one of ordinary skill in the art after reading this disclosure that the order of the weighted bits can be selected for optimization of different characteristics, such as bandwidth or visual effect.
  • Figure 6A shows another scheme for selecting the data to be loaded into the register without the necessity of performing a complex optimization scheme. Only the first eight rows of the row of data are shown in this Figure. Immediately before time zero, the bit in the register that corresponds to row 0 is loaded with the data for the 0th weight bit, the register bit for row 1 is loaded with the 3rd weight bit, the register for row 2 is loaded with the 2nd weight bit, the register for rows 3-6 are loaded with the 1st weight bits and row 7 is loaded with the 0th weight bit. During the next clock cycle the data in rows 1 and 2 changes such that row 1 is loaded with the data for its 0th weight bit and row 2 is loaded with the 3rd weight bit. At time one, this new data is clocked into the display. During the next clock cycle, only the data in rows 2 and 3 changes, and so forth. In this way, the number of data transitions per clock cycle is dramatically reduced and the data can be extracted from the memory in a regular fashion.
  • Figure 6B shows a bandwidth requirement diagram for a system built according to the timing diagram of Figure 6A. As discussed above the bandwidth requirements of a system built according to the embodiment of Figure 6A are reduced. Here, as shown in Figure 6B, the bandwidth requirement becomes constant; there are no 'dead times' as shown in the prior art of Figure 3C.
  • FIG. 6A shows an alternative scheme to that of Figure 6A. According the the scheme of Figure 6C, the longest duration bit 602 is split into two (or more) time-separated display periods.
  • next shortest bit 604 is displayed between the two halves of the longest duration bit 602.
  • the third longest duration bit 606 and the shortest duration bit 608 follow the second half of the longest duration bit 602. In this way, even if only the longest duration bit is displayed, its duty cycle is the same but the duration of each on-off cycle is sufficiently shortened to avoid forming a flicker.
  • Figures 7A and 7B show the timing for loading the data for the rows of this small display according to a prior art PWM scheme.
  • the time to display a frame is divided into (2 n -1) segments.
  • Figure 7A all fifteen rows display the data for the longest event during the time segment zero.
  • All fifteen rows display the data for the next longest event during the time segment eight.
  • All fifteen rows display the data for the third longest event during the time segment twelve.
  • All fifteen rows display the data for the shortest event during the time segment fourteen.
  • Figure 7B shows the same prior art PWM timing as Figure 7A except that the shortest event is displayed first.
  • all fifteen rows display the data for the shortest event during the time segment zero.
  • All fifteen rows display the data for the next shortest event during the time segment one, for the third shortest event during the time segment three and for the longest event during the time segment seven.
  • Figure 8 shows the timing necessary for loading the data for the rows of this small display according to one non-binary embodiment of the present invention.
  • the timing diagram for Figure 8 shows that the bandwidth requirement for the display system are considerably reduced by not having all the shortest duration events displayed at the same time.
  • the time segment zero there are four events displayed: for rows zero (the shortest event gray scale), eight (the longest event gray scale), twelve (the third shortest event) and fourteen (the second shortest event).
  • the time segment one there are four events displayed: for rows zero (the second shortest event), one (the shortest event), nine (the longest event) and thirteen (the third shortest event).
  • the time segment two only four events are displayed: for the rows one (the second shortest), two (the shortest), ten (the longest) and fourteen (the third shortest). This timing for displaying the rest of the frame is shown in the remainder of the drawing.
  • the number of rows that can be drawn according to the present invention is equal to the number of time segments. Because of the nature of conventional PWM weighting, only 2 n -1 time segments are available, where n is the number of bits of gray scale. For example, in Figure 8, because 4 bit gray scale is used, only 15 rows can appear in the display. To provide for more rows, for example 30 rows, the timing for drawing the two halves of the array must be interleaved.
  • the granularity of gray scale is a function of the number of rows in the display or the number of rows in the video format.
  • each row of bits is first blanked before each new display event.
  • Figure 10 shows a modified time chart for a single row of a display which includes these blanking times.
  • the total blanking time for displaying the gray scale for a row is equal to one time segment. Because there is one blanking time of duration 1/n for each bit of gray scale one full time segment is added.
  • the preferred embodiment includes 2 n time segments rather than 2 n -1 as found in the prior art. Accordingly, this embodiment can readily support drawing sixteen rows as shown in Figure 11 rather than the fifteen rows shown in Figures 7A, 7B and 8. Referring now to Figure 10, the timing can be seen for a single row having its shortest event first.
  • Bit zero (the shortest event) is displayed during the first time segment. Next, the blanking period is provided for bit 1 for a duration of 1/4 time segment. Then, bit 1 is displayed for a total period of 2 time segments. This sequence continues for the remaining bits of gray scale control.
  • Figures 7A, 7B, 8 and 11 imply that the rows of an entire frame image are all simultaneously displayed.
  • the data for each frame is received serially.
  • Figure 6 shows a time. line representation for the timing of data presentation of the rows in a display.
  • the shaded portion 600 of Figure 6 shows the collection of data and their respective timing for forming a single frame image. As the first row of a new frame image is drawn onto the display, the remaining portion of the previous frame image is still being displayed.
  • Table I shows the timing for displaying the lowest order bit according to the scheme of Figure 7B. According to Table I, each data bit is sequentially loaded into each row as also shown in Figure 3. To display a frame, 240 clock cycles are neede for 4 bit gray scale according to one version of the prior art.
  • Table II shows the timing of the present invention.
  • the timing for loading and for clearing the data is indicated such as graphically indicated in Figure 10.
  • the data for Bit0, Row0 is loaded and data for Row15 is cleared.
  • the data for Bit1, Row15 is loaded and data for row 13 is cleared.
  • This analysis continues for the remainder of Table II.
  • 64 clock cycles are neede for 4 bit gray scale according to the preferred embodiment of the present invention.
  • Virtual lines can be added to the display sequence to match the gray scale resolution requirement. It will be understood that these virtual rows are not display but rather add only to the sequence of events for forming the display image. For example, if only 480 lines comprise a frame, and the cycle time is adjusted to represent 512 lines per frame, the a 6% increase in bandwidth results. In this case 6% of the possible update cyucles are not used for writing data to the display.
  • a second approach for resolving a non-matching gray scale-display system is to use the granularity provided by the total number of rows.
  • the gray scale definition can be reduced and/or a higher bandwidth can be implemented.
  • a 480 row display would achieve nearly 9 bits of gray scale resolution (512 levels), but some of the binary codes would be missing while others would produce equal output brightness.
  • 9 bits of gray scale are used to encode the 480 distinct values, a 12% increase in bandwidth results.
  • a third approach for resolving a non-matching gray scale-display system is to increase the duration of the least significant bits in combination with a clear behind technique such as taught in U.S. Patent Application, Serial No. 08/482,192, filed June 7, 1995, and entitled CLEAR-BEHIND MATRIX ADDRESSING FOR DISPLAY SYSTEMS.
  • Such a system can provide a bandwidth optimal system for a non-power-of-2 number of rows but reduces the optical efficiency.

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Claims (13)

  1. Procédé de formation d'une pluralité de signaux de modulation de largeur d'impulsion, comprenant les étapes, dans lesquelles :
    b. on mémorise un nombre prédéterminé de bits pour chaque signal, dans lequel les bits suffisent à définir le signal, de façon que chacun des bits représente un événement de durée différente ;
    c1. on choisit un ensemble de bits, un pour chaque signal, de façon à choisir des bits d'au moins deux événements de durée différente ; et
    d. on choisit un ensemble de bits de remplacement, un pour chaque bit représentant un événement qui expire à une impulsion d'horloge suivante.
  2. Procédé selon la revendication 1, comprenant en outre l'étape :
    a. de réception dudit nombre prédéterminé de bits de chaque signal avant de le mémoriser.
  3. Procédé selon la revendication 2 de formation d'une pluralité de signaux de modulation de largeur d'impulsion pour délivrance à un afficheur numérique (406) comportant une pluralité de lignes et une pluralité de colonnes, dans lequel l'afficheur (406) est configuré pour recevoir des signaux de modulation de largeur d'impulsion, une ligne de pixels à la fois, dans lequel :
    c2. lesdites étapes de choix d'un ensemble de bits et de bits de remplacement comprennent, respectivement, le choix d'un sous-ensemble de bits et de bits de remplacement, chaque sous-ensemble comprenant les bits de chaque pixel d'une ligne prédéterminée pour former une partie de signal d'une durée prédéterminée,
       ledit procédé comprenant en outre les étapes, dans lesquelles :
    c3. on écrit des données pour toutes les lignes, une ligne à la fois,
    d. on forme une pluralité de parties de signal, une pour chacun des sous-ensembles de bits, de durée représentative du sous-ensemble de bits, et l'on couple les signaux avec l'une, prédéterminée, des lignes de l'afficheur (406) ; et
       dans lequel au moins trois sous-ensembles consécutifs de bits sont affichés pendant une durée différente.
  4. Dispositif pour obtenir une modulation de largeur d'impulsion pondérée pour chacun d'une pluralité de signaux pendant une durée de trame, comprenant :
    a. une mémoire destinée à mémoriser une pluralité de groupements de bits de données représentatifs de chacun des signaux, dans lequel chacun des groupements comprend un nombre identique de bits, de sorte que chaque bit d'un groupement représente l'une d'une durée d'événement différente prédéterminée ;
    b. un circuit de choix destiné à choisir, à partir d'un premier sous-ensemble de la pluralité, un bit par groupement formant un premier ensemble de bits choisis ayant tous une durée d'événement prédéterminée, de façon à choisir des bits d'au moins deux événements de durée différente ; et
    c. un circuit destiné à générer plusieurs signaux modulés correspondant aux bits choisis ; et
    d. un circuit de commande (402) destiné à commander le circuit de choix pour choisir, à partir d'un second sous-ensemble de la pluralité, un bit par groupement en formant un second ensemble de bits choisis, de façon à ne remplacer que les bits, pendant un cycle d'horloge suivant, pour lesquels la durée d'événement différente expire à l'impulsion d'horloge suivante, et en outre, dans lequel seul un ensemble de bits peut expirer à une quelconque impulsion d'horloge.
  5. Dispositif selon la revendication 4, dans lequel une exigence de largeur de bande pour adaptation au choix du second ensemble de bits choisis est inférieure à celle du cas dans lequel tous les bits de durée la plus courte sont choisis successivement.
  6. Dispositif selon la revendication 5, dans lequel l'exigence de largeur de bande est constante.
  7. Dispositif selon l'une quelconque des revendications 4 à 6, dans lequel les signaux sont couplés pour moduler plusieurs pixels d'un afficheur (406), dans le but de former une image en demi-teintes.
  8. Dispositif selon la revendication 7, dans lequel les pixels sont agencés en une pluralité de lignes et de colonnes et comprenant en outre un registre (404) comportant plusieurs éléments de mémorisation, un pour chaque pixel d'une ligne.
  9. Dispositif selon l'une quelconque des revendications 4 à 8, dans lequel le circuit de commande (402) choisit l'ensemble de bits choisis en fonction d'un algorithme prédéterminé.
  10. Dispositif selon l'une quelconque des revendications 4 à 6, dans lequel les signaux sont couplés pour moduler une pluralité de pixels d'un afficheur (406), dans le but de former une couleur prédéterminée.
  11. Dispositif selon la revendication 10, dans lequel les pixels sont agencés en une pluralité de lignes et de colonnes et comprenant en outre un registre (404) comportant une pluralité d'éléments de mémorisation, un pour chaque pixel d'une ligne.
  12. Dispositif selon l'une quelconque des revendications 4 à 11, dans lequel ledit dispositif est apte à fournir une modulation de largeur d'impulsion pondérée de n bits pour chaque m lignes de signaux, dans lequel, chaque ligne de signaux est configurée pour recevoir n signaux, dans le but d'afficher des bits d'une durée qui varie ayant une durée la plus courte à une durée la plus longue, qui sont représentatifs de m x n bits de données modulés en largeur d'impulsion, dans lequel lesdits ensembles de bits choisis comprennent des sous-ensembles incluant des bits de chaque pixel d'une ligne prédéterminée ayant tous la même durée, dans lequel ledit circuit de commande est apte à afficher ultérieurement des sous-ensembles différents dans des rangées différentes, et dans lequel au moins trois sous-ensembles consécutifs concernent des bits de durée différente.
  13. Afficheur comprenant :
    a. un groupement de pixels agencés en une pluralité de lignes et une pluralité de colonnes ;
    b. un registre (404) comportant une pluralité d'éléments de mémorisation servant à mémoriser temporairement des données, le registre (404) comportant autant d'éléments de mémorisation que de pixels d'une ligne ; et
    c. un dispositif selon l'une quelconque des revendications 4 à 7 ou 9 à 12.
EP97921309A 1996-04-22 1997-04-21 Systeme d'affichage numerique a modulation d'impulsions en largeur et plan de memoire d'image a multiprogrammation autonome Expired - Lifetime EP0897573B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/635,479 US5731802A (en) 1996-04-22 1996-04-22 Time-interleaved bit-plane, pulse-width-modulation digital display system
US635479 1996-04-22
PCT/US1997/006656 WO1997040487A1 (fr) 1996-04-22 1997-04-21 Systeme d'affichage numerique a modulation d'impulsions en largeur et plan de memoire d'image a multiprogrammation autonome

Publications (2)

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EP0897573A1 EP0897573A1 (fr) 1999-02-24
EP0897573B1 true EP0897573B1 (fr) 2002-09-25

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US (1) US5731802A (fr)
EP (1) EP0897573B1 (fr)
JP (1) JP2000510252A (fr)
KR (1) KR20000010572A (fr)
AT (1) ATE225071T1 (fr)
AU (1) AU2738097A (fr)
DE (1) DE69715837T2 (fr)
NO (1) NO984907L (fr)
WO (1) WO1997040487A1 (fr)

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JP2000510252A (ja) 2000-08-08
DE69715837D1 (de) 2002-10-31
KR20000010572A (ko) 2000-02-15
US5731802A (en) 1998-03-24
ATE225071T1 (de) 2002-10-15
EP0897573A1 (fr) 1999-02-24
WO1997040487A1 (fr) 1997-10-30
DE69715837T2 (de) 2003-01-23
NO984907L (no) 1998-12-18
NO984907D0 (no) 1998-10-21
AU2738097A (en) 1997-11-12

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