EP0886884A1 - Memory cell arrangement with vertical mos transistors and the production process thereof - Google Patents

Memory cell arrangement with vertical mos transistors and the production process thereof

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Publication number
EP0886884A1
EP0886884A1 EP97915321A EP97915321A EP0886884A1 EP 0886884 A1 EP0886884 A1 EP 0886884A1 EP 97915321 A EP97915321 A EP 97915321A EP 97915321 A EP97915321 A EP 97915321A EP 0886884 A1 EP0886884 A1 EP 0886884A1
Authority
EP
European Patent Office
Prior art keywords
trenches
doped
main surface
flanks
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP97915321A
Other languages
German (de)
French (fr)
Inventor
Franz Hofmann
Josef Willer
Wolfgang Krautschneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0886884A1 publication Critical patent/EP0886884A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Definitions

  • MOS transistors Semiconductor-based read-only memories are known for storing smaller amounts of data. In many cases, these are implemented as a plane integrated silicon circuit in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word line. The input of the MOS transistor is connected to a reference line, the output to a bit line. The reading process evaluates whether a current flows through the transistor or not. The logical values zero and one are assigned accordingly.
  • the storage of zero and one is effected in that no MOS transistor is produced in memory cells in which the logic value associated with the state "no current flow through the transistor" is stored or no conductive connection to the bit line is realized MOS transistors can be realized for the two logical values, which have different threshold voltages due to different dopant concentrations in the channel region.
  • semiconductor-based memories allow random access to the stored information.
  • the one for reading the The electrical power required for information is significantly smaller than in the aforementioned storage systems with mechanically moving parts. As no moving parts are required, mechanical wear and sensitivity to vibrations are also eliminated.
  • Semiconductor-based memories can therefore also be used for mobile systems.
  • the silicon memories described usually have a planar structure. This means that a minimum space requirement is required per memory cell, which in the best case is 4 F ⁇ , where F is the smallest structure size that can be produced in the respective technology.
  • a read-only memory cell arrangement is known, the memory cells of which comprise MOS transistors. These MOS transistors are arranged along trenches such that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region both vertically to the surface of the substrate and parallel to the surface of the substrate on the flank and Bottom of the trench adjoins.
  • the surface of the channel area is provided with a gate dielectric.
  • the gate electrode is designed as a flank covering (spacer). The logical values zero and one are distinguished by different threshold voltages which are brought about by channel implantation.
  • the implanting ions hit the surface of the respective trench at such an angle that is specifically implanted along one flank by shadowing effects of the opposite flank.
  • the word lines run as spacers along the flanks of the trenches.
  • JP-OS 4-226071 which comprises vertical MOS transistors arranged as memory cells on the flanks of trenches. Diffusion runs on the bottom of trenches and between adjacent trenches. ons regions, which each form the source / drain regions of the vertical MOS transistors.
  • the word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicular to the trenches.
  • the threshold voltage of the vertical MOS transistors is set by an angled implant.
  • a memory cell arrangement is known from US Pat. No. 4,663,644 which comprises vertical MOS transistors as memory cells. These vertical MOS transistors are each arranged on the flanks of trenches.
  • the word lines which each comprise the gate electrodes of the vertical MOS transistors, are arranged in the trenches. Two word lines are arranged in each trench.
  • the bit lines are implemented as conductor tracks on the surface of the substrate.
  • the contact between the bit lines and the respective source / drain regions, which adjoin the surface of the substrate, is realized via a contact hole.
  • the source / drain regions, which adjoin the bottom of the trenches, are implemented as a continuous doped layer and are set to reference potential.
  • the information is stored in this memory cell arrangement in the form of threshold voltages of different levels for the MOS transistors.
  • the different threshold voltages are realized by different dopant concentrations in the channel region of the MOS transistors.
  • a doped layer is deposited and structured in such a way that flanks in which increased dopant concentrations are to be formed remain covered by the structured dopant layer.
  • the channel regions with an increased dopant concentration are formed by diffusion out of the structured dopant layer.
  • the invention is based on the problem of specifying a memory cell arrangement based on semiconductors in which an increased memory density is achieved and which can be produced with a few production steps and with a high yield. Of- Furthermore, a method for producing such a memory cell arrangement is to be specified.
  • memory cells are provided in a substrate, each of which comprises a MOS transistor vertical to the main surface.
  • a substrate made of monocrystalline silicon or the silicon layer of an SOI substrate is preferably used as the substrate.
  • the vertical MOS transistors have different threshold voltages depending on the stored information.
  • the MOS transistors are driven at a voltage level at which the MOS transistors conduct with a lower threshold voltage and those with a higher threshold voltage do not conduct.
  • Strip-shaped trenches running essentially parallel are provided in the substrate. Strip-shaped doped regions are arranged on the bottom of the trenches and on the main area between adjacent trenches, which are doped with a second conductivity type opposite to the first. Gate dielectrics are arranged on the flanks of the trenches. Word lines are provided which run transversely to the trenches and which comprise gate electrodes for the vertical MOS transistors in the region of the flanks of the trenches.
  • the vertical MOS transistors each consist of two strip-shaped doped regions adjacent to the same flank of one of the trenches, which act as a source / drain region, the flank of the trench arranged therebetween, the gate dielectric and the part arranged above one of the words - lines formed.
  • the striped doped areas are used as bit or reference line in the operation of the memory cell arrangement.
  • memory cells in which predetermined information is stored have a dopant region in the upper region of the flank of the trench, the extent of the dopant perpendicular to the main surface being less than the depth of the trenches.
  • the doping regions are preferably doped with the same conductivity type as the channel regions, but with an increased doping concentration. In this case, the threshold voltage increases. They can also be doped from the opposite conductivity type, in which case the threshold voltage drops.
  • the invention makes use of the knowledge that the threshold voltage of a MOS transistor can also be set by a locally inhomogeneous dopant concentration in the channel region.
  • the parts of the dopant region and its precise adjustment with respect to the associated word line are therefore not critical.
  • the vertical MOS transistors have more than two different threshold voltages.
  • the dopant regions are realized with different dopant concentrations in the flanks.
  • the distance between adjacent trenches is preferably selected such that it is substantially equal to the width of the trenches.
  • the distance between adjacent word lines is also chosen equal to the width of the word lines. If the width of the trenches and the width of the word lines correspond to the minimum structure width F in the respective
  • stripe-shaped trenches are preferably formed in a main surface of a substrate, said trenches running essentially parallel.
  • Strip-shaped doped regions are formed on the bottom of the trenches and on the main surface between adjacent trenches, which are doped from a second conductivity type opposite to the first.
  • a mask layer is applied, which has an essentially conformal edge covering.
  • a mask for example made of photoresist, is produced on the mask layer and has openings.
  • the mask layer is structured using the mask so that in the area of the openings
  • the main surface and the surface of the trenches are exposed.
  • the flanks of trenches in the area of the openings are only partially exposed, so that a residue of the mask layer remains on these flanks in the lower area of the trenches.
  • the trenches are preferably formed by anisotropic etching using a trench mask.
  • the stripe-shaped doped regions on the bottom of the trenches and on the main area between adjacent trenches are preferably produced by an implantation after the trench formation and after removal of the trench mask. It is advantageous to include the flanks of the trenches before the implantation
  • the stripe-shaped doped regions can be produced by creating a doped region on the main surface before the trenches are formed, which covers the entire memory cell array. When the trenches are opened, this doped region is divided into the strip-like doped regions on the main surface.
  • the strip-shaped doped regions at the bottom of the trenches are produced by ion implantation after the trenches have opened. When using a trench mask, it is advantageous to leave it as a mask on the main surface during the implantation.
  • the mask layer is preferably structured by anistropic etching.
  • the mask layer can also be structured by combined isotropic and anisotropic etching. The etching is selective to the substrate.
  • the main surface and the bottoms of the trenches are exposed in the region of the openings.
  • the etching attack on the exposed main area and the exposed bottoms of the trenches which is inevitable because of the finite selectivity of the etching, is reduced.
  • the threshold voltage only depends on the dopant concentration in the channel area, both the exact depth of the dopant area and its lateral adjustment with respect to the arrangement of the gate electrodes are not critical.
  • the dopant regions are preferably formed in the exposed flank parts by an angled implantation.
  • the implantation is preferably carried out with an inclination angle in the range between 20 ° and 30 ° against the normal of the Main area. Such inclination angles are provided as standard in many implantation systems to avoid the channeling effect.
  • the dopant regions are produced by diffusion out of a doped layer.
  • the doped layer is applied over the entire surface above the structured mask layer.
  • the doped layer is preferably formed from doped glass, doped polysilicon or doped amorphous silicon.
  • doped glass has the advantage that in this case the doped layer can be selectively removed from the substrate.
  • the mask used for structuring can be removed in order to avoid shadowing by the mask during the subsequent implantation.
  • the method according to the invention can thus also be used for trench widths which can be significantly smaller than in the storage cell arrangement known from DE 42 14 923 A1.
  • the mask for structuring the mask layer is formed from photoresist, the photoresist does not have to be exposed to the bottom of the trench during the exposure for programming.
  • Modern exposure steppers with a focus depth of ⁇ 0.5 ⁇ m can thus also be used in the method according to the invention. Because the mask layer at the bottom of the trench is not necessarily removed unexposed photoresist can remain on the bottom of the trench in the method according to the invention. This avoids exposure problems over the full topology of the trench.
  • FIG. 1 shows a substrate with a trough doped with a first conductivity type.
  • FIG. 2 shows the substrate after the etching of stripe-shaped trenches.
  • FIG. 3 shows the substrate after the formation of stripe-shaped doped regions on the bottoms of the trenches and between adjacent trenches on the main surface.
  • FIG. 4 shows the substrate after the application of a mask layer and the formation of a mask.
  • FIG. 5 shows the substrate after structuring the mask layer.
  • FIG. 6 shows the substrate after the application of a doped layer.
  • FIG. 7 shows the substrate after the formation of dopant regions in the flanks of the trenches and after the formation of word lines running transversely to the trenches.
  • FIG. 8 shows a plan view of the substrate after the word lines have been formed.
  • a substrate 1 of, for example, p-doped silicon with a dopant concentration monokri ⁇ stallinem of 5 x l ⁇ l5 cm "3 is in a major surface 2 by implantation and subsequent heat-doped p-a trough 3 with a dopant concentration of 2 x 10- * - 7 cm ⁇ ⁇ generated (see Figure 1.)
  • a scattering oxide with a thickness of, for example, 50 nm (not shown) is used, which after driving in the p-doped well 3 with 180 keV, 7 x 10 ⁇ 2 cm ⁇ 2.
  • the p-doped well 3 extends at least over an area for one cell field.
  • An SiO 2 "layer is deposited on the main surface 2 in a layer thickness of, for example, 300 nm, for example in a TEOS process.
  • the SiO 2 layer is structured with the aid of photolithographic process steps, a trench mask 4 being formed.
  • the trench mask 4 has stripes
  • the strip-shaped openings in the trench mask 4 have a width of, for example, 0.4 ⁇ m, a length of, for example, 125 ⁇ m and a distance of 0.4 ⁇ m.
  • trenches 5 are etched into the main surface 2 of the substrate 1 in an anisotropic etching process, for example using HBr, He, O2, NF3.
  • Trenches 5 have a strip-shaped cross section corresponding to the openings of the trench mask 4 parallel to the main surface 2. They have a width of for example 0.4 ⁇ m, a length of for example 125 ⁇ m and a distance of for example 0.4 ⁇ m. The depth of the trenches is, for example, 0.6 ⁇ m (see FIG. 2). For example, 32 parallel trenches 5 are formed. The trench mask 4 is then removed using, for example, HF dip. In order to improve the quality of the crystal surfaces, an SiO 2 layer 6 (so-called sacrificial oxide) with a thickness of, for example, 20 nm is produced by thermal oxidation (see FIG. 3).
  • SiO 2 layer 6 silicacrificial oxide
  • SiO 2 spacers 7 and the SiO 2 layer 6 are then removed, for example by wet chemical etching with HF dip.
  • a mask layer 9 with an essentially conformal edge covering is deposited from SiO 2, for example in a TEOS process.
  • the mask layer 9 is deposited in a layer thickness of 60 to 80 nm (see FIG. 4).
  • a mask 10 is then formed, for example, from photoresist using photolithographic process steps.
  • the mask 10 has openings 11 in the cell field.
  • the openings 11 are adjusted so that they overlap at least one flank of the trenches 5.
  • the dimensions of the openings 11 parallel to the main surface 2 each correspond to the width of the trenches 5. Larger dimensions of the openings 11 result from the collapse of adjacent openings.
  • the mask 10 is adjusted so that the openings 11 are arranged to overlap the flanks of the trenches 5.
  • the openings 11 likewise have minimal dimensions of F x F.
  • the adjustment accuracy is, for example, F / 2 to F / 3 .
  • the mask layer 9 is structured in an anisotropic etching process, for example using HBr, CI2, He.
  • the mask 10 acts as an etching mask. In this case, 5 etching residues 9 'remain in the region of the openings 11 on the flanks of the trenches. In the area of the openings 11, the silicon surface is exposed on the bottoms of the trenches 5 and on the main surface 2 between adjacent trenches 5. Under the mask 10, however, the mask layer 9 is not attacked.
  • the patterning of the mask layer 9 takes place in an etching process which is selective for silicon. However, due to the limited selectivity, there is an etching attack on the exposed silicon surfaces. Since the etching residues 9 ′ remain on the flanks of the trenches 5, the etching attack on the exposed silicon surfaces that is unavoidable due to the finite selectivity is reduced.
  • the height of the etching residues 9 ′ is less than the depth of the strip-shaped, doped regions 8 arranged on the main surface 2.
  • the height of the etching residues 9 ' is, for example, 300 nm.
  • the exact height of the etching residues 9' is not critical as long as part of the trench wall is exposed below the strip-shaped doped region 8 adjacent to the trench wall.
  • Parts of the mask layer 9 exposed at the bottom of the trenches 5 by the mask 10 are removed during the structuring of the mask layer 9. In the event that when the mask 10 is formed from photoresist, the photoresist has not been exposed to the bottom of the trenches 5, the mask layer 9 at the bottom of the trenches 5 is covered by unexposed photoresist.
  • the mask layer 9 is not attacked during the anisotropic etching at the bottom of the trenches 5 and the bottom of the trenches 5 remains covered by the mask layer 9. This is not critical for the further course of the method according to the invention.
  • the mask 10 is removed (see FIG. 5).
  • a thin scattering oxide (approx. 10 nm) is then deposited using a TEOS process (not shown).
  • two angled implantations with boron are carried out with a dose of 10 ⁇ 3 c ⁇ 2 to 5 x 10 ⁇ - cm ⁇ 2 and an energy of 60 keV.
  • the angle of inclination relative to the normal of the main surface 2 is 20 ° to 30 °, and - 20 ° to - 30 °.
  • dopant regions 12 are formed in the exposed flanks of the trenches 5 above the etching residues 9 '(see FIG. 7).
  • the Dotierstoff capableen 12 is a dopant concentration of some 10 17 cm -3, 8 x 10 ⁇ preferred wise adjusted to 7 cm ⁇ 3 f.
  • the doping in the stripe-shaped doped regions is 8 10 ⁇ 1 cm "3, the implantation of boron in this area can be tolerated.
  • the mask 10 is formed, 5 unexposed photoresist remains at the bottom of the trenches and the Bottoms of the trenches 5 are covered with the mask layer 9, boron is not implanted into the strip-shaped doped regions 8 arranged at the bottom of the trenches 5.
  • the formation of the dopant regions 12 in the exposed flanks of the trenches 5 is not impaired by this.
  • the dopant regions 12 are formed in the flanks of the trenches 5 by diffusion out of a doped layer 13.
  • the doped layer 13 for example made of borosilicate glass, is deposited over the entire surface in a layer thickness of 50 nm (see FIG. 6).
  • the doping areas 12 are produced by out-diffusion.
  • the doped layer 13 is removed, for example with an HF dip.
  • a gate dielectric 14 is produced, for example by thermal oxidation, in a layer thickness of 10 nm, for example.
  • the vertical MOS transistors are each formed from two strip-shaped doped regions 8 which adjoin the same flank of one of the trenches 5, the part of the trough 3 arranged in between as a channel region, the gate dielectric 14 and the part of one of the word lines 15 adjoining it.
  • the extent of the vertical MOS transistor parallel to the course of the strip-shaped trenches 5 is given by the width of the word lines 15.
  • MOS transistors that are adjacent along an edge of one of the trenches are separated by the distance between adjacent word lines 15 separated from each other.
  • the strip-shaped doped regions 8 each run over the entire cell field. They form lines which, depending on the circuitry, are used as bit lines or reference lines and which connect the source / drain regions of MOS transistors adjacent along a trench.
  • the vertical MOS transistor has an increased threshold voltage or not.
  • the information stored in the memory cell arrangement is stored in the presence or absence of the dopant regions 12.
  • the programming of the memory cell arrangement is therefore carried out when the mask layer 9 is structured.
  • the arrangement of the openings 11 in the mask 10 transfers the information into the memory cell arrangement.
  • the strip-shaped doped regions 8 are used as bit or reference lines for reading out the memory cells.
  • the memory cell to be evaluated is selected via the word line.
  • a control signal is applied to the word line, the voltage level of which lies between the threshold voltage of the MOS transistors with dopant region 12 in the channel region and that of the MOS transistors without dopant region 12 in the channel region. With this control signal, the MOS transistors without dopant region 12 in the channel region become conductive, while the MOS transistors with dopant region 12 in the channel region, which have an increased threshold voltage, continue to block.
  • it is evaluated whether a current flows between the associated strip-shaped doped regions 8 or not.
  • FIG. 8 shows a top view of the memory cell arrangement. The course of the word lines 15 across the trenches 5 is shown. Furthermore, the stripe-shaped, doped areas 8 entered, which run at the bottom of the trenches 5 and between adjacent trenches 5. Doping regions 12 are entered in the flanks of the trenches as a dashed contour.
  • Each memory cell comprises a vertical MOS transistor, which has an extent of 2 F parallel to the course of the stripe-shaped trenches 5 and an extent of F perpendicular to the course of the stripe-shaped trenches 5.
  • the space requirement per memory cell is therefore 2 F 2 .
  • the production of the memory cell arrangement is concluded with the deposition of an intermediate dielectric, the opening of contact holes and the production of a metallization (not shown).

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Abstract

In a memory cell arrangement which includes vertical MOS transistors as the memory cells, information is stored by different threshold voltages of the transistors. Dopant regions are formed for an information state by angular implantation or diffusion in the upper part of the channel region. The lower part of the channel region is consequently covered by an etching residue (9') which is produced by a masked spacer etching. The arrangement can be produced with a surface requirement of 2 F2 (F being the minimum structural size) per memory cell.

Description

Beschreibungdescription
SPEICHERZELLENANORDNUNG MIT VERTIKALEN MOS-TRANSISTOREN UND DEREN HERSTELLUNGSVERFAHRENSTORAGE CELL ARRANGEMENT WITH VERTICAL MOS TRANSISTORS AND THEIR PRODUCTION METHOD
Zur Abspeicherung großer Datenmengen, zum Beispiel für DV- Anwendungen oder zur digitalen Abspeicherung von Musik oder Bildern, werden derzeit hauptsachlich Speichersysteme mit me¬ chanisch bewegten Teilen wie zum Beispiel Festplattenspei¬ cher, Floppy-Discs oder Kompaktdiscs verwendet. Die bewegten Teile sind mechanischem Verschleiß unterworfen. Ferner benö¬ tigen sie vergleichsweise viel Volumen und erlauben nur einen langsamen Datenzugriff. Da sie darüber hinaus erschütterungs- und lageempfindlich sind und einen vergleichsweise hohen Energieverbrauch zu ihrem Betrieb haben, sind diese Speicher- Systeme in mobilen Systemen nur begrenzt einsetzbar.For the storage of large amounts of data, for example for DV applications or for the digital storage of music or images, storage systems with mechanically moving parts such as, for example, hard disk memories, floppy disks or compact discs are currently used. The moving parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and only permit slow data access. Since they are also sensitive to vibrations and situations and have a comparatively high energy consumption for their operation, these storage systems can only be used to a limited extent in mobile systems.
Zur Speicherung kleinerer Datenmengen sind Festwertspeicher auf Halbleiterbasis bekannt. Vielfach werden diese als plane¬ re integrierte Siliziumschaltung realisiert, in der als Spei- cherzellen MOS-Transistoren verwendet werden. Die Transisto¬ ren werden über die Gateelektrode, die mit der Wortleitung verbunden ist, ausgewählt. Der Eingang des MOS-Transistors ist mit einer Referenzleitung verbunden, der Ausgang mit ei¬ ner Bitleitung. Beim Lesevorgang wird bewertet, ob ein Strom durch den Transistor fließt oder nicht. Entsprechend werden die logischen Werte Null und Eins zugeordnet. Technisch wird die Speicherung von Null und Eins dadurch bewirkt, daß in Speicherzellen, in denen der dem Zustand »kein Stromfluß durch den Transistor" zugeordnete logische Wert gespeichert ist, kein MOS-Transistor hergestellt wird oder keine leitende Verbindung zur Bitleitung realisiert wird. Alternativ können für die beiden logischen Werte MOS-Transistoren realisiert werden, die durch unterschiedliche Dotierstoffkonzentrationen im Kanalgebiet unterschiedliche Einsatzspannungen aufweisen.Semiconductor-based read-only memories are known for storing smaller amounts of data. In many cases, these are implemented as a plane integrated silicon circuit in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word line. The input of the MOS transistor is connected to a reference line, the output to a bit line. The reading process evaluates whether a current flows through the transistor or not. The logical values zero and one are assigned accordingly. Technically, the storage of zero and one is effected in that no MOS transistor is produced in memory cells in which the logic value associated with the state "no current flow through the transistor" is stored or no conductive connection to the bit line is realized MOS transistors can be realized for the two logical values, which have different threshold voltages due to different dopant concentrations in the channel region.
Diese Speicher auf Halbleiterbasis erlauben einen wahlfreien Zugriff auf die gespeicherte Information. Die zum Lesen der Information erforderliche elektrische Leistung ist deutlich kleiner als bei den erwähnten Speichersystemen mit mechanisch bewegten Teilen. Da keine bewegten Teile erforderlich sind, entfällt hier auch der mechanische Verschleiß und die E p- findlichkeit gegenüber Erschütterungen. Speicher auf Halblei¬ terbasis sind daher auch für mobile Systeme einsetzbar.These semiconductor-based memories allow random access to the stored information. The one for reading the The electrical power required for information is significantly smaller than in the aforementioned storage systems with mechanically moving parts. As no moving parts are required, mechanical wear and sensitivity to vibrations are also eliminated. Semiconductor-based memories can therefore also be used for mobile systems.
Die beschriebenen Siliziumspeicher weisen meist einen plana- ren Aufbau auf. Damit wird pro Speicherzelle ein minimaler Flächenbedarf erforderlich, der im günstigsten Fall bei 4 F^ liegt, wobei F die in der jeweiligen Technologie kleinste herstellbare Strukturgröße ist.The silicon memories described usually have a planar structure. This means that a minimum space requirement is required per memory cell, which in the best case is 4 F ^, where F is the smallest structure size that can be produced in the respective technology.
Aus DE 42 14 923 AI ist eine Festwertspeicherzellenanordnung bekannt, deren Speicherzellen MOS-Transistoren umfassen. Die¬ se MOS-Transistoren sind entlang von Gräben so angeordnet, daß ein Sourcegebiet an den Boden des Grabens angrenzt, ein Draingebiet an die Oberfläche des Substrats angrenzt und ein Kanalgebiet sowohl vertikal zur Oberfläche des Substrats als auch parallel zur Oberfläche des Substrats an Flanke und Bo¬ den des Grabens angrenzt. Die Oberfläche des Kanalgebietes ist mit einem Gatedielektrikum versehen. Die Gateelektrode ist als Flankenbedeckung (Spacer) ausgebildet. Die logischen Werte Null und Eins werden durch unterschiedliche Einsatz- Spannungen, die durch Kanalimplantation bewirkt werden, un¬ terschieden. Bei der Kanalimplantation treffen die implantie¬ renden Ionen unter einem solchen Winkel auf die Oberfläche des jeweiligen Grabens, das durch Abschattungseffekte der ge¬ genüberliegenden Flanke gezielt nur entlang einer Flanke i - plantiert wird. Die Wortleitungen verlaufen in dieser Spei¬ cherzellenanordnung als Spacer entlang den Flanken der Grä¬ ben.From DE 42 14 923 AI a read-only memory cell arrangement is known, the memory cells of which comprise MOS transistors. These MOS transistors are arranged along trenches such that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region both vertically to the surface of the substrate and parallel to the surface of the substrate on the flank and Bottom of the trench adjoins. The surface of the channel area is provided with a gate dielectric. The gate electrode is designed as a flank covering (spacer). The logical values zero and one are distinguished by different threshold voltages which are brought about by channel implantation. In the case of channel implantation, the implanting ions hit the surface of the respective trench at such an angle that is specifically implanted along one flank by shadowing effects of the opposite flank. In this memory cell arrangement, the word lines run as spacers along the flanks of the trenches.
Aus JP-OS 4-226071 ist eine weitere Speicherzellenanordnung bekannt, die als Speicherzellen an den Flanken von Gräben an¬ geordnete vertikale MOS-Transistoren umfaßt. Dabei verlaufen am Boden von Gräben und zwischen benachbarten Gräben Diffusi- onsgebiete, die jeweils die Source/Drain-Gebiete der vertika¬ len MOS-Transistoren bilden. Die Wortleitungen, die die Ga¬ teelektroden der vertikalen MOS-Transistoren umfassen, ver¬ laufen senkrecht zu den Gräben. Die Einsatzspannung der ver- tikalen MOS-Transistoren wird durch eine gewinkelte Implanta¬ tion eingestellt.A further memory cell arrangement is known from JP-OS 4-226071, which comprises vertical MOS transistors arranged as memory cells on the flanks of trenches. Diffusion runs on the bottom of trenches and between adjacent trenches. ons regions, which each form the source / drain regions of the vertical MOS transistors. The word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicular to the trenches. The threshold voltage of the vertical MOS transistors is set by an angled implant.
Aus US-PS 4 663 644 ist eine Speicherzellenanordnung bekannt, die als Speicherzellen vertikale MOS-Transistoren umfaßt. Diese vertikalen MOS-Transistoren sind jeweils an den Flanken von Gräben angeordnet. Die Wortleitungen, die jeweils die Ga¬ teelektroden der vertikalen MOS-Transistoren umfassen, sind in den Gräben angeordnet. In jedem Graben sind zwei Wortlei¬ tungen angeordnet. Die Bitleitungen sind als Leiterbahnen auf der Oberfläche des Substrats realisiert. Der Kontakt zwischen den Bitleitungen und den jeweiligen Source/Drain-Gebieten, die an die Oberfläche des Substrats angrenzen, ist über ein Kontaktloch realisiert. Die Source/Drain-Gebiete, die an den Boden der Gräben angrenzen, sind als durchgehende dotierte Schicht realisiert und werden auf Referenzpotential gelegt. In dieser Speicherzellenanordnung wird die Information in Form unterschiedlich hoher Einsatzspannungen der MOS- Transistoren gespeichert. Die unterschiedlichen Einsatzspan¬ nungen werden durch unterschiedliche Dotierstoffkonzentratio- nen im Kanalgebiet der MOS-Transistoren realisiert. Zur Bil¬ dung einer erhöhten Dotierstoffkonzentration im Kanalgebiet wird eine dotierte Schicht abgeschieden und so strukturiert, daß Flanken, in denen erhöhte Dotierstoffkonzentrationen ge¬ bildet werden sollen, von der strukturierten Dotierstoff- schicht bedeckt bleiben. Durch Ausdiffusion aus der struktu¬ rierten Dotierstoffschicht werden die Kanalbereiche mit er¬ höhter Dotierstoffkonzentration gebildet.A memory cell arrangement is known from US Pat. No. 4,663,644 which comprises vertical MOS transistors as memory cells. These vertical MOS transistors are each arranged on the flanks of trenches. The word lines, which each comprise the gate electrodes of the vertical MOS transistors, are arranged in the trenches. Two word lines are arranged in each trench. The bit lines are implemented as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source / drain regions, which adjoin the surface of the substrate, is realized via a contact hole. The source / drain regions, which adjoin the bottom of the trenches, are implemented as a continuous doped layer and are set to reference potential. The information is stored in this memory cell arrangement in the form of threshold voltages of different levels for the MOS transistors. The different threshold voltages are realized by different dopant concentrations in the channel region of the MOS transistors. To form an increased dopant concentration in the channel region, a doped layer is deposited and structured in such a way that flanks in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions with an increased dopant concentration are formed by diffusion out of the structured dopant layer.
Der Erfindung liegt das Problem zugrunde, eine Speicherzel- lenanordnung auf Halbleiterbasis anzugeben, bei der eine er¬ höhte Speicherdichte erzielt wird und die mit wenigen Her¬ stellungsschritten und hoher Ausbeute herstellbar ist. Des- weiteren soll ein Verfahren zur Herstellung einer solchen Speicherzellenanordnung angegeben werden.The invention is based on the problem of specifying a memory cell arrangement based on semiconductors in which an increased memory density is achieved and which can be produced with a few production steps and with a high yield. Of- Furthermore, a method for producing such a memory cell arrangement is to be specified.
Dieses Problem wird erfindungsgemäß gelöst durch eine Spei- cherzellenanordnung nach Anspruch 1 sowie ein Verfahren zu deren Herstellung nach Anspruch 3. Weitere Ausgestaltungen der Erfindung ergeben sich aus den Unteransprüchen.According to the invention, this problem is solved by a memory cell arrangement according to claim 1 and a method for its production according to claim 3. Further developments of the invention result from the subclaims.
In der erfindungsgemäßen Speicherzellenanordnung sind in ei- nem Substrat Speicherzellen vorgesehen, die jeweils einen zur Hauptfläche vertikalen MOS-Transistor umfassen. Als Substrat wird vorzugsweise ein Substrat aus monokristallinem Silizium oder die Siliziumschicht eines SOI-Substrats verwendet. Die vertikalen MOS-Transistoren weisen je nach gespeicherter In- formation unterschiedliche Einsatzspannungen auf.In the memory cell arrangement according to the invention, memory cells are provided in a substrate, each of which comprises a MOS transistor vertical to the main surface. A substrate made of monocrystalline silicon or the silicon layer of an SOI substrate is preferably used as the substrate. The vertical MOS transistors have different threshold voltages depending on the stored information.
Zum Auslesen der Information werden die MOS-Transistoren mit einem Spannungspegel angesteuert, bei dem die MOS- Transistoren mit geringerer Einsatzspannung leiten und die mit höherer Einsatzspannung nicht leiten.To read out the information, the MOS transistors are driven at a voltage level at which the MOS transistors conduct with a lower threshold voltage and those with a higher threshold voltage do not conduct.
In dem Substrat sind streifenförmige, im wesentlichen paral¬ lel verlaufende Gräben vorgesehen. Am Boden der Gräben und an der Hauptfläche zwischen benachbarten Gräben sind streifen- förmige dotierte Gebiete angeordnet, die von einem zweiten, dem ersten entgegengesetzten Leitfähigkeitstyp dotiert sind. An den Flanken der Gräben sind jeweils Gatedielektrika ange¬ ordnet. Es sind Wortleitungen vorgesehen, die quer zu den Gräben verlaufen und die im Bereich der Flanken der Gräben Gateelektroden für die vertikalen MOS-Transistoren umfassen. Die vertikalen MOS-Transistoren werden jeweils aus zwei an dieselbe Flanke eines der Gräben angrenzenden streifenförmi- gen dotierten Gebiete, die als Source/Drain-Gebiet wirken, die dazwischen angeordnete Flanke des Grabens, das Gatedie- lektrikum und den darüber angeordneten Teil einer der Wort- leitungen gebildet. Die streifenförmigen dotierten Gebiete werden im Betrieb der Speicherzellenanordnung als Bit- bzw. Referenzleitung verwendet.Strip-shaped trenches running essentially parallel are provided in the substrate. Strip-shaped doped regions are arranged on the bottom of the trenches and on the main area between adjacent trenches, which are doped with a second conductivity type opposite to the first. Gate dielectrics are arranged on the flanks of the trenches. Word lines are provided which run transversely to the trenches and which comprise gate electrodes for the vertical MOS transistors in the region of the flanks of the trenches. The vertical MOS transistors each consist of two strip-shaped doped regions adjacent to the same flank of one of the trenches, which act as a source / drain region, the flank of the trench arranged therebetween, the gate dielectric and the part arranged above one of the words - lines formed. The striped doped areas are used as bit or reference line in the operation of the memory cell arrangement.
Zur Realisierung der unterschiedlichen Schwellenspannungen weisen Speicherzellen, in denen eine vorbestimmte Information gespeichert ist, im oberen Bereich der Flanke des Grabens ein Dotierstoffgebiet auf, dessen Ausdehnung senkrecht zur Hauptfläche geringer als die Tiefe der Gräben ist. Die Do¬ tierstoffgebiete werden vorzugsweise von demselben Leitfähig- keitstyp wie die Kanalbereiche jedoch mit erhöhter Dotier- stoffkonzentration dotiert. In diesem Fall steigt die Ein¬ satzspannung an. Sie können auch vom entgegengesetzten Leit¬ fähigkeitstyp dotiert werden, hier sinkt dann die Einsatz¬ spannung.In order to implement the different threshold voltages, memory cells in which predetermined information is stored have a dopant region in the upper region of the flank of the trench, the extent of the dopant perpendicular to the main surface being less than the depth of the trenches. The doping regions are preferably doped with the same conductivity type as the channel regions, but with an increased doping concentration. In this case, the threshold voltage increases. They can also be doped from the opposite conductivity type, in which case the threshold voltage drops.
Die Erfindung macht sich dabei die Erkenntnis zunutze, daß die Einsatzspannung eines MOS-Transistors auch durch eine lo¬ kal inhomogene Dotierstoffkonzentration im Kanalbereich ein¬ stellbar ist. Die Teile des Dotierstoffgebietes und dessen genaue Justierung bezüglich der zugehörigen Wortleitung sind damit unkritisch.The invention makes use of the knowledge that the threshold voltage of a MOS transistor can also be set by a locally inhomogeneous dopant concentration in the channel region. The parts of the dopant region and its precise adjustment with respect to the associated word line are therefore not critical.
Soll die Speicherzellenanordnung im Sinne einer Mehrwertlogik eingesetzt werden, so liegt es im Rahmen der Erfindung, daß die vertikalen MOS-Transistoren mehr als zwei unterschiedli¬ che Einsatzspannungen aufweisen. In diesem Fall werden die Dotierstoffgebiete mit unterschiedlichen Dotierstoffkonzen¬ trationen in den Flanken realisiert.If the memory cell arrangement is to be used in the sense of a multi-value logic, it is within the scope of the invention that the vertical MOS transistors have more than two different threshold voltages. In this case, the dopant regions are realized with different dopant concentrations in the flanks.
Vorzugsweise wird der Abstand zwischen benachbarten Gräben so gewählt, daß er im wesentlichen gleich der Breite der Gräben ist. Der Abstand zwischen benachbarten Wortleitungen wird ebenfalls gleich der Breite der Wortleitungen gewählt. Wird die Breite der Gräben und die Breite der Wortleitungen ent- sprechend der minimalen Strukturbreite F in der jeweiligenThe distance between adjacent trenches is preferably selected such that it is substantially equal to the width of the trenches. The distance between adjacent word lines is also chosen equal to the width of the word lines. If the width of the trenches and the width of the word lines correspond to the minimum structure width F in the respective
Technologie gewählt, so ergibt sich für die Speicherzelle ein Platzbedarf von 2 F2. Legt man eine minimale Strukturbreite von F = 0,4 um zugrunde, so wird in der Speicherzellenanord¬ nung eine Speicherdichte von etwa 3,1 Bit/um2 erzielt.Technology selected, the space required for the memory cell is 2 F 2 . If you set a minimum structure width of F = 0.4 µm, a storage density of approximately 3.1 bits / µm 2 is achieved in the memory cell arrangement.
Zur Herstellung der erfindungsgemäßen Speicherzellenanordnung werden vorzugsweise in einer Hauptfläche eines Substrats streifenförmige Gräben gebildet, die im wesentlichen.parallel verlaufen. Am Boden der Gräben und an der Hauptfläche zwi¬ schen benachbarten Gräben werden streifenförmige dotierte Ge¬ biete gebildet, die von einem zweiten, zum ersten entgegenge- setzten Leitfähigkeitstyp dotiert sind. Anschließend wird ei¬ ne Maskenschicht aufgebracht, die eine im wesentlichen kon¬ forme Kantenbedeckung aufweist. Auf der Maskenschicht wird eine Maske, zum Beispiel aus Photolack, erzeugt, die Öffnun¬ gen aufweist. Die Maskenschicht wird unter Verwendung der Maske so strukturiert, daß im Bereich der Öffnungen dieTo produce the memory cell arrangement according to the invention, stripe-shaped trenches are preferably formed in a main surface of a substrate, said trenches running essentially parallel. Strip-shaped doped regions are formed on the bottom of the trenches and on the main surface between adjacent trenches, which are doped from a second conductivity type opposite to the first. Then a mask layer is applied, which has an essentially conformal edge covering. A mask, for example made of photoresist, is produced on the mask layer and has openings. The mask layer is structured using the mask so that in the area of the openings
Hauptfläche und die Oberfläche an den Böden der Gräben frei¬ gelegt wird. Die Flanken von Gräben im Bereich der Öffnungen werden dagegen nur teilweise freigelegt, so daß an diesen Flanken im unteren Bereich der Gräben ein Rest der Masken- schicht verbleibt.The main surface and the surface of the trenches are exposed. The flanks of trenches in the area of the openings, on the other hand, are only partially exposed, so that a residue of the mask layer remains on these flanks in the lower area of the trenches.
Anschließend werden in den freigelegten Flankenteilen Dotier¬ stoffgebiete erzeugt. Nach Entfernen der strukturierten Mas¬ kenschicht wird an den Flanken der Gräben ein Gatedielektri- kum gebildet. Schließlich werden Wortleitungen gebildet, die quer zu den Gräben verlaufen.Subsequently, dopant regions are generated in the exposed flank parts. After removing the structured mask layer, a gate dielectric is formed on the flanks of the trenches. Finally, word lines are formed that run across the trenches.
Die Gräben werden vorzugsweise durch anisotropes Ätzen unter Verwendung einer Grabenmaske gebildet.The trenches are preferably formed by anisotropic etching using a trench mask.
Die streifenförmigen dotierten Gebiete am Boden der Gräben und an der Hauptfläche zwischen benachbarten Gräben werden vorzugsweise durch eine Implantation nach der Grabenbildung und nach Entfernen der Grabenmaske erzeugt. Dabei ist es vor- teilhaft, die Flanken der Gräben vor der Implantation mitThe stripe-shaped doped regions on the bottom of the trenches and on the main area between adjacent trenches are preferably produced by an implantation after the trench formation and after removal of the trench mask. It is advantageous to include the flanks of the trenches before the implantation
Spacern zu versehen, die bei der Implantation maskierend wir¬ ken. Diese Spacer werden anschließend entfernt. Die Bildung der Gräben und der streifenförmigen dotierten Gebiete erfor¬ dert nur eine Maske.To provide spacers that have a masking effect during implantation. These spacers are then removed. The education the trenches and the stripe-shaped doped regions require only one mask.
Alternativ können die streifenförmigen dotierten Gebiete da- durch hergestellt werden, daß vor der Bildung der Gräben ein dotierter Bereich an der Hauptfläche erzeugt wird, der das gesamte Speicherzellenfeld überdeckt. Bei der Öffnung der Gräben wird dieser dotierte Bereich in die streifenförmigen dotierten Gebiete an der Hauptfläche unterteilt. Die strei- fenförmigen dotierten Gebiete am Boden der Gräben werden nach der Öffnung der Gräben durch Ionenimplantation erzeugt. Bei Verwendung einer Graben aske ist es dabei vorteilhaft, diese bei der Implantation als Maske auf der Hauptfläche zu belas¬ sen.Alternatively, the stripe-shaped doped regions can be produced by creating a doped region on the main surface before the trenches are formed, which covers the entire memory cell array. When the trenches are opened, this doped region is divided into the strip-like doped regions on the main surface. The strip-shaped doped regions at the bottom of the trenches are produced by ion implantation after the trenches have opened. When using a trench mask, it is advantageous to leave it as a mask on the main surface during the implantation.
Die Strukturierung der Maskenschicht erfolgt vorzugsweise durch anistropes Ätzen. Die Strukturierung der Maskenschicht kann jedoch auch durch kombiniertes isotropes und anisotropes Ätzen erfolgen. Das Ätzen erfolgt selektiv zu dem Substrat.The mask layer is preferably structured by anistropic etching. However, the mask layer can also be structured by combined isotropic and anisotropic etching. The etching is selective to the substrate.
In dem erfindungsgemäßen Verfahren werden zwar die Hauptflä¬ che und die Böden der Gräben im Bereich der Öffnungen freige¬ legt. Da jedoch an den Flanken der Gräben ein Rest der Mas¬ kenschicht verbleibt, wird der Ätzangriff auf die freigelegte Hauptfläche und die freigelegten Böden der Gräben, der wegen der endlichen Selektivität der Ätzung unvermeidlich ist, re¬ duziert.In the method according to the invention, the main surface and the bottoms of the trenches are exposed in the region of the openings. However, since a remainder of the mask layer remains on the flanks of the trenches, the etching attack on the exposed main area and the exposed bottoms of the trenches, which is inevitable because of the finite selectivity of the etching, is reduced.
Da die Einsatzspannung lediglich von der Dotierstoffkonzen- tration im Kanalbereich abhängt, sind sowohl die exakte Tiefe des Dotierstoffgebietes als auch dessen seitliche Justierung in bezug auf die Anordnung der Gateelektroden unkritisch.Since the threshold voltage only depends on the dopant concentration in the channel area, both the exact depth of the dopant area and its lateral adjustment with respect to the arrangement of the gate electrodes are not critical.
Die Dotierstoffgebiete werden in den freigelegten Flankentei- len vorzugsweise durch eine gewinkelte Implantation gebildet. Die Implantation erfolgt vorzugsweise mit einem Neigungswin¬ kel im Bereich zwischen 20° und 30° gegen die Normale der Hauptfläche. Derartige Neigungswinkel sind in vielen Implan¬ tationsanlagen zur Vermeidung des Channeling-Effekts stan¬ dardmäßig vorgesehen.The dopant regions are preferably formed in the exposed flank parts by an angled implantation. The implantation is preferably carried out with an inclination angle in the range between 20 ° and 30 ° against the normal of the Main area. Such inclination angles are provided as standard in many implantation systems to avoid the channeling effect.
Alternativ werden die Dotierstoffgebiete durch Ausdiffusion aus einer dotierten Schicht erzeugt. Die dotierte Schicht wird ganzflächig oberhalb der strukturierten Maskenschicht aufgebracht. Die dotierte Schicht wird vorzugsweise aus do¬ tiertem Glas, dotiertem Polysilizium oder dotiertem amorphem Silizium gebildet. Die Verwendung von dotiertem Glas hat den Vorteil, daß die dotierte Schicht in diesem Fall selektiv zum Substrat entfernt werden kann.Alternatively, the dopant regions are produced by diffusion out of a doped layer. The doped layer is applied over the entire surface above the structured mask layer. The doped layer is preferably formed from doped glass, doped polysilicon or doped amorphous silicon. The use of doped glass has the advantage that in this case the doped layer can be selectively removed from the substrate.
Die Einführung der Maskenschicht in den erfindungsgemäßen Prozeß führt zu folgenden Vorteilen:The introduction of the mask layer into the process according to the invention leads to the following advantages:
- Es wird nur eine Maske zur Programmierung der Speicherzel- lenanordnung benötigt. Im Gegensatz dazu werden in den aus DE 42 14 923 AI und JP-OS 4-22 60 71 bekannten Speicherzel- lenanordnungen jeweils zwei Masken zur Programmierung benö¬ tigt.- Only one mask is required to program the memory cell arrangement. In contrast, two masks are required for programming in the memory cell arrangements known from DE 42 14 923 AI and JP-OS 4-22 60 71.
- Nach der Strukturierung der Maskenschicht kann die zur Strukturierung verwendete Maske entfernt werden, um bei der nachfolgenden Implantation eine Abschattung durch die Maske zu vermeiden. Damit ist das erfindungsgemäße Verfahren auch bei Grabenweiten anwendbar, die deutlich kleiner sein kön¬ nen als in der aus DE 42 14 923 AI bekannten Speicherzel¬ lenanordnung.- After structuring the mask layer, the mask used for structuring can be removed in order to avoid shadowing by the mask during the subsequent implantation. The method according to the invention can thus also be used for trench widths which can be significantly smaller than in the storage cell arrangement known from DE 42 14 923 A1.
- Wird die Maske zur Strukturierung der Maskenschicht aus Photolack gebildet, so muß der Photolack bei der Belichtung zur Programmierung nicht bis auf den Boden des Grabens durchbelichtet werden. Damit können in dem erfindungsgemä- ßen Verfahren auch moderne Belichtungsstepper verwendet werden, die eine Fokustiefe von < 0,5 um aufweisen. Da die Maskenschicht am Boden des Grabens nicht unbedingt entfernt werden muß, kann in dem erfindungsgemäßen Verfahren am Gra¬ benboden unbelichteter Photolack verbleiben. Damit werden Belichtungsprobleme über die volle Topologie des Grabens vermieden.- If the mask for structuring the mask layer is formed from photoresist, the photoresist does not have to be exposed to the bottom of the trench during the exposure for programming. Modern exposure steppers with a focus depth of <0.5 μm can thus also be used in the method according to the invention. Because the mask layer at the bottom of the trench is not necessarily removed unexposed photoresist can remain on the bottom of the trench in the method according to the invention. This avoids exposure problems over the full topology of the trench.
- Bei Bildung der Dotierstoffgebiete durch Ausdiffusion aus einer dotierten Schicht wird diese im Gegensatz zu dem aus US-PS 4 663 644 bekannten Verfahren nicht strukturiert. Da¬ mit werden Probleme, die bei der Strukturierung über die Topologie des Grabens auftreten, vermieden.In contrast to the method known from US Pat. No. 4,663,644, when the dopant regions are formed by diffusion out of a doped layer, this is not structured. This avoids problems that arise when structuring via the topology of the trench.
Im folgenden wird die Erfindung anhand eines Ausführungsbei- spiels und der Figuren näher erläutert.The invention is explained in more detail below with the aid of an exemplary embodiment and the figures.
Figur 1 zeigt ein Substrat mit einer von einem ersten Leitfä¬ higkeitstyp dotierten Wanne.FIG. 1 shows a substrate with a trough doped with a first conductivity type.
Figur 2 zeigt das Substrat nach der Ätzung von streifenförmi- gen Gräben.FIG. 2 shows the substrate after the etching of stripe-shaped trenches.
Figur 3 zeigt das Substrat nach der Bildung streifenförmiger dotierter Gebiete an den Böden der Gräben und zwi¬ schen benachbarten Gräben an der Hauptfläche.FIG. 3 shows the substrate after the formation of stripe-shaped doped regions on the bottoms of the trenches and between adjacent trenches on the main surface.
Figur 4 zeigt das Substrat nach dem Aufbringen einer Masken¬ schicht und der Bildung einer Maske.FIG. 4 shows the substrate after the application of a mask layer and the formation of a mask.
Figur 5 zeigt das Substrat nach Strukturierung der Masken¬ schicht.FIG. 5 shows the substrate after structuring the mask layer.
Figur 6 zeigt das Substrat nach dem Aufbringen einer dotier¬ ten Schicht.FIG. 6 shows the substrate after the application of a doped layer.
Figur 7 zeigt das Substrat nach der Bildung von Dotierstoff- gebieten in den Flanken der Gräben und nach Bildung von quer zu den Gräben verlaufenden Wortleitungen. Figur 8 zeigt eine Aufsicht auf das Substrat nach Bildung der Wortleitungen.FIG. 7 shows the substrate after the formation of dopant regions in the flanks of the trenches and after the formation of word lines running transversely to the trenches. FIG. 8 shows a plan view of the substrate after the word lines have been formed.
Die Darstellungen in den Figuren sind nicht maßstäblich.The representations in the figures are not to scale.
In einem Substrat 1 aus zum Beispiel p-dotiertem monokri¬ stallinem Silizium mit einer Dotierstoffkonzentration von 5 x lθl5 cm"3 wird in einer Hauptfläche 2 durch Implantation und anschließendes Tempern eine p-dotierte Wanne 3 mit einer Do- tierstoffkonzentration von 2 x 10-*-7 cm~^ erzeugt (siehe Figur 1) . Bei der Implantation der p-dotierten Wanne 3 wird ein Streuoxid in einer Dicke von zum Beispiel 50 nm (nicht darge¬ stellt) verwendet, das nach dem Eintreiben der p-dotierten Wanne 3 mit 180 keV, 7 x 10^2 cm~2 wieder entfernt wird. Die p-dotierte Wanne 3 erstreckt sich mindestens über einen Be¬ reich für ein Zellenfeld.In a substrate 1 of, for example, p-doped silicon with a dopant concentration monokri¬ stallinem of 5 x lθl5 cm "3 is in a major surface 2 by implantation and subsequent heat-doped p-a trough 3 with a dopant concentration of 2 x 10- * - 7 cm ~ ^ generated (see Figure 1.) When implanting the p-doped well 3, a scattering oxide with a thickness of, for example, 50 nm (not shown) is used, which after driving in the p-doped well 3 with 180 keV, 7 x 10 ^ 2 cm ~ 2. The p-doped well 3 extends at least over an area for one cell field.
Auf der Hauptfläche 2 wird eine Siθ2"Schicht in einer Schichtdicke von zum Beispiel 300 nm zum Beispiel in einem TEOS-Verfahren abgeschieden. Mit Hilfe photolithographischer Prozeßschritte wird die Siθ2-Schicht strukturiert, wobei eine Grabenmaske 4 gebildet wird. Die Graben aske 4 weist strei- fenförmige Öffnungen auf, die im wesentlichen parallel ver¬ laufen. Die streifenförmigen Öffnungen in der Grabenmaske 4 weisen eine Breite von zum Beispiel 0,4 um, eine Länge von zum Beispiel 125 μm und einen Abstand von 0,4 μm auf.An SiO 2 "layer is deposited on the main surface 2 in a layer thickness of, for example, 300 nm, for example in a TEOS process. The SiO 2 layer is structured with the aid of photolithographic process steps, a trench mask 4 being formed. The trench mask 4 has stripes The strip-shaped openings in the trench mask 4 have a width of, for example, 0.4 μm, a length of, for example, 125 μm and a distance of 0.4 μm.
Unter Verwendung der Grabenmaske 4 als Ätzmaske werden in ei¬ nem anisotropen Ätzprozeß zum Beispiel mit HBr, He, O2, NF3 in die Hauptflache 2 des Substrats 1 Gräben 5 geätzt. DieUsing the trench mask 4 as an etching mask, trenches 5 are etched into the main surface 2 of the substrate 1 in an anisotropic etching process, for example using HBr, He, O2, NF3. The
Gräben 5 weisen entsprechend den Öffnungen der Grabenmaske 4 parallel zur Hauptfläche 2 einen streifenförmigen Querschnitt auf. Sie weisen eine Weite von zum Beispiel 0,4 μm, eine Län¬ ge von zum Beispiel 125 μm und einen Abstand von zum Beispiel 0,4 μm auf. Die Tiefe der Gräben beträgt zum Beispiel 0,6 μm (siehe Figur 2) . Es werden zum Beispiel 32 parallele Gräben 5 gebildet. Anschließend wird die Grabenmaske 4 mit zum Beispiel HF-Dip abgelöst. Um die Qualität der Kristalloberflächen zu verbes¬ sern, wird durch thermische Oxidation eine Siθ2-Schicht 6 (sogenanntes sacrificial oxide) in einer Dicke von zum Bei¬ spiel 20 nm erzeugt (siehe Figur 3) . Durch konforme Abschei¬ dung zum Beispiel in einem TEOS-Verfahren einer Siθ2-Schicht in einer Schichtdicke von zum Beispiel 60 nm und anschließen¬ des anisotropes Trockenätzen mit CHF3, O2 werden an senkrech- ten Flanken der Gräben 5 Siθ2-Spacer 7 erzeugt (siehe Figur 3) . Anschließend wird ein dünnes Streuoxid in einem TEOS- Verfahren abgeschieden (nicht dargestellt) . Durch Implantati¬ on senkrecht zur Hauptfläche 2 mit As mit einer Dosis von 5 x 10^5 cm~2 und einer Energie von 80 keV und einen anschließen- den Temperschritt zur Dotierstoffaktivierung werden am Boden der Gräben 5 und an der Hauptfläche 2 zwischen benachbarten Gräben 5 n+-dotierte, streifenförmige Gebiete 8 gebildet. In den streifenförmigen, dotierten Gebieten 8 wird eine Dotier¬ stoffkonzentration von zum Beispiel 10^1 cm~3 eingestellt. Bei der Implantation wirkt die Siθ2-Schicht 6 als Streuoxid.Trenches 5 have a strip-shaped cross section corresponding to the openings of the trench mask 4 parallel to the main surface 2. They have a width of for example 0.4 μm, a length of for example 125 μm and a distance of for example 0.4 μm. The depth of the trenches is, for example, 0.6 μm (see FIG. 2). For example, 32 parallel trenches 5 are formed. The trench mask 4 is then removed using, for example, HF dip. In order to improve the quality of the crystal surfaces, an SiO 2 layer 6 (so-called sacrificial oxide) with a thickness of, for example, 20 nm is produced by thermal oxidation (see FIG. 3). By conformal deposition, for example in a TEOS process, of a SiO 2 layer in a layer thickness of, for example, 60 nm and subsequent anisotropic dry etching with CHF3, O2, 5 SiO 2 spacers 7 are produced on vertical flanks of the trenches (see Figure 3). A thin scattering oxide is then deposited in a TEOS process (not shown). By implantation perpendicular to the main surface 2 with As with a dose of 5 × 10 ^ 5 cm ~ 2 and an energy of 80 keV and a subsequent tempering step for dopant activation, the trenches 5 on the bottom and on the main surface 2 between adjacent trenches 5 n + -doped, strip-shaped regions 8 are formed. In the strip-shaped doped regions 8 a dopes will concentration of, for example, 10 ^ 1 cm ~ 3 is set. During implantation, the SiO 2 layer 6 acts as a scatter oxide.
Anschließend werden die Siθ2-Spacer 7 und die Siθ2-Schicht 6 zum Beispiel durch naßchemisches Ätzen mit HF-Dip entfernt. Es wird eine Maskenschicht 9 mit im wesentlichen konformer Kantenbedeckung zum Beispiel in einem TEOS-Verfahren aus Siθ2 abgeschieden. Die Maskenschicht 9 wird in einer Schichtdicke von 60 bis 80 nm abgeschieden (siehe Figur 4) .The SiO 2 spacers 7 and the SiO 2 layer 6 are then removed, for example by wet chemical etching with HF dip. A mask layer 9 with an essentially conformal edge covering is deposited from SiO 2, for example in a TEOS process. The mask layer 9 is deposited in a layer thickness of 60 to 80 nm (see FIG. 4).
Anschließend wird eine Maske 10 zum Beispiel aus Photolack unter Verwendung photolithographischer Prozeßschritte gebil¬ det. Die Maske 10 weist im Zellenfeld Öffnungen 11 auf. Der Bereich außerhalb des Zellenfeldes, in dem zum Beispiel eine Peripherie für die Speicherzellenanordnung gebildet wird, wird von der Maske 10 abgedeckt. Die Öffnungen 11 werden so justiert, daß sie jeweils mindestens eine Flanke der Gräben 5 überlappen. Die Abmessungen der Öffnungen 11 parallel zur Hauptfläche 2 entsprechen jeweils der Weite der Gräben 5. Größere Abmessungen der Öffnungen 11 kommen durch das Zusam¬ menfallen benachbarter Öffnungen zustande. Die Maske 10 wird so justiert, daß die Öffnungen 11 jeweils überlappend zu den Flanken der Gräben 5 angeordnet sind. Werden die Gräben 5 mit einer Weite entsprechend der in der jeweiligen Technologie minimal herstellbaren Strukturgröße F von zum Beispiel 0,4 um gebildet, so weisen die Öffnungen 11 ebenfalls minimale Ab¬ messungen von F x F auf. Bei der Justierung der Maske 10 wird in diesem Fall ausgenutzt, daß die Justiergenauigkeit jeweils größer ist als die in der jeweiligen Technologie kleinste herstellbare Strukturgröße F. In einer 0,4 um-Technologie be¬ trägt die Justiergenauigkeit beispielsweise F/2 bis F/3.A mask 10 is then formed, for example, from photoresist using photolithographic process steps. The mask 10 has openings 11 in the cell field. The area outside the cell field, in which, for example, a periphery for the memory cell arrangement is formed, is covered by the mask 10. The openings 11 are adjusted so that they overlap at least one flank of the trenches 5. The dimensions of the openings 11 parallel to the main surface 2 each correspond to the width of the trenches 5. Larger dimensions of the openings 11 result from the collapse of adjacent openings. The mask 10 is adjusted so that the openings 11 are arranged to overlap the flanks of the trenches 5. If the trenches 5 are formed with a width corresponding to the structure size F that can be produced in the respective technology, for example 0.4 μm, then the openings 11 likewise have minimal dimensions of F x F. In the case of the adjustment of the mask 10, use is made of the fact that the adjustment accuracy is greater than the structure size F that can be produced in the respective technology. In a 0.4 μm technology, the adjustment accuracy is, for example, F / 2 to F / 3 .
In einem anisotropen Ätzverfahren zum Beispiel mit HBr, CI2, He wird die Maskenschicht 9 strukturiert. Die Maske 10 wirkt dabei als Ätzmaske. Dabei verbleiben im Bereich der Öffnungen 11 an den Flanken der Gräben 5 Ätzreste 9'. Im Bereich der Öffnungen 11 wird die Siliziumoberfläche an den Böden der Gräben 5 und an der Hauptfläche 2 zwischen benachbarten Grä- ben 5 freigelegt. Unter der Maske 10 wird die Maskenschicht 9 dagegen nicht angegriffen.The mask layer 9 is structured in an anisotropic etching process, for example using HBr, CI2, He. The mask 10 acts as an etching mask. In this case, 5 etching residues 9 'remain in the region of the openings 11 on the flanks of the trenches. In the area of the openings 11, the silicon surface is exposed on the bottoms of the trenches 5 and on the main surface 2 between adjacent trenches 5. Under the mask 10, however, the mask layer 9 is not attacked.
Die Strukturierung der Maskenschicht 9 erfolgt zwar in einem zu Silizium selektiven Ätzverfahren. Wegen der begrenzten Se- lektivitat kommt es jedoch dennoch zu einem Ätzangriff auf die freigelegten Oberflächen aus Silizium. Da an den Flanken der Gräben 5 die Ätzreste 9' verbleiben, wird der aufgrund der endlichen Selektivität unvermeidbare Ätzangriff auf die freigelegten Siliziumoberflächen reduziert.The patterning of the mask layer 9 takes place in an etching process which is selective for silicon. However, due to the limited selectivity, there is an etching attack on the exposed silicon surfaces. Since the etching residues 9 ′ remain on the flanks of the trenches 5, the etching attack on the exposed silicon surfaces that is unavoidable due to the finite selectivity is reduced.
Die Höhe der Ätzreste 9' ist geringer, als es der Tiefe der an der Hauptfläche 2 angeordneten streifenförmigen, dotierten Gebiete 8 entspricht. Die Höhe der Ätzreste 9' beträgt zum Beispiel 300 nm. Die exakte Höhe der Ätzreste 9' ist dabei unkritisch, solange ein Teil der Grabenwand unterhalb des an die Grabenwand angrenzenden streifenförmigen dotierten Gebie¬ tes 8 freigelegt wird. Von der Maske 10 freigelegte Teile der Maskenschicht 9 am Bo¬ den der Gräben 5 werden bei der Strukturierung der Masken¬ schicht 9 entfernt. Für den Fall, daß bei der Bildung der Maske 10 aus Photolack der Photolack nicht bis zum Boden der Gräben 5 durchbelichtet worden ist, ist die Maskenschicht 9 am Boden der Gräben 5 von unbelichtete Photolack bedeckt. In diesem Fall wird die Maskenschicht 9 bei dem anisotropen Ät¬ zen am Boden der Gräben 5 nicht angegriffen und der Boden der Gräben 5 bleibt von der Maskenschicht 9 bedeckt. Dieses ist für den weiteren Ablauf des erfindungsgemäßen Verfahrens un¬ kritisch. Nach der Strukturierung der Maskenschicht 9, 9' wird die Maske 10 entfernt (siehe Figur 5) .The height of the etching residues 9 ′ is less than the depth of the strip-shaped, doped regions 8 arranged on the main surface 2. The height of the etching residues 9 'is, for example, 300 nm. The exact height of the etching residues 9' is not critical as long as part of the trench wall is exposed below the strip-shaped doped region 8 adjacent to the trench wall. Parts of the mask layer 9 exposed at the bottom of the trenches 5 by the mask 10 are removed during the structuring of the mask layer 9. In the event that when the mask 10 is formed from photoresist, the photoresist has not been exposed to the bottom of the trenches 5, the mask layer 9 at the bottom of the trenches 5 is covered by unexposed photoresist. In this case, the mask layer 9 is not attacked during the anisotropic etching at the bottom of the trenches 5 and the bottom of the trenches 5 remains covered by the mask layer 9. This is not critical for the further course of the method according to the invention. After the mask layer 9, 9 'has been structured, the mask 10 is removed (see FIG. 5).
Anschließend wird ein dünnes Streuoxid (ca. 10 nm) mit einem TEOS-Verfahren abgeschieden (nicht dargestellt) .A thin scattering oxide (approx. 10 nm) is then deposited using a TEOS process (not shown).
Anschließend werden zwei gewinkelte Implantationen mit Bor mit einer Dosis von 10^3 c ~2 bis 5 x 10^- cm~2 und einer Energie von 60 keV durchgeführt. Dabei beträgt der Neigungs¬ winkel gegen die Normale der Hauptfläche 2 20° bis 30°, und - 20° bis - 30°. Dabei werden in den freiliegenden Flanken der Gräben 5 oberhalb der Ätzreste 9' Dotierstoffgebiete 12 gebildet (siehe Figur 7) . In den Dotierstoffgebieten 12 wird eine Dotierstoffkonzentration von einigen 1017 cm~3, vorzugs¬ weise 8 x 10^7 cm~3f eingestellt. Da die Dotierung in den streifenförmigen dotierten Gebieten 8 10^1 cm"3 beträgt, kann die Implantation von Bor in diesem Bereich toleriert werden. Für den Fall, daß bei der Bildung der Maske 10 am Boden der Gräben 5 unbelichteter Photolack verblieben ist und die Böden der Gräben 5 mit der Maskenschicht 9 bedeckt sind, erfolgt keine Implantation von Bor in die am Boden der Gräben 5 ange¬ ordneten streifenförmigen dotierten Gebiete 8. Die Bildung der Dotierstoffgebiete 12 in den freiliegenden Flanken der Gräben 5 ist davon nicht beeinträchtigt. Alternativ werden die Dotierstoffgebiete 12 in den Flanken der Gräben 5 durch Ausdiffusion aus einer dotierten Schicht 13 gebildet. Dazu wird nach Entfernen der Maske 10 ganzflä¬ chig die dotierte Schicht 13 zum Beispiel aus Borsilikatglas in einer Schichtdicke von 50 nm abgeschieden (siehe Figur 6) . In einem Temperschritt bei zum Beispiel 900° werden die Do¬ tierstoffgebiete 12 durch Ausdiffusion erzeugt. Anschließend wird die dotierte Schicht 13 zum Beispiel mit HF-Dip ent¬ fernt.Then two angled implantations with boron are carried out with a dose of 10 ^ 3 c ~ 2 to 5 x 10 ^ - cm ~ 2 and an energy of 60 keV. The angle of inclination relative to the normal of the main surface 2 is 20 ° to 30 °, and - 20 ° to - 30 °. In this case, dopant regions 12 are formed in the exposed flanks of the trenches 5 above the etching residues 9 '(see FIG. 7). In the Dotierstoffgebieten 12 is a dopant concentration of some 10 17 cm -3, 8 x 10 ^ preferred wise adjusted to 7 cm ~ 3 f. Since the doping in the stripe-shaped doped regions is 8 10 ^ 1 cm "3, the implantation of boron in this area can be tolerated. In the event that when the mask 10 is formed, 5 unexposed photoresist remains at the bottom of the trenches and the Bottoms of the trenches 5 are covered with the mask layer 9, boron is not implanted into the strip-shaped doped regions 8 arranged at the bottom of the trenches 5. The formation of the dopant regions 12 in the exposed flanks of the trenches 5 is not impaired by this. Alternatively, the dopant regions 12 are formed in the flanks of the trenches 5 by diffusion out of a doped layer 13. For this purpose, after removing the mask 10, the doped layer 13, for example made of borosilicate glass, is deposited over the entire surface in a layer thickness of 50 nm (see FIG. 6). In a tempering step at 900 ° for example, the doping areas 12 are produced by out-diffusion. Subsequently, the doped layer 13 is removed, for example with an HF dip.
Durch naßchemisches Ätzen mit HF werden anschließend die strukturierte Maskenschicht 9 und die Ätzreste 9' entfernt (siehe Figur 7) . Es wird ein Gatedielektrikum 14 zum Beispiel durch thermische Oxidation in einer Schichtdicke von zum Bei- spiel 10 nm erzeugt. Anschließend wird ganzflächig eine n+- dotierte Polysiliziumschicht in einer Schichtdicke von 400 nm aufgebracht. Dieses erfolgt vorzugsweise durch in situ do¬ tiertes Abscheiden von Polysilizium. Alternativ wird die Po¬ lysiliziumschicht undotiert abgeschieden und anschließend durch Belegung mit einer POCL-Schicht (POCL steht für PCI3: Phosphor-Chlorid-Gas) dotiert. Mit Hilfe photolithographi¬ scher Prozeßschritte wird die dotierte Polysiliziumschicht durch anisotropes Ätzen strukturiert. Dabei entstehen Wort¬ leitungen 15, die quer zu den Gräben 5 verlaufen (siehe Figur 7 und Figur 8) . Die Wortleitungen 15 weisen eine Breite von zum Beispiel F = 0,4 μm auf. Der Abstand zwischen benachbar¬ ten Wortleitungen 15 beträgt ebenfalls F.The structured mask layer 9 and the etching residues 9 'are then removed by wet chemical etching with HF (see FIG. 7). A gate dielectric 14 is produced, for example by thermal oxidation, in a layer thickness of 10 nm, for example. An n + -doped polysilicon layer is then applied over the entire surface in a layer thickness of 400 nm. This is preferably done by in situ doped polysilicon. Alternatively, the polysilicon layer is deposited undoped and then doped by covering it with a POCL layer (POCL stands for PCI3: phosphorus chloride gas). With the help of photolithographic process steps, the doped polysilicon layer is structured by anisotropic etching. This results in word lines 15 which run transversely to the trenches 5 (see FIG. 7 and FIG. 8). The word lines 15 have a width of, for example, F = 0.4 μm. The distance between adjacent word lines 15 is also F.
Die vertikalen MOS-Transistoren werden jeweils aus zwei streifenförmigen dotierten Gebieten 8, die an dieselbe Flanke eines der Gräben 5 angrenzen, der dazwischen angeordnete Teil der Wanne 3 als Kanalgebiet, das Gatedielektrikum 14 und der daran angrenzende Teil einer der Wortleitungen 15 gebildet. Die Ausdehnung des vertikalen MOS-Transistors parallel zum Verlauf der streifenförmigen Gräben 5 ist durch die Breite der Wortleitungen 15 gegeben. Entlang einer Flanke eines der Gräben benachbarte MOS-Transistoren sind durch den Abstand zwischen benachbarten Wortleitungen 15 voneinander getrennt. Die streifenförmigen dotierten Gebiete 8 verlaufen jeweils über das gesamte Zellenfeld. Sie bilden Leitungen, die je nach Beschaltung als Bitleitung oder Referenzleitung einge- setzt werden und die die Source/Drain-Gebiete von entlang ei¬ nem Graben benachbarten MOS-Transistoren miteinander verbin¬ den.The vertical MOS transistors are each formed from two strip-shaped doped regions 8 which adjoin the same flank of one of the trenches 5, the part of the trough 3 arranged in between as a channel region, the gate dielectric 14 and the part of one of the word lines 15 adjoining it. The extent of the vertical MOS transistor parallel to the course of the strip-shaped trenches 5 is given by the width of the word lines 15. MOS transistors that are adjacent along an edge of one of the trenches are separated by the distance between adjacent word lines 15 separated from each other. The strip-shaped doped regions 8 each run over the entire cell field. They form lines which, depending on the circuitry, are used as bit lines or reference lines and which connect the source / drain regions of MOS transistors adjacent along a trench.
Je nachdem, ob in der Flanke des jeweiligen Grabens 5 ein Do- tierstoffgebiet 12 angeordnet ist oder nicht, weist der ver¬ tikale MOS-Transistor eine erhöhte Einsatzspannung auf oder nicht. Die in der Speicherzellenanordnung gespeicherte Infor¬ mation ist in dem Vorhandensein oder NichtVorhandensein der Dotierstoffgebiete 12 gespeichert. Die Programmierung der Speicherzellenanordnung erfolgt daher bei der Strukturierung der Maskenschicht 9. Über die Anordnung der Öffnungen 11 in der Maske 10 wird die Information in die Speicherzellenanord¬ nung übertragen.Depending on whether or not a doping region 12 is arranged in the flank of the respective trench 5, the vertical MOS transistor has an increased threshold voltage or not. The information stored in the memory cell arrangement is stored in the presence or absence of the dopant regions 12. The programming of the memory cell arrangement is therefore carried out when the mask layer 9 is structured. The arrangement of the openings 11 in the mask 10 transfers the information into the memory cell arrangement.
Zum Auslesen der Speicherzellen werden die streifenförmigen dotierten Gebiete 8 als Bit- bzw. Referenzleitung verwendet. Die zu bewertende Speicherzelle wird über die Wortleitung ausgewählt. An die Wortleitung wird dabei ein Steuersignal angelegt, dessen Spannungspegel zwischen der Einsatzspannung der MOS-Transistoren mit Dotierstoffgebiet 12 im Kanalbereich und der der MOS-Transistoren ohne Dotierstoffgebiet 12 im Ka¬ nalbereich liegt. Bei diesem Steuersignal werden die MOS- Transistoren ohne Dotierstoffgebiet 12 im Kanalbereich lei¬ tend, während die MOS-Transistoren mit Dotierstoffgebiet 12 im Kanalbereich, die eine erhöhte Einsatzspannung aufweisen, weiterhin sperren. Beim Auslesen wird bewertet, ob zwischen den zugehörigen streifenförmigen dotierten Gebieten 8 ein Strom fließt oder nicht.The strip-shaped doped regions 8 are used as bit or reference lines for reading out the memory cells. The memory cell to be evaluated is selected via the word line. A control signal is applied to the word line, the voltage level of which lies between the threshold voltage of the MOS transistors with dopant region 12 in the channel region and that of the MOS transistors without dopant region 12 in the channel region. With this control signal, the MOS transistors without dopant region 12 in the channel region become conductive, while the MOS transistors with dopant region 12 in the channel region, which have an increased threshold voltage, continue to block. When reading out, it is evaluated whether a current flows between the associated strip-shaped doped regions 8 or not.
In Figur 8 ist eine Aufsicht auf die Speicherzellenanordnung dargestellt. Es ist der Verlauf der Wortleitungen 15 quer zu den Gräben 5 dargestellt. Ferner sind die streifenförmigen, dotierten Gebiete 8 eingetragen, die am Boden der Gräben 5 sowie zwischen benachbarten Gräben 5 verlaufen. Als gestri¬ chelte Kontur sind Dotierstoffgebiete 12 in den Flanken der Gräben eingetragen.FIG. 8 shows a top view of the memory cell arrangement. The course of the word lines 15 across the trenches 5 is shown. Furthermore, the stripe-shaped, doped areas 8 entered, which run at the bottom of the trenches 5 and between adjacent trenches 5. Doping regions 12 are entered in the flanks of the trenches as a dashed contour.
Jede Speicherzelle umfaßt einen vertikalen MOS-Transistor, der parallel zum Verlauf der streifenförmigen Gräben 5 eine Ausdehnung von 2 F, senkrecht zum Verlauf der streifenförmi¬ gen Gräben 5 eine Ausdehnung von F aufweist. Der Platzbedarf pro Speicherzelle beträgt daher 2 F2.Each memory cell comprises a vertical MOS transistor, which has an extent of 2 F parallel to the course of the stripe-shaped trenches 5 and an extent of F perpendicular to the course of the stripe-shaped trenches 5. The space requirement per memory cell is therefore 2 F 2 .
Die Herstellung der Speicherzellenanordnung wird abgeschlos¬ sen mit der Abscheidung eines Zwiεchendielektrikums, der Öff¬ nung von Kontaktlöchern und der Herstellung einer Metallisie- rung (nicht dargestellt) . The production of the memory cell arrangement is concluded with the deposition of an intermediate dielectric, the opening of contact holes and the production of a metallization (not shown).

Claims

Patentansprüche claims
1. Speicherzellenanordnung1. Memory cell arrangement
- bei der in einem Substrat (1) , das mindestens im Bereich einer Hauptfläche (2) von einem ersten Leitfähigkeitstyp dotiertes Halbleitermaterial umfaßt, Speicherzellen vorge¬ sehen sind, die jeweils einen zur Hauptfläche vertikalen MOS-Transistor umfassen,memory cells are provided in a substrate (1), which comprises semiconductor material doped with a first conductivity type at least in the area of a main surface (2), each comprising a MOS transistor vertical to the main surface,
- bei der die vertikalen MOS-Transistoren je nach gespeicher¬ ter Information unterschiedliche Einsatzspannungen aufwei¬ sen,in which the vertical MOS transistors have different threshold voltages depending on the stored information,
- bei der in dem Substrat (1) streifenförmige, im wesentli¬ chen parallel verlaufende Gräben (5) vorgesehen sind,in which strip-shaped trenches (5) which run essentially parallel are provided in the substrate (1),
- bei der am Boden der Gräben (5) und an der Hauptfläche (2) zwischen benachbarten Gräben (5) streifenförmige dotierte Gebiete (8) angeordnet sind, die von einem zweiten, dem er¬ sten entgegengesetzten Leitfähigkeitstyp dotiert sind,in which strip-shaped doped regions (8) are arranged on the bottom of the trenches (5) and on the main surface (2) between adjacent trenches (5), which are doped with a second conductivity type opposite to the first,
- bei der an den Flanken der Gräben (5) ein Gatedielektrikum (14) angeordnet ist,- A gate dielectric (14) is arranged on the flanks of the trenches (5),
- bei der Wortleitungen (15) vorgesehen sind, die quer zu den Gräben (5) verlaufen,- The word lines (15) are provided, which run transversely to the trenches (5),
- bei der die vertikalen MOS-Transistoren jeweils aus zwei an dieselbe Flanke eines der Gräben (5) angrenzenden streifen¬ förmige dotierte Gebiete (8) , die dazwischen angeordnete Flanken des Grabens, das Gatedielektrikum (14) und eine der Wortleitungen (15) gebildet werden,- In which the vertical MOS transistors are each formed from two strip-shaped doped regions (8) adjacent to the same flank of one of the trenches (5), the flanks of the trench arranged between them, the gate dielectric (14) and one of the word lines (15) become,
- bei der die Speicherzellen, in denen eine vorbestimmte In¬ formation gespeichert ist, im oberen Bereich der Flanke des Grabens (5) ein Dotierstoffgebiet (12) aufweisen, dessen Ausdehnung senkrecht zur Hauptfläche (2) geringer als die Tiefe der Gräben (5) ist.- in which the memory cells, in which a predetermined information is stored, have a dopant region (12) in the upper region of the flank of the trench (5), the Expansion perpendicular to the main surface (2) is less than the depth of the trenches (5).
2. SpeicherZeilenanordnung nach Anspruch 1,2. Memory line arrangement according to claim 1,
- bei der der Abstand zwischen benachbarten Gräben (5) gleich der Breite der Gr ben (5) ist,- in which the distance between adjacent trenches (5) is equal to the width of the trenches (5),
- bei der der Abstand zwischen benachbarten Wortleitungen (15) gleich der Breite der Wortleitungen (15) ist.- In which the distance between adjacent word lines (15) is equal to the width of the word lines (15).
3. Verfahren zur Herstellung einer Speicherzellenanordnung,3. Method for producing a memory cell arrangement,
- bei dem in einer Hauptfläche (2) eines Substrats (1), das mindestens im Bereich der Hauptfläche (2) von einem ersten- In which in a main surface (2) of a substrate (1), at least in the region of the main surface (2) of a first
Leitfähigkeitstyp dotiertes Halbleitermaterial umfaßt, streifenförmige Gräben (5) gebildet werden, die im wesent¬ lichen parallel verlaufen,Comprises conductivity-type doped semiconductor material, strip-shaped trenches (5) are formed which run essentially parallel,
- bei dem am Boden der Gräben (5) und an der Hauptfläche (2) zwischen benachbarten Gräben (5) streifenförmige dotierte Gebiete (8) gebildet werden, die von einem zweiten, zum er¬ sten entgegengesetzten Leitfähigkeitstyp dotiert sind,in which strip-shaped doped regions (8) are formed on the bottom of the trenches (5) and on the main surface (2) between adjacent trenches (5), which are doped with a second conductivity type opposite to the first,
- bei dem eine Maskenschicht (9) mit im wesentlichen konfor¬ mer Kantenbedeckung aufgebracht wird,- in which a mask layer (9) with an essentially conformal edge covering is applied,
- bei dem auf der Maskenschicht (9) eine Maske (10) erzeugt wird, die Öffnungen (11) aufweist,- In which a mask (10) is produced on the mask layer (9), which has openings (11),
- bei dem die Maskenschicht (9) unter Verwendung der Maske- In which the mask layer (9) using the mask
(10) durch anisotropes Ätzen so strukturiert wird, daß im Bereich der Öffnungen (11) die Flanken von Gräben (5) teil¬ weise freigelegt werden, so daß an diesen Flanken ein Rest der Maskenschicht (9') verbleibt, 19(10) is structured by anisotropic etching in such a way that the flanks of trenches (5) are partially exposed in the area of the openings (11), so that a remainder of the mask layer (9 ') remains on these flanks, 19
- bei dem in den freigelegten Flankenteilen Dotierstoffgebie¬ te (12) erzeugt werden,- in which dopant regions (12) are generated in the exposed flank parts,
- bei dem nach Entfernen der strukturierten Maskenschicht (9, 9') an den Flanken der Gräben (5) ein Gatedielektrikum (14) gebildet wird,in which a gate dielectric (14) is formed on the flanks of the trenches (5) after the structured mask layer (9, 9 ') has been removed,
- bei dem Wortleitungen (15) gebildet werden, die quer zu den Gräben verlaufen.- In the word lines (15) are formed, which run across the trenches.
4. Verfahren nach Anspruch 3, bei dem die Dotierstoffgebiete (12) in den freigelegten Flan¬ kenteilen durch eine gewinkelte Implantation gebildet werden.4. The method according to claim 3, wherein the dopant regions (12) are formed in the exposed flank parts by an angled implantation.
5. Verfahren nach Anspruch 4, bei dem die Implantation mit einem Neigungswinkel im Bereich zwischen 20° und 30° und/ oder - 20° und - 30° gegen die Nor¬ male der Hauptfläche (2) erfolgt.5. The method according to claim 4, wherein the implantation is carried out with an inclination angle in the range between 20 ° and 30 ° and / or - 20 ° and - 30 ° against the normal of the main surface (2).
6. Verfahren nach Anspruch 3, bei dem zur Bildung der Dotierstoffgebiete (12) in den frei¬ gelegten Flankenteilen eine dotierte Schicht (13) aufgebracht wird, aus der in einem Temperschritt Dotierstoff ausdiffun¬ diert wird.6. The method according to claim 3, in which a doped layer (13) is applied from the exposed flank parts to form the dopant regions (12), from which dopant is diffused in a tempering step.
7. Verfahren nach Anspruch 6, bei dem die dotierte Schicht (13) aus dotiertem Glas, dotier¬ tem Polysilizium oder dotiertem amorphem Silizium gebildet wird.7. The method according to claim 6, in which the doped layer (13) is formed from doped glass, doped polysilicon or doped amorphous silicon.
8. Verfahren nach einem der Ansprüche 3 bis 7,8. The method according to any one of claims 3 to 7,
- bei dem nach der Bildung der Gräben (5) die Flanken der Gräben (5) mit Spacern (7) versehen werden, - bei dem die streifenförmigen dotierten Gebiete (8) durch eine Implantation gebildet werden, bei der die Spacer (7) an den Flanken der Gräben (5) maskierend wirken,- In which after the formation of the trenches (5), the flanks of the trenches (5) are provided with spacers (7), - in which the strip-shaped doped regions (8) are formed by an implantation in which the spacers (7) have a masking effect on the flanks of the trenches (5),
- bei dem die Spacer (7) nach Bildung der streifenförmigen dotierten Gebiete (8) entfernt werden. - In which the spacers (7) are removed after formation of the strip-shaped doped regions (8).
EP97915321A 1996-03-12 1997-03-03 Memory cell arrangement with vertical mos transistors and the production process thereof Ceased EP0886884A1 (en)

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DE19609678A1 (en) 1997-09-18
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KR19990087642A (en) 1999-12-27
US6180979B1 (en) 2001-01-30

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